An adaptive continuous‐time incremental Σ∆ ADC for neural recording implants.

Summary: In this paper, an analog‐to‐digital converter (ADC) with adaptive resolution is presented for wireless neural recording implants. The resolution of the ADC is changed according to the neural signal content, and for this purpose, a continuous‐time (CT) incremental sigma‐delta (IΣ∆) modulator is employed. The ADC digitizes the action potential (AP) and background noise (B‐noise) with 8‐bit and 3‐bit resolutions, respectively. An automatic AP detector is used to separate the APs from the B‐noise in order to select one of the two proportional resolutions. The power dissipation and output data rate of the ADC are reduced by using this technique. Analytical calculations and behavioral simulation results are provided to evaluate the performance of the proposed ADC. To further confirm its efficiency, the circuit‐level implementation of the CT IΣ∆ ADC is presented in Taiwan Semiconductor Manufacturing Company (TSMC) 90‐nm complementary metal‐oxide semiconductor (CMOS) process. According to the simulation results, the proposed ADC achieves 8‐bit or 3‐bit resolution adaptively with 10 kHz bandwidth while the average power consumption is less than 1.89 μW from a single 1‐V power supply. This paper presents an adaptive resolution analog‐to‐digital converter (ADC) for wireless neural recording implants. It employs a continuous‐time incremental sigma‐delta (IΣ∆) modulator with resolution corresponding to the neural signal content. The proposed ADC digitizes the action potential and background noise (B‐noise) with 8‐bit and 3‐bit resolutions, respectively. The power and data rate are reduced significantly because the neural signal contains the B‐Noise in the most of the time, and the ADC mostly operates in the 3‐bit resolution mode. [ABSTRACT FROM AUTHOR]