Hardware Protection via Logic Locking Test Points.

MLA

Chen, Michael, et al. “Hardware Protection via Logic Locking Test Points.” IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 37, no. 12, Dec. 2018, pp. 3020–30. EBSCOhost, https://doi.org/10.1109/TCAD.2018.2801240.

APA

Chen, M., Moghaddam, E., Mukherjee, N., Rajski, J., Tyszer, J., & Zawada, J. (2018). Hardware Protection via Logic Locking Test Points. IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, 37(12), 3020–3030. https://doi.org/10.1109/TCAD.2018.2801240

Chicago

Chen, Michael, Elham Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, and Justyna Zawada. 2018. “Hardware Protection via Logic Locking Test Points.” IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems 37 (12): 3020–30. doi:10.1109/TCAD.2018.2801240.