An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture.

This paper presents an energy-efficient network-on-chip (NoC)-based multi-core architecture for realizing a reconfigurable Viterbi decoder (VD). The proposed architecture can support a wide range of wireless communication standards that have varied constraint lengths. The energy efficiency in the proposed architecture has been primarily achieved by mapping the add–compare–select operations of the VD onto a $4\times 4$ ZMesh topology-based NoC and then by employing a reconfigurable memoryless survivor memory unit to decode the input symbols. When compared with the existing ASIC-based multi-core VD architectures, the proposed architecture achieves an improvement by at least 3.06 times in the energy consumption per decoded bit (EC) metric. Similarly, when compared with the state-of-the-art single-core VD architectures, the proposed architecture achieves an improvement by at least 4.99 times in the EC metric. [ABSTRACT FROM AUTHOR]