Design and evaluation of ZMesh topology for on-chip interconnection networks.

This article presents the design and evaluation of a scalable and energy efficient Network-on-Chip topology with diagonal links, called ZMesh. A heuristic technique for mapping applications onto the ZMesh topology has been proposed. Further, a mapping technique based on particle swarm optimization combined with simulated annealing has also been considered for a fair comparison of the performance of ZMesh with that of other topologies. Experimental evaluation shows that ZMesh when compared with baseline Mesh, shows an average improvement of up to 1.25 × and 1.20 × in energy consumption and execution time, respectively while running real application traces. Compared to the state-of-the-art topologies such as DMesh, ZMesh shows an average improvement of up to 2.39 × in terms of energy consumption, while suffering a degradation of up to 9.37% in execution time, for running real application traces. For the synthetic as well as real applications with more uniform traffic pattern, such as constant geometry algorithms, ZMesh achieves better energy efficiency than the other considered topologies. Evaluation of ZMesh for multicast kind of traffic using a proposed multicast routing algorithm shows improvement in link energy consumption by up to 55%, for the considered scenarios, as compared to unicast-based multicast routing. [ABSTRACT FROM AUTHOR]