Cite
A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%.
MLA
Laskar, Nivedita, et al. “A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%.” Journal of Circuits, Systems & Computers, vol. 27, no. 3, Mar. 2018, p. 1. EBSCOhost, https://doi.org/10.1142/S0218126618500494.
APA
Laskar, N., Debnath, S., Majumder, A., & Bhattacharyya, B. K. (2018). A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%. Journal of Circuits, Systems & Computers, 27(3), 1. https://doi.org/10.1142/S0218126618500494
Chicago
Laskar, Nivedita, Suman Debnath, Alak Majumder, and Bidyut Kumar Bhattacharyya. 2018. “A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%.” Journal of Circuits, Systems & Computers 27 (3): 1. doi:10.1142/S0218126618500494.