Compressed Sharer Tracking and Relinquishment Coherence for Superior Directory Efficiency of Chip Multiprocessors.

To lower on-chip SRAM area overhead for chip multiprocessors (CMPs), this work treats a novel directory design which compresses <underline>p</underline>resent-bit <underline>v</underline>ectors (PVs) by dropping “runs of zeros” commonly existing and lets PVs be transformed to their variations after sharer relinquishment for hashing alternative table sets to lift table utilization. Featured with <underline>re</underline>linquishment <underline>c </underline>oherence and <underline>co</underline>mpressed <underline>s</underline>harer <underline>t</underline> racking (ReCoST), the proposed design attains superior directory efficiency and maintains “exact” directory representations, as a result of dropping abound long runs of zeros present in PVs. According to full-system simulation using gem5 for a range of core counts under PARSEC benchmarks, ReCoST is found to enjoy 3.21 $\times$<alternatives><inline-graphic xlink:href="shu-ieq1-2698043.gif"/> </alternatives> (or 2.64$\times$<alternatives> <inline-graphic xlink:href="shu-ieq2-2698043.gif"/></alternatives>) more efficiency in directory storage than conventional bit-tracking directories (or the best directory known so far, called SCD) for a 64-core CMP under monotasking (or multitasking) workloads while ensuring execution slowdowns to stay within 2.4 percent (or 3.3 percent). [ABSTRACT FROM AUTHOR]