Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity.

MLA

Pudi, Vikramkumar, et al. “Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity.” IEEE Transactions on Computers, vol. 66, no. 10, Oct. 2017, pp. 1824–30. EBSCOhost, https://doi.org/10.1109/TC.2017.2696524.

APA

Pudi, V., Sridharan, K., & Lombardi, F. (2017). Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity. IEEE Transactions on Computers, 66(10), 1824–1830. https://doi.org/10.1109/TC.2017.2696524

Chicago

Pudi, Vikramkumar, K. Sridharan, and Fabrizio Lombardi. 2017. “Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity.” IEEE Transactions on Computers 66 (10): 1824–30. doi:10.1109/TC.2017.2696524.