A 2.25–2.7 GHz Area-Efficient Subharmonically Injection-Locked Fractional-N Frequency Synthesizer With a Fast-Converging Correlation Loop.

An area-efficient subharmonically injection-locked fractional-N frequency synthesizer is presented. The phase domain analysis confirms that a second-order subharmonically injection-locked phase-locked loop (SIPLL) can be stable even if the loop filter is composed of only a tiny capacitor. Thus, the area of the loop filter shrinks dramatically to realize an area-efficient SIPLL. Besides, a fast-converging correlation loop is used to calibrate the gain error of the digital-to-time converter in background by using a binary search algorithm. It ensures the initial output of the correlator close to the final one and is insensitive to process/supply/temperature variations. The chip is fabricated in a 40 nm process and occupies a core area of 0.0104 mm2. The converging time of the correlation loop is within 30~\mu \text s . The power consumption is 3.19 mW from a 1.1 V supply. [ABSTRACT FROM AUTHOR]