Cite
Sensitivity aware NSGA-II based Pareto front generation for the optimal sizing of analog circuits.
MLA
Kchaou, O.Bellaaj, et al. “Sensitivity Aware NSGA-II Based Pareto Front Generation for the Optimal Sizing of Analog Circuits.” Integration: The VLSI Journal, vol. 55, Sept. 2016, pp. 220–26. EBSCOhost, https://doi.org/10.1016/j.vlsi.2016.07.001.
APA
Kchaou, O. B., Garbaya, A., Kotti, M., Pereira, P., Fakhfakh, M., & Helena Fino, M. (2016). Sensitivity aware NSGA-II based Pareto front generation for the optimal sizing of analog circuits. Integration: The VLSI Journal, 55, 220–226. https://doi.org/10.1016/j.vlsi.2016.07.001
Chicago
Kchaou, O. Bellaaj, A. Garbaya, M. Kotti, P. Pereira, M. Fakhfakh, and M. Helena Fino. 2016. “Sensitivity Aware NSGA-II Based Pareto Front Generation for the Optimal Sizing of Analog Circuits.” Integration: The VLSI Journal 55 (September): 220–26. doi:10.1016/j.vlsi.2016.07.001.