The effect of the thickness of tunneling layer on the memory properties of high- k composite charge-trapping memory devices.

The charge-trapping memory devices namely Pt/Al2O3/(Al2O(Cu2O)/SiO2/-Si with 2, 3 and 4 nm SiO2 tunneling layers were fabricated by using RF magnetron sputtering and atomic layer deposition techniques. At an applied voltage of ±11 V, the memory windows in the C- V curves of the memory devices with 2, 3 and 4 nm SiO2 tunneling layers were about 4.18, 9.91 and 11.33 V, respectively. The anomaly in memory properties among the three memory devices was ascribed to the different back tunneling probabilities of trapped electrons in the charge-trapping dielectric (Al2O(Cu2O) due to the different thicknesses of SiO2 tunneling layer. [ABSTRACT FROM AUTHOR]