Análisis de la respuesta temporal del diseño de un controlador de SSRAM.

The digital systems are every day faster and more complex. Therefore, from the conception of a design until the validation of their operation, it is necessary to carry out a detailed time analysis. In that sense, this work has as central objective the analysis of the timing performance of a digital system, from the design until the verification. The memory controller was implemented in the EP3C25F324C6, FPGA of the family Cyclone III from Altera. The memory IS61LPS25636A, manufactured by ISSI (Integrated Silicon Solution, Inc.) was used. The design was focused to work with the greater clock frequency as possible. The analysis of the design was carried out using the simulation tools Modelsim and TimeQuest Timing Analyzer from Quartus II. It was obtained an SSRAM controller with a worst setup slack of 155 psfor a clock frequency of 190 MHz. [ABSTRACT FROM AUTHOR]