Nueva evaluación y propuesta de un esquema de sincronización para la conexión a la red de convertidores estáticos de potencia en presencia de perturbaciones de la red eléctrica.

The paper starts by casting new light to the existing Phase Lock Loop (PLL) schemes used to synchronize the static converters with the grid under utility disturbances. Two approaches are pursued to detect the fundamental harmonic of the positive-sequence component of the grid voltages in presence of the disturbances. Arithmetical approaches improve the operation of the basic PLL circuit by making robust the PLL algorithm. Structural approaches improve the operation of the basic PLL circuit by adding a block intended to cope with the disturbances. This paper considers the structural approach and shows that it works by either post processing the detected grid quantities or preprocessing the grid voltages. Afterwards, the paper proposes an improved PLL scheme termed as double processing (DP) PLL scheme since it includes preprocessing and post processing functionalities. By properly designing the scheme parameters, it is proved that the proposed scheme exhibits superior robustness against the utility disturbances. [ABSTRACT FROM AUTHOR]