Simulation native basée sur le support matériel à la virtualisation.

Since 2004, the trend in the semiconductor industry is to increase the number of cores. Circuits with tens or even hundreds of cores are currently available on the market, and circuits with thousands of cores are foreseen within the next few years. Virtual platforms are key tools for the design and validation of these circuits and to develop the software. To simulate processors in virtual platforms, interpretive instruction set simulation is the most widespread technique but it does not scale well with the increasing number of cores. In this paper, we extend a native simulation technique to handle of ad-hoc architectural specificities and study its scalability with respect to the number of cores. [ABSTRACT FROM AUTHOR]