A Power- and Area-Efficient Multirate Quasi-Cyclic LDPC Decoder.

In this paper, a power- and area-efficient, multirate, Quasi-cyclic, low-density, parity-check decoder is proposed. The proposed decoder design is based on a simplified adaptive normalized min-sum algorithm. The proposed algorithm effectively utilizes two correction factors for check-node and variable-node update processes. This corrects the channel errors at relatively low signal-to-noise ratio. In order to reduce the finite word length effects, a six-bit nonuniform quantization with the overlapped message passing scheme is used. In addition, an improved early termination scheme is also used to reduce the total number of decoding iterations. This reduces the overall power consumption of the decoder. The simulations have been carried out using Xilinx ISE 14.1 and implemented on Virtex 5 FPGA. The proposed decoder is synthesized using CADENCE with UMC 130 nm technology. With a core area of 1.16 mm $$^{2}$$ , the proposed decoder achieves a maximum throughput of 3.4 Gb/s for 15 decoding iterations with a power dissipation of 114.3 mW. [ABSTRACT FROM AUTHOR]