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Capacitance estimation for InAs Tunnel FETs by means of full-quantum [formula omitted] simulation.
- Source :
-
Solid-State Electronics . Jun2015, Vol. 108, p104-109. 6p. - Publication Year :
- 2015
-
Abstract
- We report for the first time a quantum mechanical simulation study of gate capacitance components in aggressively scaled InAs Nanowire Tunnel Field-Effect Transistors. It will be shown that the gate-drain capacitance exhibits the same functional dependence over the whole V gs range as the total gate capacitance, albeit with smaller values. However, as opposed to the previous capacitance estimations provided by semiclassical TCAD tools, we find that the gate capacitance exhibits a non-monotonic behavior vs. gate voltage, with plateaus and bumps related with energy quantization and subband formation determined by the device cross-sectional size, as well as with the position of channel-conduction subbands relative to the Fermi level in the drain contact. From this point of view, semiclassical TCAD tools seem to be inaccurate for capacitance estimation in aggressively-scaled TFET devices. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 00381101
- Volume :
- 108
- Database :
- Academic Search Index
- Journal :
- Solid-State Electronics
- Publication Type :
- Academic Journal
- Accession number :
- 101916822
- Full Text :
- https://doi.org/10.1016/j.sse.2014.12.005