Search

Terahertz (THz) quantum-cascade lasers (QCLs) are attracting an ever-increasing interest for both scientific and industrial applications in key areas, such as high-resolution spectroscopy of atomic and molecular absorption lines. Advancements in the active-region and resonator designs, hence, play a pivotal role in determining the future of this technology, especially regarding the wall-plug efficiency and the operating temperature, which are still the main factors limiting their widespread adoption. A sound characterization approach is, therefore, the foundation of the coming improvements to these semiconductor lasers. To overcome the overreliance on simulation tools for the determination of fundamental device characteristics, we report a comprehensive characterization approach to measure all relevant electrical, optical, and thermal parameters of THz QCLs in a consistent manner. Based on the lattice temperature dependence of the QCL output power, the thermal conductivity of the QCLs is extracted. We then retrieve light–current density–lattice temperature maps to decouple the influence of the bias and lattice temperature on the device performance. Applying this method to two sets of QCLs with different active-region designs allowed us to determine the internal quantum efficiency (∼12%), waveguide losses (8–20 cm−1), and transparency current density. A transparency current density greater than 60% of the threshold current density is observed for the two active regions, which demonstrates leakage currents to be the dominant factor limiting THz QCLs efficiency even at low temperatures and for optimized designs employing tall barriers of nominally pure AlAs. [ABSTRACT FROM AUTHOR]

The leakage mechanism of solar-blind AlGaN p-i-n photodetectors has been investigated. By studying the temperature-dependent I–V curves, we determined that Poole–Frenkel emission is the main source of the leakage current, and the corresponding trap energy level is 0.61 eV. Cathodoluminescence measurement demonstrates that the leakage current of the device may be related to the deep-level traps in the p-AlGaN layer. An analysis of deep-level transient spectroscopy testing results for p-AlGaN suggests that nitrogen vacancies formed during the epitaxial growth of high Al-content p-AlGaN act as electron traps. The trap potential energy decreases at high reverse bias voltage, making trapped electrons easier to escape, which increases the leakage current. [ABSTRACT FROM AUTHOR]

Both large spontaneous polarization and high breakdown strength are necessary to achieve high recoverable energy density in capacitors. Unfortunately, there is a trade-off between them within the homogeneous medium. Therefore, a sandwich structure with a high polarization layer was designed in the Aurivillius phase lead-free film to address this issue. This strategy can effectively enhance the polarization capability by introducing a highly spontaneous polarization layer and also improve the breakdown strength by reducing the leakage current caused by interfacial barriers and grain refinement. Benefiting from the synergistic effects, a high energy density of 50.4 J / cm 3 with a high efficiency of 76.6% in the sandwich-structure thin film capacitors were achieved. In addition, the energy storage performance exhibits good wide frequency range and high-temperature stability. This approach is generally applicable to the design of other ferroelectrics and dielectrics promises high-performance energy storage capacitors. [ABSTRACT FROM AUTHOR]

Due to their high similarity to biological ion channels, low power consumption, small footprint, and the fact that they do not require reset circuits, threshold switching memristors have been intensively studied for simulating neurons in neuromorphic chips. Switching speed is one of the key challenges which limit the application of threshold switching memristors in chips. In this study, Ta2O5 threshold switching memristors with high switching speeds were prepared by doping with silver. The results show that 14 wt. % Ag doped Ta2O5 threshold switching memristors exhibit excellent bi-directional threshold switching performance, featuring fast switching speeds (<20 ns, <18 ns), low leakage currents (<10 pA), and high switching ratio (>107). According to the field nucleation theory, the rapid switching speed can be attributed to the low nucleation energy (0.26 eV) of silver within the Ta2O5 matrix, which is achieved by incorporating 14 wt. % Ag during the doping process. Based on Pspice, a LIF (leaky integrate-and-fire) neuron based on the silver nanoparticles doped Ta2O5 threshold switching memristors is built, and its firing function has been simulated. The results show that the LIF neuron with a short switching time is able to excite pulse spiking with high frequencies. These results demonstrated that the silver nanoparticles doped Ta2O5-based threshold switching memristors hold significant potential for constructing high-speed artificial neural networks. [ABSTRACT FROM AUTHOR]

The S vacancy at metal/ MoS 2 interface plays a much important role than the semiconductor itself. In this work, the influence of different configurations of S vacancy concentrations on the effective work function and band structure of the Au/ MoS 2 interface has been investigated systematically using first-principles calculations. The study specifically explores the effective work function of the Au/ MoS 2 interface, the deviation of interface effects from the vacuum work function, and the dipole moment caused by interface charge transfer. The results reveal that the electronic work function of Au/ MoS 2 increases with the increase in S vacancy concentration, but the rate of increase tends to slow down with higher S concentrations. The variation in the effective work function of the Au/ MoS 2 interface may be attributed to the presence of S vacancies and the exposure of Mo atoms. S vacancies lead to a reduction in the Schottky barrier, resulting in increased leakage current. The Fermi pinning caused by S vacancy concentration and location is also observed. The results obtained in this study can serve as a theoretical foundation for applications in electronic devices that rely on metal/ MoS 2 contact. [ABSTRACT FROM AUTHOR]

Polymer dielectrics with excellent capacitive performance are urgently needed in advanced electrical and electronic systems. However, due to the dramatic increase in the conduction loss, the energy density and efficiency of polymers degrade severely at elevated temperatures, limiting their application in harsh environments up to 150 °C. Herein, an all-organic polyurea (PU)/polyetherimide (PEI) blend film is designed to prepare high-temperature polymer dielectric. It is found that carrier traps can be introduced by blending, and the hydrogen bond between PU and PEI increases the trap depth, leading to suppressed leakage current and enhanced breakdown strength, thus improving the energy storage performance. PU/30%PEI exhibits a high discharged energy density of ∼3.74 J/cm3 with an efficiency higher than 90% at 150 °C, which is 78% and 70% higher than pristine PU and PEI, respectively. This work provides a facile strategy to improve the energy storage performance of polymer dielectrics by introducing deep traps through blending. [ABSTRACT FROM AUTHOR]

This paper provides a comprehensive study of the impact of the gate recess depth (RD) on the GaN-on-Si MOS-HEMTs DC performances. IDS = f(VGS) and IDS = f(VDS) measurements are conducted at 25 and 150 °C, respectively, in forward and blocking modes. The gate recessed depth (50, 150, and 350 nm) is modulated by adjusting the plasma etching time, which is a critical step for improving the dielectric/GaN interface quality and the gate channel electron mobility. Three distinct regions can be defined separately: the bottom, the sidewall, and the corner region being the junction between the two previous regions. To assess the impact of gate recessed depth (RD) on the several mobilities around the gate cavity first, we applied our previous methodology allowing us to extract the bottom (μbot) and the entire sidewall region mobility (μT), without distinction from the corner. The mobility of the transverse region was found surprisingly to increase with deeper RD. To gain insight into the impact of the RD on this transverse section, a new extraction methodology is proposed to extract separately the gate corner (μcorner) and sidewall (μSW) mobility. These extractions show that the corner mobility is found to be reduced compared to the sidewall one (μcorner < μSW) evidencing the different weighting contributions over the transverse mobility. Moreover, these mobilities are found to be more degraded compared to the bottom one, highlighting the different contributions on the on-state resistance (RON). Indeed, the on-state resistance is lowered with the shallower RD due to the reduced sidewall resistance contribution (lower sidewall length) and despite the incremental contribution of the bottom resistance (larger effective gate length). However, the shallower RD shows an increase in the drain–source leakage current in reason of a lower gate electrostatic control. Technology Computer Aided Design (TCAD) simulations of the three RD morphologies are carried out to validate the experimental trends and the proposed methodology. [ABSTRACT FROM AUTHOR]

Amorphous composite polymers are widely used as insulators in microelectronics due to their high dielectric strength, mechanical robustness, and thermal stability. However, organic–inorganic composite systems suffer from undesirable performance and accelerated degradation due to leakage current ( J Tot ). Unfortunately, the underlying mechanism of J Tot and its components (e.g., ionic and electronic constituents) are inadequately understood, particularly in extreme use conditions (e.g., high humidity and temperature). In this study, we use numerical simulation and experimental J Tot data (in amorphous epoxy polymer with silica fillers) to (i) unify the electrostatic model for J Tot in composite polymers, (ii) illustrate that the early part of J Tot (i.e., external current) is primarily due to the image charge associated with ion transport/ localization ( J ion ) near the metallic contacts, (iii) demonstrate that the accumulated counter-ions reduce the barrier for electronic charge injection (by band bending) and facilitate electronic injection from the metals ( J elec ), and (iv) provide an algorithm for the in situ ion transport characterization of composite insulators by exploiting J ion . This work provides new insights regarding the leakage current mechanism and how it can be used as a probe into the complex transport mechanisms of the composite material. [ABSTRACT FROM AUTHOR]

In this paper, the p-GaN gate AlGaN/GaN high electron mobility transistors (HEMTs) with varying combinations of gate metal work function and gate geometry are fabricated and investigate the influence of gate leakage current (IGS) on the threshold voltage (VTH) and subthreshold swing (SS). The unique dependence of VTH and SS on gate geometry for different metals is observed, which is different from traditional field-effect transistors. A novel hybrid physics model, consisting of the traditional capacitance divider model and hole injection model, is proposed to explain this phenomenon, and the results exhibit an excellent agreement with the experimental data. The holes traverse the gate/p-GaN Schottky barrier by thermal emission or tunneling and inject into the p-GaN layer, generating the IGS. Expanding upon the traditional capacitance divider model, a portion of the injected holes accumulate at the p-GaN/AlGaN interface and induce the corresponding electrons at the AlGaN/GaN heterojunction, which promotes channel conduction. Hence, the transfer curves display the correlation between IGS and VTH as well as SS. The results show that high IGS can alleviate the instability of VTH caused by the lithographic overlay error, and simultaneously optimize SS. This work offers a novel perspective for examining the turn-on mechanism of p-GaN HEMTs, thereby contributing to device design. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a hydrogen-terminated diamond (H-diamond) field-effect transistor (FET) with Al2O3/CeB6 gate materials. The CeB6 and Al2O3 films have been deposited by electron beam evaporation technique, sequentially. For the 4/8/12/15 μm gate length (LG) devices, the whole devices demonstrate distinct p-type normally off characteristics, and all the threshold voltage are negative; all the absolute values of leakage current density are 10−4 A/cm2 at a VGS of −11 V, exhibiting a relatively low leakage current density compared with CeB6 FETs, and this further demonstrates the feasibility of the introduction of Al2O3 to reduce the leakage current density; the maximum drain–source current density is −114.6, −96.0, −80.9, and −73.7 mA/mm, which may be benefited from the well-protected channel. For the 12 μm LG devices, the saturation carrier mobility is 593.6 cm2/V s, demonstrating a good channel transport characteristic. This work may provide a promising strategy for the application of normally off H-diamond FETs significantly. [ABSTRACT FROM AUTHOR]

In this work, bottom-Schottky-structure InGaZnOx (IGZO) Schottky barrier diodes (SBDs) with sputtered PtOx anodes were fabricated and annealed in oxygen at different temperatures. Critical parameters and negative bias stress (NBS) stability of SBDs with different annealing temperatures are investigated. With the annealing temperature increases, the barrier height and rectification ratio of the SBDs exhibited a rising-then-declining trend, while the ideality factor slightly increased until 200 °C. The SBDs show up overall reliability except for a leakage current rising trend under light, which can be attributed to free electron generation from the ionized oxygen vacancy. Among all the SBDs, the 175 °C annealed ones exhibited the best overall performance, including a high barrier height of 0.89 eV, an ideality factor of 1.14, and a large rectification ratio of over 108. Compared to the initial SBDs, the annealed ones showed up great improvement in NBS stability except for the 200 °C annealed ones, which was permanently degraded and not able to recover to original states. According to experimental result analysis and IGZO material characteristics, a stability model based on the subgap trap transition from V O 2 + to VO and new V O 2 + creation was proposed, which applies to both the short-term and long-term NBS tests. The results above demonstrate that oxygen annealing at appropriate temperature is an effective method to improve both device performance and NBS stability for PtOx–IGZO SBDs. [ABSTRACT FROM AUTHOR]

β-Ga2O3 is of great interest for power electronic devices with efficiency beyond current generation Si, 4H-SiC, and GaN devices due to its large breakdown electric field of ∼8 MV/cm. However, taking advantage of this large field strength in power diodes requires device engineering to reduce leakage current that arises at high electric fields. In this work, we elucidate the current transport mechanisms of metal/TiO2/β-Ga2O3 diodes, showing that thermionic emission is an excellent descriptor of current in forward and reverse bias. It is shown that tunneling current is greatly suppressed, and consequently, that the diodes with the TiO2 interlayer can block orders of magnitude more current than Schottky barrier diodes with the same barrier heights. Finally, a 1200 V diode structure is designed based on the derived transport models, and calculated on- and off-state current characteristics closely align with those of state-of-the-art 4H-SiC commercial devices, indicating that this diode structure is ready to enable the realization of β-Ga2O3 power diodes. [ABSTRACT FROM AUTHOR]

This study presents a comprehensive investigation of the impact of the deposition temperature on the HfxZr1−xO2 (HZO) ferroelectric layer of ferroelectric random access memory with TaN electrodes. This investigation mainly focuses on its electrical characteristics and compares the differences. It is revealed that the deposition temperature plays a crucial role in determining the crystal structure of HZO, which can exhibit a combination of tetragonal and orthorhombic phases or exist solely in one of the two phases. Furthermore, the grain size of HZO varies with the deposition temperature. These findings correspond well to the electrical measurement results, including leakage current, polarization, capacitance, and reliability tests. The study tracks the phase transition process during the operation of switching cycles when the phase transition process can be monitored as well. To better understand the observed differences, physical models that shed light on the underlying mechanisms affected by deposition temperature are proposed at the end of the article. [ABSTRACT FROM AUTHOR]

Gallium oxide (G a 2 O 3 ) is a promising ultra-wide bandgap material offering a large bandgap (> --> 4.7 eV) and high critical electric fields. The increasing demand for electronic devices for high-power applications in electric automobiles, high-performance computing, green energy technologies, etc., requires higher voltages and currents with enhanced efficiency. Vertical transistors, such as fin-shaped field-effect transistors (FinFETs) have emerged to meet the growing need with improved current handling capabilities, reduced resistance, and enhanced thermal performance. However, to fully exploit the Ga 2 O 3 power transistors, precise and reliable physics-driven models are crucial. Therefore, a comprehensive surface potential model has been developed in this work for a vertical Ga 2 O 3 FinFET. The electric potential across the channel is explained by analyzing the two-dimensional (2D) Poisson equation employing parabolic approximation. Such a surface potential model is instrumental in determining the performance of the Ga 2 O 3 FinFET as it affects the threshold voltage, the drain current, and fringing capacitance. Exploiting the surface potentials, a fringing capacitance model is derived which is crucial in analyzing the speed of the device in compact integrated circuits. In addition, statistical analysis of the Ga 2 O 3 FinFET using the Monte Carlo simulation technique is performed to determine the leakage current fluctuation due to doping variations. The validation of the analytical model with experimental results confirms the effectiveness and prospects of the developed models in the rapid development and characterization of next-generation high-performance vertical Ga 2 O 3 power transistors. [ABSTRACT FROM AUTHOR]

We have attained low leakage current, low interfacial traps, and low border traps by effectively passivating both p- and n-In0.53Ga0.47As (InGaAs) surfaces using the same gate dielectrics of ultra-high-vacuum deposited Al2O3/Y2O3. Gate leakage currents below 2 × 10−7 A/cm2 at gate fields of ±4 MV/cm were obtained after 800 °C rapid thermal annealing, demonstrating the intactness of the interface and heterostructure. Negligibly small frequency dispersions in the capacitance–voltage (C–V) characteristics of p- and n-type metal-oxide-semiconductor capacitors (MOSCAPs) were obtained from accumulation, flatband, to depletion as measured from 300 K to 77 K, indicative of low border and interfacial trap density; the C–V frequency dispersions in the accumulation region are 1.5%/dec (300 K) and 0.19%/dec (77 K) for p-InGaAs, and 2.2%/dec (300 K) and 0.97%/dec (77 K) for n-InGaAs. Very low interfacial trap densities (Dit's) of (1.7–3.2) × 1011 eV−1cm−2 and (6.7–8.5) × 1010 eV−1cm−2, as extracted from the conductance method, were achieved on p- and n-InGaAs MOSCAPs, respectively. [ABSTRACT FROM AUTHOR]

It is a formidable challenge to find the minority carrier recombination lifetime in low-dimensional devices as low-dimensionality increases the surface recombination rate and often reduces the recombination lifetime to a scale of picoseconds. In this work, we demonstrated a simple but powerful method to quantitatively probe the minority carrier recombination lifetime in silicon nanowires or microwires by fitting the experimental photoresponses with our recently established analytical photoresponse principle of photoconductors. The nanowires were passivated with small molecules and Al2O3 to suppress surface recombination, which will increase the minority recombination lifetimes. As expected, the minority carrier recombination lifetime found by this approach increases by orders of magnitude. These wires were also made into PIN diodes, the leakage of which was reduced at least 1 order of magnitude after surface passivation by Al2O3. The minority recombination lifetime found from the leakage current of these devices is largely consistent with what we found from our analytical photoresponse principle. As a further step, we performed scanning photocurrent microscopy to find the minority diffusion length from which we found that the minority recombination lifetime is close to what we found from the analytical photoresponses. In short, this work validated that our analytical response principle is a reliable method to find the minority recombination lifetime in low-dimensional semiconductors. [ABSTRACT FROM AUTHOR]

We have analyzed and modeled the reverse-biased gate leakage current in a Schottky-gate AlGaN/GaN high electron mobility transistor. While the Poole–Frenkel emission current along conductive threading dislocations dominates at low negative gate bias, the trap-assisted tunneling of thermally energized electrons and the thermal emission of electrons from threading dislocations aided by dislocation-related states at multiple energy levels within the AlGaN bandgap are dominant at moderate to large reverse bias. Additionally, deep trap levels of high density localized near the gate/AlGaN interface cause significant leakage at 473 K at low to moderate reverse bias, which could be specific to the device we have analyzed. We extracted about 10 12 cm − 2 traps near the AlGaN/GaN interface from the difference of the barrier layer electric field profile obtained from the experimental high-frequency capacitance–gate voltage and the one needed for final matching. The thermionic- and the thermionic field-emission currents are considerably low; the latter, however, dominates in the defect-free case. Finally, the simulation framework we developed here helped us identify various conduction mechanisms contributing to the reverse-biased gate leakage and the density and electronic structure of the responsible defects. [ABSTRACT FROM AUTHOR]

Lead-free piezoelectric (K, Na)NbO3 (KNN) is considered one of the promising candidates for the replacement of Pb(ZrxTi1−x)O3. Several studies underlined the issue of K and Na volatility with increasing deposition temperatures, leading to high leakage currents in thin films, which still represents a major drawback for applications. This paper shows how epitaxial growth with concomitant preferred orientation of KNN films on niobium-doped strontium titanate (Nb:STO) depends on growth temperature and substrate strain. A preferred out-of-plane polar (001) orientation of KNN is obtained at high temperatures (>600 °C), while (100) orientation is dominant for lower ones. The (001) orientation is forced out-of-plane due to the sizeable in-plane stress derived from a negative lattice mismatch of pseudo-cubic KNN with respect to the underlying cubic (001) Nb:STO substrate. Moreover, we show that K-Na deficiency and high leakage of epitaxial KNN films deposited at high temperatures are accompanied by the appearance of a pattern of orthogonal spontaneous ferroelectric domains aligned to the [100] and [010] directions of Nb:STO. This pattern, visible in secondary electron microscopy, piezoforce response microscopy, and conductive atomic force microscopy images, is uncorrelated to the surface morphology. Supported by reciprocal space mapping by x-ray diffraction, this phenomenon is interpreted as the result of strain relaxation via ferroelectric domain formation related to K-Na deficient films displaying a sizable and increasing compressive strain when grown on Nb:SrTiO3. Our findings suggest that strain engineering strategies in thin films could be used to stabilize specific configurations of piezo- and ferroelectric domains. [ABSTRACT FROM AUTHOR]

A non-destructive method for detecting sub-micrometer-sized micropipes on an entire wafer surface is investigated. Since it is difficult to detect sub-micrometer-sized micropipes due to their small core size, a non-destructively and accurately detecting method is required. To solve the issue, we focus on a characteristic depression generated around micropipes, namely, line-shaped depressions. In this paper, the location of line-shaped depressions is identified by using optical inspection, and the line-shaped depressions are distinguished whether micropipes exhibit line-shaped depression or not by using mirror electron microscope observation as high-resolution inspection. The accuracy of the distinction results is confirmed by scanning electron microscope observation, and electrical characteristics of the P–N diode are fabricated using the inspected wafer. Furthermore, the sub-micrometer-sized micropipes are observed at the sites of leakage current identified by emission microscopy. Additionally, device simulation of the blocking-voltage characteristics of P–N diodes suggests that the increase in leakage current depends on the electric field at the sub-micrometer-sized micropipes, regardless of their core size. [ABSTRACT FROM AUTHOR]

We investigated leakage current characteristics affected by crystallinity and domain wall currents of epitaxial Bi5Ti3FeO15 (BTFO) thin films on Nb-doped SrTiO3 substrates. Highly a-oriented BTFO thin films, highly c-oriented BTFO thin films, and BTFO thin films with a mixture of a-oriented and c-oriented crystallinity were prepared by controlling the substrate temperature and the pulsed laser deposition deposition rate. Highly c-oriented BTFO thin films exhibited the best leakage current characteristics because the Bi2O2 layers were placed perpendicular to the c-axis to reduce leakage currents. The BTFO thin films with a mixture of a-oriented and c-oriented crystallinity showed larger leakage currents compared to highly c-oriented BTFO thin films. The current domains of the BTFO thin films corresponding to the ferroelectric domain structures were observed by a conducting atomic force microscope, and it was observed that leakage currents were formed around the domain walls. In particular, the largest leakage currents are formed at the boundaries of c-oriented domains and a-oriented domains, and these domain boundaries confirmed that the BTFO thin films with a mixture of a-oriented and c-oriented crystallinity were responsible for the largest leakage currents. [ABSTRACT FROM AUTHOR]

Due to the erratic switching phenomenon of the Si avalanche bipolar junction transistor (ABJT) in the Marx bank circuit (MBC), an explanation of the leakage current trigger mode in the overvoltage state with a lack of displacement current is proposed. There are random switching properties (i.e., switching or non-switching) in the ABJT with emitter–base shorted, triggered by a voltage ramp to the overvoltage state temporarily with dV/dt rate close to 0 V/ns. The experimental conditions and characteristics of erratic behaviors are summarized. The optical visualization of the current channel in an erratic switching state is obtained, and the corresponding physical model of the leakage current trigger mode is established. It shows that the switching event occurs with the change in the position of the conductive channel. The process of emitter electron injection is caused by the leakage current in the overvoltage state instead of the displacement current. Meanwhile, the intensity of this trigger mode is weak, and the instability of the leakage current may cause the failure of switching. The study of erratic switching is of great significance for the working reliability of MBCs and failure analysis of ABJTs. The proposed explanation is validated by the agreement between the simulation results and the experimental observations. [ABSTRACT FROM AUTHOR]

Silicone rubber (SR) is an ideal dielectric elastomer substrate due to its excellent flexibility and fast response speed. However, the innate low dielectric permittivity (ε) of SR generally requires a rather high driving voltage that restricts its widespread application. Typical attempts to increase ε of SR usually deteriorate either its flexibility or electrical stability. Herein, conductive multi‐walled carbon nanotube (MWCNT) were first surface modified with polyphenols (PNs) (MWCNT@PNs), aiming to facilitate its well dispersion within SR matrix, which may maintain the softness and electrical stability of SR via suppressing concentrated physical crosslinking and local leakage current flow. Then, five‐layered MWCNT@PNs/SR composites were prepared with the outer two insulating layers of SR while middle three dielectric layers of MWCNT@PNs filled SR. The multilayered structure further hindered the formation of conductive pathways through the composites, promising a high breakdown strength of the composites. Therefore, the multilayered MWCNT@PNs/SR composites exhibited increased ε, maintained low Young's modulus and electrical breakdown strength compared with pure SR of the same five‐layered structure. Among them, the composite with uniformly distributed MWCNT@PNs (m‐1: 1: 1) showed a highest actuation strain of 11.9% (at 19.6 kV mm−1), which was 4.1 times higher than that of SR (2.9% at 19.1 kV mm−1). [ABSTRACT FROM AUTHOR]

BiFeO 3 (BF) based ceramics are inspiring great interest in advanced pulsed power applications owing to their giant spontaneous polarization, meanwhile limited by the significant leakage current. In this work, Sr 0.7 Bi 0.2 TiO 3 (SBT) modified 0.7BiFeO 3 -0.3BaTiO 3 (BF-BT) ternary lead-free relaxor ferroelectric ceramics are investigated to elaborate the dielectric performances, including the impedance, relaxor behavior, ferroelectric and energy storage, and strain properties. The substitution of SBT induces a phase transition from an R 3 c to an average pseudo-cubic structure and forms a secondary phase at high dopants. Simultaneously, the resistivity, electrically homogeneous, and band gaps are increased significantly, related to the inhibition of oxygen vacancy formation. Besides, the ferroelectric long-range order is disrupted, which promotes the formation of local defect fields and polar nanoregions. The structural heterogeneity for the higher doped components leads to an increased relaxation behavior with an almost hysteresis-free polarization response to external electric fields. Excellent temperature-insensitive dielectric response and promising dielectric energy storage properties in low electric fields are achieved, respectively. These results indicate that the SBT modification is an effective route in regulating the dielectric performance of bismuth ferrite based relaxors. [ABSTRACT FROM AUTHOR]

Sintering temperature is decisive for optimizing the grain boundary environment to obtain the high performance ZnO based varistor ceramic. In this work, the impacts of sintering temperature on microstructure and electrical properties of ternary Zn-Sr-Co varistor were investigated. It was found that the distribution of Sr, the critical factor to form grain boundary, was heavily sensitive to sintering temperature. The considerable Sr ions precipitated at grain boundaries and formed the clusters of SrZnO 2 while the sintering temperature increases from 1150 °C to 1190 °C. Besides, the precipitation of Sr led to the large segregation of Co at grain boundaries. The enrichment behavior of Sr and Co contributed to the optimization of grain boundaries, resulting in the enhanced barrier height. As a result, the excellent nonlinear current-voltage performances, i.e., the high nonlinear coefficient of 56.47 and the low leakage current density of 0.73 μA/cm2 were obtained in the ternary ZnO-SrCO 3 -Co 2 O 3 varistor sintered at 1190 °C. However, the grain boundary environment would be destroyed by the excessive temperature of 1210 °C, resulting in the degradation of grain boundary barrier and especially a surge in the leakage current I L from 0.73 to 92.19 μA/cm2. In addition, varying sintering temperature has the important effects on impedance and dielectric properties of the ZnO-SrCO 3 -Co 2 O 3 varistors. The findings provide new perspectives for developing the high-performance ternary ZnO-SrCO 3 -Co 2 O 3 varistor ceramics by optimizing the initial grain boundary environment at different sintering temperatures. [ABSTRACT FROM AUTHOR]

Doped Hf 0.5 Zr 0.5 O 2 materials have drawn increasing attention due to the excellent ferroelectric properties, but the relevant research is just in the preliminary stage and the reported doped systems are rare. In this work, Ca doped Hf 0.5 Zr 0.5 O 2 (Ca:HZO) ferroelectric films were successfully fabricated via chemical solution deposition and investigated for the first time. It is observed that Ca doping induces a phase transformation from monoclinic to orthorhombic/tetragonal and then to monoclinic/tetragonal. The highest orthorhombic phase fraction is achieved in 2.5 mol% Ca doped HZO film, contributing to the optimum ferroelectric property with the largest remnant polarization of 14.00 μC/cm2 after 105 cycles. Additionally, the leakage current density is observed to decrease with increasing Ca content, which is mainly associated with the changes of grain size and surface roughness. As a result, the endurance is significantly improved in the Ca doped films, and an excellent endurance of 1010 cycles is achieved in the 2.5 mol% Ca doped film. These results suggest that Ca doping can enhance the ferroelectric and endurance properties of HZO films by optimizing the phase and morphological structure. [ABSTRACT FROM AUTHOR]

Silicon carbide particle reinforced aluminum matrix composites (SiCp/Al), combine the properties of aluminum matrix materials and reinforced silicon carbide (SiC) particles, finding widespread application in aerospace, optics, and electronics. The increased hardness and electrochemical inertness of SiC particles present significant challenges in their processing. This research investigates the impact of photocatalytic processes on machining accuracy in electrochemical processing (ECM). The dissolution characteristics of SiCp/Al during ECM and photocatalytic-assisted electrochemical machining (PAECM) were analyzed with varying electrolyte compositions, using polarization curves and oxidation–reduction potential (ORP). Validation of improved machining accuracy and surface quality in PAECM was achieved through no-feeding machining. According to theoretical principles and laboratory analyses of the workpiece surface, it was found that PAECM, through its photocatalytic reaction, generated more oxides, blocked stray currents and stray corrosion effectively, and attained accuracy in profile creation. Through a comparative analysis it revealed that PAECM exhibited smoother profiles and reduced Overcut Ratio (OCR) in hole and groove machining compared to ECM, particularly in groove machining. Adjusting machining gaps as well as reducing abrasive particle size in PAECM influenced groove depth and width, which achieved optimal morphology with a 0.4 mm gap and a 2–3 nm abrasive particle size, resulting in a 370 μm depth. [ABSTRACT FROM AUTHOR]

Nanofilm CdS@Cd/Si heterojunctions have been fabricated by a two-step method. The obvious rectification effect can be observed. However, the leakage current density is relatively large. According to the criterion for judging the conduction model, three conduction mechanisms can be observed, which are the thermally generated electrons model, the Ohmic model and the space-charge-limited-current model from low voltage to high voltage, respectively. The preparation process of nanofilm CdS@Cd/Si heterojunctions by this two-step method, which directly grows nanofilm CdS@Cd on the silicon substrate to construct heterojunctions, can reduce the introduction of excessive defects and facilitate the release of stress in the interface. [ABSTRACT FROM AUTHOR]

The ten-switch inverter is recently proposed in the literature to replace the neutral clamped point three-level inverter; it can produce a two/three-level output voltage using only ten switches. The conventional modulation strategies generate a large common mode voltage (CMV), which increases the leakage current. The use of the sinusoidal pulse width modulation (SPWM) produces a high CMV of Vdc/2. On the other hand, using conventional space vector modulation (SVM) methods can only reduce the CMV to Vdc/3. To achieve further reduction in the magnitude of the CMV, a new virtual SVM (VSVM) strategy is suggested. The space vector diagram is constructed with virtual vectors which can generate the lowest possible CMV (|VCM|= Vdc/6). In the proposed VSVM, the action times are calculated and the switching sequence is synthesized for each region. The VSVM is applied to a ten-switch inverter through a simulation, and it is validated experimentally. It is compared to some existing modulation techniques, such as the SPWM method, two SVM methods and the conventional VSVM. Simulation and experimental results showed that the proposed VSVM algorithm can effectively reduce CMV to Vdc/6. The use of virtual vectors does not affect the performance of the proposed algorithm in terms of the use of the DC bus voltage. In addition, it can effectively balance the neutral point voltage. However, the analysis of voltages and currents demonstrated that the use of virtual vectors increases the rate of harmonics compared to conventional SVM methods. [ABSTRACT FROM AUTHOR]

This study presents and examines the feasibility of a dual metal gate ferroelectric germanium heterojunction-based step channel double-gate tunnel field-effect transistor (SC-DMTFET) to eliminate issues pertaining to drive current, subthreshold swing, and leakage current, concurrently decreasing ambipolar behavior resulting from structural similarities between the source and drain ends. Mitigating the consequences of ambipolar effects is the purpose of the study. The performance of the proposed structure was assessed and compared to that of a single metal gate, both with and without a step channel, by utilizing various TCAD simulation parameters. An analysis of the energy diagram, carrier concentration, electric field, drain characteristics, surface potential, and analog/radio frequency (RF) parameters was conducted to evaluate the electrostatic behavior of all the structures. The proposed structure yields minimum OFF current of 2.10 × 10−17 A/μm and maximum ON current of 2.33 × 10−3 A/μm. Also, the SC-DMTFET exhibits the highest current ratio of ≃1014 and the minimum subthreshold slope of 26.17 mV/decade in all designed structures. [ABSTRACT FROM AUTHOR]

ZnO varistor samples generally have poor preparation repeatability. In this work, ZnO varistor samples A and B with the same preparation technique showed significant differences in properties, and the reasons were explored in detail. Nonlinear coefficient (α) values of 42.59 and 72.68, and leakage current density of 0.013 mA/cm2 and 0.002 mA/cm2 were found for samples A and B, respectively, which are markedly different between the samples. However, samples A and B showed the same phases. In addition, samples A and B exhibited mean grain size (d) of 2.21 μm and 2.47 μm, double Schottky barrier height (φB) of 0.45 eV and 0.48 eV, and grain boundary resistivity (ρgb) of 5.32 × 106 Ω m and 5.40 × 106 Ω m, respectively, which were all similar between the two samples. According to the low-temperature dielectric spectral analyses, the values of k1 of samples A and B, reflecting the concentration of interstitial zinc, were 14.06 and 11.09, and the values of k2 reflecting the concentration of oxygen vacancy were 7.48 and 3.35, respectively. Therefore, the obvious difference in the electrical properties between samples A and B may be caused mainly by the obvious difference in the concentration of oxygen vacancy. Thus, this work provides evidence of the effects of oxygen vacancy on the electrical properties of ZnO varistors. [ABSTRACT FROM AUTHOR]

Due to the atomic thickness of 2D MoS2 film, the electronic structure is easily tunable by electric field and exhibits abundant property. However, due to the limit capacitance of inorganic dielectric, the tunability is still not well exhibited. Herein, a MoS2 phototransistor with large tunability driven by ion‐gel film is fabricated. To improve the interface and reduce the dark current, the passivation layer is used to hinder the leakage current. With the passivation layer, there will be a specific barrier height on the interface of metal electrodes and ion‐gel membrane. Under effect of the PVA (polyvinyl alcohol) passivation layer, the current on/off radio can reach 107 and the mobility can reach 6.54 cm2/(Vs) superior to the one without passivation layer. There is an abnormal behavior in the transistor including positive and negative photoresponse due to the coupling of the photogating effect and the adsorption of negative ion. The photoresponsivity can increase by 29 times which can reach 603.48 A W−1 at 400 nm illumination. Furthermore, the flexible transistor based on ion‐gel can be demonstrated and it found that the transistor still has a considerable photoresponse with strain of 0.49%. This work provides a new solution for flexible wearable electronic and photoelectronic detection field. [ABSTRACT FROM AUTHOR]

A flexible and printed field‐effect biosensor with a graphene channel (Gr‐FET biosensor) is designed and characterized to detect ferritin. The biosensor offers an onboard Ag/AgCl gate to give stable transfer characteristics with a significantly low gate leakage current of 0.06% of the minimum drain current. Further, the proposed Gr‐FET shows 1.5–3 times higher transconductance (gm) with a value of gm,hole up to 400 µS and gm,electron up to 250 µS, compared to the reported printed electrolyte‐gated Gr‐FET on flexible substrates. The Gr‐FET operation is also optimized to have a minimal hysteresis effect for reliable sensing operation. The Gr‐FET shows fairly linear characteristics at a low ferritin concentration (0.05–0.5 µg L−1) with sensitivity as high as ≈230 mV/(µg L−1) and a very low limit of detection (LOD) ≈27 ng L−1. Given the cost‐effective fabrication process and scalability, the proposed printed Gr‐FET biosensor can be deployed on a large scale for early diagnosis of iron deficiency anemia. [ABSTRACT FROM AUTHOR]

Aramid fiber (AF)-reinforced epoxy (EP) resin composite materials are widely used in the application of insulation rod-reinforced components, but the adhesion performance between AFs and EP resin is poor, which easily leads to interfacial defects and even gradually develops into breakdown, flashover, and other faults. In this study, a simple, environmentally friendly, diverse, and highly designable layer-by-layer self-assembly modification method was adopted to assemble aramid nanofibers/SiO2 onto the surface of AFs. The modified AFs were then used to produce composite materials with EP resin. By testing the interface breakdown, flashover, and leakage current of the AF/EP resin composite materials, the influence mechanism of AF surface modification on the material interface insulation performance was studied. The results show that the insulation performance of the modified composite material first increases and then decreases with the increase in the number of assembled layers, with the maximum increase in breakdown voltage being 93.56% and the maximum increase in flashover voltage being 30.91%. [ABSTRACT FROM AUTHOR]

Organic ferroelectric field-effect transistors (Fe-OFETs) exhibit exceptional capabilities in mimicking biological neural systems and represent one of the primary options for flexible artificial synaptic devices. Ferroelectric polymers, such as poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)), given their strong ferroelectricity and facile solution processing, have emerged as the preferred choices for the ferroelectric dielectric layer of wearable devices. However, the solution processed P(VDF-TrFE) films can lead to high interface roughness, prone to cause excessive gate leakage. Meanwhile, the ferroelectric layer in neural computing and memory applications also faces a trade-off between storage time and energy for read/write operations. This study introduces a composite dielectric layer for Fe-OFETs, fabricated via a solution-based process. Different thicknesses of poly(N-vinylcarbazole) (PVK) are shown to significantly alter the ferroelectric hysteresis window and leakage current. The optimized devices exhibit synaptic plasticity with a transient current of 3.52 mA and a response time of approximately 50 ns. The Fe-OFETs with the composite dielectric were modeled and integrated into convolutional neural networks, achieving a 92.95% accuracy rate. This highlights the composite dielectric's advantage in neuromorphic computing. The introduction of PVK optimizes the interface and balances device performance of Fe-OFETs for neuromorphic computing. [ABSTRACT FROM AUTHOR]

ABSTRACT Leakage current and conducted electromagnetic interference (EMI) significantly impact the safe operation of servo motor drive systems (SMDSs). The impedance characteristics of the components in the circuit change considerably in the general frequency range studied for leakage current and conducted EMI. These variations at high frequency (HF) can result in conducted EMI and leakage current deviating from the expected results, necessitating further investigation. A method of impedance analysis is proposed in this paper, which can efficiently analyze the influence of HF characteristics of circuit components on leakage current and conducted EMI. The influences of Y‐capacitor capacitance value and cable length on conducted EMI and leakage current are analyzed specifically. According to the HF characteristics of the Y‐capacitor and the cable, it can be deduced that changes in leakage current and conducted EMI are associated with alterations in impedance characteristics. Finally, the accuracy of the theoretical analysis is verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

ABSTRACT Grid‐tied photovoltaic (PV) systems using switched capacitor (SC) inverters face challenges related to efficiency, reliability, and power quality. Despite their simplicity and reduced need for passive components, these inverters often experience high voltage stress on switches, limited voltage gain, and significant power losses due to frequent switching operations. These issues can negatively impact the efficiency, lifespan, and cost‐effectiveness of PV systems—factors that are increasingly critical for sustainable energy solutions. To address these challenges, we present a cost‐effective five‐level SC‐based grid‐tied inverter for PV applications. The proposed inverter features seven power switches, a single SC, and one source, providing a two‐fold voltage boost. Additionally, a current control structure is incorporated to regulate synchronized grid current injection. This paper offers a detailed analysis of the inverter's specifications, control technique, PWM scheme, and loss calculations, along with comprehensive design recommendations for components. Furthermore, when compared to recent topologies, the proposed inverter demonstrates superior performance in terms of power devices, leakage current, and efficiency. The design is validated through Matlab simulations and a hardware prototype. [ABSTRACT FROM AUTHOR]

The switchable electronic properties at the surface of ferroelectric nanomaterials offer possibilities for electrocatalytic hydrogen and oxygen evolution reactions, HER and OER respectively. Here, 0.5(BaTiO 3)-0.5(CoFe 2 O 4) (abbreviated as BTCF0.5) are prepared chemically. The material shows a high dielectric constant in the order of 107. Nyquist plot is consistent with non-Debye-type and negative temperature coefficient of resistance (NTCR) characteristics with low leakage current. BTCF0.5 shows superior electrocatalytic HER and OER with a low overpotential of ∼156 and ∼284 mV at current density10 mA/cm2 along with Tafel slopes of 43.37 mV/dec and 41.52 mV/dec respectively. The stability of the electrocatalyst is checked through a chronoamperometry test and up to 1000 cycles of CV both for HER and OER operations. The non-traditional behavior of the nanocomposite may make it highly desirable for usage in numerous renewable and sustainable energy-related applications in the present-day scenario. [Display omitted] • 0.5BaTiO 3 -0.5CoFe 2 O 4 nanocomposite sample was synthesized by chemical route. • A high dielectric constant in the order of 104 - 107 was observed at room temperature. • An impedance study was performed which confirmed the non-Debye type relaxation. • HER, OER showed 156 mV and 284 mV overpotential at 10 mA cm−2 current density. • The electrocatalyst showed ∼1.65 V cell voltage for overall water splitting. [ABSTRACT FROM AUTHOR]

Transformerless grid‐connected inverters (GCIs) are universally utilized in the PV system. However, they have the shoot‐through issue and common mode leakage current (CMLC). To address the above‐mentioned issues, a transformerless common‐ground GCI without shoot‐through issue is proposed. The proposed topology has one common ground between the PV array and the grid that eliminates the CMLC. The topology is the combination of two buck‐boost converters, so it has the boost capability. Each buck‐boost converter operates in half‐line period, so the proposed inverter is a single‐stage system. Only two switches operate in high frequency in positive half‐line period and only one switch operates in high frequency in negative half‐line period. Therefore, efficiency of the system can be improved. There is no current flowing through the body diode of the MOSFET. Additionally, the presented inverter has no shoot‐through problem. The operating principle is elaborated. At last, simulation and experimental results of a 250 W proposed inverter validate the theoretical analysis. The maximum efficiency of the system is 96.2%. [ABSTRACT FROM AUTHOR]

In this letter, to improve the performance and reduce leakage currents of bulk low‐temperature multi‐layer SiGe/Si superlattice (SL) fin field‐effect transistors (FinFETs), a p‐type omega‐shaped channel (Ω‐channel) SL FinFET is realized by etching a Si/Si0.7Ge0.3 triple‐layer stacked structure in a replacement metal gate (RMG) module on a silicon‐on‐insulator (SOI) substrate. In addition, a self‐allied Ni0.9Pt0.1 silicide process and a low‐thermal‐budget (≤400°C) integration procedure were performed on the Ω‐channel SL FinFET. Test results demonstrate that the on‐state current (Ion) is increased by 5.5 times (from 78 to 429 µA/µm) and the off‐state current (Ioff) is reduced by 78.8% (from 5.2 × 10−3 to 1.1 × 10−3 µA/µm) when compared with the corresponding currents of traditional bulk SL FinFETs. [ABSTRACT FROM AUTHOR]

The polycrystalline Sr 0.8 Sn 0.2 Bi 1.75 Nd 0.25 Nb 2 O 9 (NdSBN) was synthesized using the green synthesis microwave sintering method, which significantly reduced the processing parameters of the NdSBN ceramics. Orthorhombic crystal structure with A2 1 am symmetry was revealed by Rietveld refinement study, whereas the doping-induced strain and crystallite size was studied using the Williamson Hall method. Crossectional SEM micrographs confirm the plate-like structure, with an average grain size of 273.7 nm. A diffuse type of phase transition was observed at 345 °C, which usually arises due to compositional fluctuations and mobile oxygen vacancies; further, the diffusiveness of the NdSBN was studied using Uchino and Nomura function, a modified version of Curie-Weiss law (CW). The frequency and temperature-dependent dielectric study of NdSBN ceramics display a Maxwell-Wagner relaxation with a high loss in a low frequency regime, possibly due to the presence of leakage current in the solid solution. Frequency dependent AC conductivity obeys Jonscher's power law, whereas DC conductivity supports polaron assisted hopping in NdSBN composition with dual activation energies of 0.55 eV and 0.75 eV, which correspond to electrons and ions, respectively. The non-Debye type relaxation mechanism in conjunction with negative temperature coefficient of resistance (NTCR) behavior was demonstrated by temperature dependent impedance spectroscopy, while modulus spectroscopy confirmed the multiple relaxation processes in NdSBN ceramics. [ABSTRACT FROM AUTHOR]

Controlling the formation of interfacial layers in dynamic random-access memory (DRAM) capacitors is crucial because it affects electrical performance, such as increasing the equivalent oxide thickness. This study investigates the formation of an interfacial layer during atomic layer deposition (ALD) of ZrO 2 on TiN electrodes and examines its influence on electrical properties. Utilizing O 3 and H 2 O as oxygen sources, we quantitatively identified notable differences in the formation of the interfacial TiO x layer. Using O 3 results in a thicker TiO x layer with fewer impurities, which lowers the leakage current, whereas H 2 O creates a thinner interfacial layer with higher impurity levels, leading to an increased leakage current. To optimize these effects, we developed a two-step ALD process that combines both oxygen sources, reducing the interfacial layer thickness while maintaining low leakage currents. This approach significantly improved the electrical performance of capacitors. Furthermore, similar results were observed for HfO 2 /TiN systems, suggesting that our findings are broadly applicable to high-k dielectric materials. [ABSTRACT FROM AUTHOR]

Atomic layer deposition (ALD) benefits from high process temperatures when the substrate is not temperature-sensitive because the films deposited at higher temperatures exhibit better electrical properties. In this study, we investigated the ALD process of silicon oxide films by alternating injections of tris(dimethylamino)silane (tris-DMAS) and O 3 /O 2 at temperatures ranging from 400 to 700 °C. The saturation dose of tris-DMAS was 1.5 × 106 L at 400 °C. Self-limiting growth with a growth rate of approximately 0.9 Å/cycle was observed up to 600 °C, allowing excellent step coverage. However, at 700 °C, the growth rate increased significantly to 4.6 Å/cycle, carbon and nitrogen impurities were detected by secondary ion mass spectrometry, and step coverage was poor, supporting the thermal decomposition of tris-DMAS at this temperature. Therefore, the optimum temperature for ALD SiO 2 using tris-DMAS is 600 °C for application as an insulating film on high aspect ratio patterns. At this temperature, the leakage current density was 0.58 nA/cm2, and the oxide-trapped charge density was 4.0 × 1010 cm−2. [ABSTRACT FROM AUTHOR]

Beta-phase gallium oxide, β-Ga2O3, in transistors and diodes has been reported due to its distinctive electrical characteristics, such as wide bandgap, low leakage current, and high breakdown electric field. However, besides such conventional basic devices, more advanced device applications using β-Ga2O3 are always necessary. Here, we report on the dynamic behavior of Pt/β-Ga2O3-based Schottky diode for power-efficient organic light emitting display (OLED). Two Schottky diodes are back-to-back connected in series to form a half-wave rectifier circuit and finally integrated with an OLED diode pixel. When AC voltage is applied to the circuit at a frequency greater than 60 Hz, blinking of the OLED light is indistinguishable to human eyes. By way of the rectifier circuit, the OLED pixel efficiently saves more than 35% of the power that should be consumed by applying DC voltage. [ABSTRACT FROM AUTHOR]

A 600-V p-GaN gate double channel HEMT (DC-HEMT) is presented with a systematic investigation of the gate characteristics, including the leakage current, breakdown, and reliability under forward bias stress. It is found that the gate leakage of the DC-HEMT is substantially lower than that of the p-GaN single channel HEMT (SC-HEMT) owing to suppressed electron spillover that stems from hole storage in the quantum well upper channel. Consequently, the gate breakdown voltage of the DC-HEMT is improved to 14.7 V compared to 12.2 V of the SC-HEMT. Besides, the gate operating voltage margin of the DC-HEMT is expanded to 4.2 V compared to 3.3 V of the SC-HEMT according to the gate lifetime evaluation. [ABSTRACT FROM AUTHOR]

ABSTRACT The output AC side voltage of traditional full‐bridge inverter is lower than the input DC side voltage, which is limited in low‐voltage power generation. The conventional boost circuit and the modified boost circuit structure are effectively combined, thus putting forward a kind of no leakage current of single‐phase single‐stage booster inverter. The inverter has the characteristics of common ground, which can suppress the leakage current from the structure and avoid the problem of shoot‐through and improve the reliability of the system. The working mode, modulation strategy, and steady‐state performance of the proposed circuit structure are analyzed in detail. Finally, a 250‐W experimental prototype is designed in the laboratory, and the experimental results verify the feasibility and superiority of the proposed inverter. [ABSTRACT FROM AUTHOR]

ABSTRACT This paper presents a novel single‐source common‐ground switched‐capacitor (CGSC) type dual‐mode five‐level (5L) transformer‐less (TL) multilevel inverter (MLI) topology with inherent boosting capability. The proposed topology comprises a single DC source, nine power switches, and two capacitors with self‐voltage balancing ability, reducing the inverter's size, cost, and complexity. The direct connection of the negative terminal of the source to the neutral point of the load eliminates the leakage current. The converter can operate in both buck and boost mode based on the series–parallel switching conversion of the involved switches. The circuit description, control strategy, and design guidelines are discussed in detail. The steady‐state and dynamic performance of the proposed circuit is validated using MATLAB Simulink software. Reliability analysis of the proposed converter is done in detail. Furthermore, the proposed converter is being compared with state‐of‐the‐art topologies. [ABSTRACT FROM AUTHOR]

The gate reliability of p-GaN gate high electron mobility transistors (HEMTs) was investigated in this Letter. Compared with conventional p-GaN gate HEMT, the in situ SiN cap-layer on the p-GaN layer can lift up the energy band and form a metal–insulator–semiconductor structure. With the introduction of an in situ SiN cap-layer, the DC electrical characteristics and reliability have been significantly improved. The reverse gate leakage current is reduced by 3 orders of magnitude. The threshold voltage shifts from 1.67 to 3.25 V, the on-resistances increased from 8.7 to 9.9 Ω mm, and the gate breakdown voltage is improved from 10.2 to 16.3 V. After conducting time-dependent gate breakdown measurement and predicting lifetime with a 10-year failure rate of 63%, it is calculated that the maximum allowable gate voltage increased from 6.3 to 11.4 V. The 10-year gate voltage swing has improved from 4.63 to 8.15 V. In addition, the in situ SiN HEMT exhibits good stability under high temperatures and long-term stress tests. The experimental results demonstrate that the in situ SiN cap-layer offers significant advantages in gate reliability. [ABSTRACT FROM AUTHOR]

Flexible perovskite light‐emitting diodes (f‐PeLEDs) have attracted increasing interest to realize true‐color, low‐cost, and light‐weight wearable optoelectronic and flexible display applications. However, their external quantum efficiency (EQE) and mechanical stability lag far behind because of the inherent surface and brittle issues of polycrystalline perovskite films. In this work, a multi‐functional polymeric‐termination surface of perovskite film is constructed for achieving efficient and mechanically stable f‐PeLEDs. It takes the roles to not only reduce defects through equipping coordination groups to improve emission properties, but also optimize film morphology and eliminate pinholes to solve the long‐standing issue of leakage current. Meanwhile, the polymeric‐termination surface with anchoring points and polymeric soft chains on perovskites demonstrates synergetic effects beyond the corresponding functional group‐only or polymer‐only strategies in reducing the Young's modulus and improving the mechanical flexibility. Ultimately, the record EQE of 22.1% and significantly enhanced mechanical stability of maintaining 82% of the initial performance after 2000 bending cycles with radius of 5 mm are achieved in pure‐green f‐PeLEDs. The work paves the way for the development of high‐performance flexible optoelectronic devices. [ABSTRACT FROM AUTHOR]

ABSTRACT Nonisolated three‐level inverter has the problem of leakage current and neutral‐point (NP) potential imbalance in photovoltaic grid‐connected system. Therefore, a new subregional vector‐optimized modulation strategy is proposed, which can be adopted to achieve leakage current suppression and NP potential balance control in full power factor and the range of full modulation ratio. First, a system model is established for the three‐level grid‐connected inverter to analyze the mechanism of leakage current and the factors affecting the NP potential. Aiming at the shortcomings of existing modulation strategies, the three‐level space vector modulation region is redivided, and different voltage vector preselection methods are used in different modulation regions, reduced computing power. In addition, controlling the balance of NP potential, the effect of dead zone effect on the leakage current is further analyzed and improved on the basis of the proposed strategy. Finally, the proposed strategy is compared with the traditional space vector pulse width modulation strategy. The experimental results show that the proposed control strategy suppresses the leakage current below 300 mA and can effectively control the NP potential shift and eliminate the midpoint potential fluctuation. Meanwhile, the control strategy is low in computation and fast in seeking the optimum. [ABSTRACT FROM AUTHOR]

A model of the tunneling current through an ultrathin insulating barrier coming from carriers in an inversion layer using a simple linear potential model is presented. This model provides analytical expressions for the wavefunctions of these carriers and simple equations to obtain numerically their corresponding eigenvalues. These expressions can be inserted in the tunneling current equation allowing a more simple understanding of the physics involved in this tunneling problem. As an example, one can fit the experimental results for the leakage current obtained by different authors in planar metal oxide semiconductor field effect transistors and also in a LaAlO3/SrTiO3 and a HfO2/Ge bilayer. The modification of the tunneling current when the dielectric constant is increased, a subject of interest in device applications, is explored. [ABSTRACT FROM AUTHOR]