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We demonstrate a quantitative framework to evaluate a nonradiative capture process with multiphonon emission in a semiconductor/dielectric heterostructure, mediated by a tunneling process. In addition to evanescent tunneling decay, the presence of an internal electric field modifies the relative energy depth of the carrier trap depending on the distance, modulating the overall capture behavior. We quantitatively derive the capture rate based on the parameters of the device structure (gate voltage, threshold voltage, dielectric material thickness, and temperature). We benchmark the formalism for the case of a Si/SiO 2 heterostructure, using an isolated Si dangling bond in α -quartz as a prototype defect in silica. We find that the calculated capture coefficients show a nonmonotonic trend as a function of distance of the defect from the interface, due to countervailing trends in capture barrier and wave-function decay. The predicted capture rates are in reasonable agreement with experimentally measured capture time constants, showing promise for the application of this compact model. [ABSTRACT FROM AUTHOR]

In this study, we report tunable metallic and semiconducting behavior in molybdenum di-telluride (2H-MoTe2) by manipulating the Joule heating process through electrical control of the channel current. At low voltages, 2H-MoTe2 exhibits semiconducting behavior. As the current surpasses a critical threshold at higher voltages, the material transitions to a metallic-like state, confirmed by a positive temperature coefficient of resistance. Temperature- and voltage-dependent Raman studies confirm that this semiconducting to metal-like transition occurs without any accompanying structural phase transformation. This metallic behavior is likely due to enhanced phonon scattering caused by the increase in lattice temperature. In the metallic state, exposure to H2 gas results in a negative response, with increased resistance due to additional phonon scattering. Conversely, laser exposure at this state produces no noticeable photoresponse because the already high lattice temperature limits the impact of further heating. These effects were suppressed when 2H-MoTe2 was placed on a hexagonal boron nitride/multilayer graphene heat sink. This dynamic modulation of conductivity in 2H-MoTe2 through electrical stimuli highlights its potential for nanoelectronic device applications. [ABSTRACT FROM AUTHOR]

Amorphous oxide semiconductors have garnered significant attention in recent years for their potential in flat-panel displays and back-end-of-line-compatible monolithic 3D (M3D) integration applications. This study explores amorphous InSnZnO thin films deposited via plasma-enhanced atomic layer deposition (PEALD) and the development of high-performance PEALD ITZO thin-film transistors (TFTs) with different active layer thicknesses, fabricated under a low thermal budget of 200 °C. By optimizing the deposition process of binary oxides InOx, SnOx, and ZnOx, a shared temperature window of 170–180 °C was identified for ITZO thin-film deposition. The deposited ITZO films, irrespective of thickness, exhibit an amorphous phase. Moreover, a reduction in ITZO film thickness from 24 to 4.8 nm leads to an increase in the optical bandgap from 3.35 to 3.65 eV. The channel thickness significantly impacts the threshold voltage and carrier density of ITZO TFTs. Optimized ITZO TFTs with a 16 nm channel thickness demonstrate excellent electrical performance, including a threshold voltage of −0.58 V, a field-effect mobility of 29 cm2/V s, an on/off ratio exceeding 108, and a subthreshold swing of 74 mV/dec. Furthermore, the optimized ITZO TFT exhibits excellent stability under positive bias stress at 2 MV/cm, with a threshold voltage shift of 0.15 V after 3600 s. Consequently, ALD-based ITZO emerges as a promising channel material for future applications in transparent electronics and flat-panel displays. [ABSTRACT FROM AUTHOR]

In this study, we report tunable metallic and semiconducting behavior in molybdenum di-telluride (2H-MoTe2) by manipulating the Joule heating process through electrical control of the channel current. At low voltages, 2H-MoTe2 exhibits semiconducting behavior. As the current surpasses a critical threshold at higher voltages, the material transitions to a metallic-like state, confirmed by a positive temperature coefficient of resistance. Temperature- and voltage-dependent Raman studies confirm that this semiconducting to metal-like transition occurs without any accompanying structural phase transformation. This metallic behavior is likely due to enhanced phonon scattering caused by the increase in lattice temperature. In the metallic state, exposure to H2 gas results in a negative response, with increased resistance due to additional phonon scattering. Conversely, laser exposure at this state produces no noticeable photoresponse because the already high lattice temperature limits the impact of further heating. These effects were suppressed when 2H-MoTe2 was placed on a hexagonal boron nitride/multilayer graphene heat sink. This dynamic modulation of conductivity in 2H-MoTe2 through electrical stimuli highlights its potential for nanoelectronic device applications. [ABSTRACT FROM AUTHOR]

The electrical properties and defects behavior in Si-based laterally diffused metal oxide semiconductor (LDMOS) chips under repetitive gate transmission line pulse stress were investigated. The results show that the threshold voltage increased by 22.4%, the output saturation current reduced by 12.5%, and the gate leakage current increased with the increasing gate voltage by 4.3 mA/V after the stress. An intrinsic trap H1 at 300 K was observed in the fresh Si-based LDMOS chip by using deep-level transient spectroscopy, where the activation energy did not change obviously, but the interface state density increased after the stress, resulting in the increase of threshold voltage. In addition, a new trap E1 appeared at 75 K in the stressed Si-based LDMOS chip, which may capture electrons, decreasing the effective electron concentration, leading to the decrease of the saturation current. High-resolution transmission electron microscopy results show that there are some cracks at the grain boundaries in poly-silicon, which may be the main path for the gate leakage current. Our study lays a foundation to further understand defects and their evolution in the Si-based LDMOS chips during the operation. [ABSTRACT FROM AUTHOR]

In this work, the first fabrication and investigation of normally-off single crystal hydrogen-sterminated diamond MOSFETs with Ga2O3 dielectric has been successfully carried out. 50-nm-thick Ga2O3 was deposited by electron-beam evaporation technique at room temperature. The maximum drain current was −36 mA/mm, which was 164 times larger than previous work. Based on the transfer characteristic curve, the threshold voltage, on/off ratio and extrinsic transconductance were −0.37 V, 2.3 × 107, and 9.8 mS/mm, respectively. The effective mobility of the MOSFET was calculated to be 264.1 cm2/V ⋅s at VGS = − 1 V. This work may significantly promote the application of H-diamond FETs. [ABSTRACT FROM AUTHOR]

In this work, the first fabrication and investigation of normally-off single crystal hydrogen-sterminated diamond MOSFETs with Ga2O3 dielectric has been successfully carried out. 50-nm-thick Ga2O3 was deposited by electron-beam evaporation technique at room temperature. The maximum drain current was −36 mA/mm, which was 164 times larger than previous work. Based on the transfer characteristic curve, the threshold voltage, on/off ratio and extrinsic transconductance were −0.37 V, 2.3 × 107, and 9.8 mS/mm, respectively. The effective mobility of the MOSFET was calculated to be 264.1 cm2/V ⋅s at VGS = − 1 V. This work may significantly promote the application of H-diamond FETs. [ABSTRACT FROM AUTHOR]

Gate oxide reliability has become a significant concern for emerging technology nodes, particularly as transistors continue to scale down. Quantum confinement effects in nano-scaled devices complicate the trapping dynamics near the interface. Although these behaviors can be modeled using density-functional theory (DFT) and Marcus theory, a more efficient method is essential for characterizing critical reliability issues at the nano-device level. This paper presents a pioneering numerical study that employs a Bohm potential and Marcus theory, examining carrier concentration decay near the channel/oxide interface to evaluate the charge-trapping process using density-gradient coupled Poisson equations. This approach incorporates vital quantum corrections to classical studies. Key physics-based parameters are initially derived from DFT calculations and subsequently calibrated against experimental data. Our findings indicate that charge trap rates decrease with carrier density at the interface, ultimately affecting the device's threshold voltage shift. [ABSTRACT FROM AUTHOR]

Forthcoming infrared event-based sensors will have utility in the space-based surveillance domain where they could potentially perform traditional sensing and tracking functions with significantly enhanced temporal resolution and reduced downstream datalink demands and power consumption. As a first step toward extending event-based sensing technology into the mid-wave infrared, a DC simulation of the conventional event-based sensor unit cell's photoreceptor circuit is performed, and the results are compared with measurements of a printed circuit board implementation of the same circuit to assess what design freedom is available to interface the photoreceptor with a mid-wave infrared photodetector. Detailed analysis of the circuit and measurements provides insight into which fundamental properties of the transistors drive the photoreceptor's dynamic range and demonstrates several characteristics that are relevant to mid-wave infrared sensing. These characteristics include the capability to produce a stable, low voltage bias on the infrared photodetector to maximize sensitivity, and that operating the circuit below room temperature increases the photoreceptor's dynamic range. Measurements show that even the simplest implementation of the photoreceptor circuit exhibits a dynamic range of logarithmic compression of 150 dB at room temperature. However, the dynamic range is ultimately limited by the mid-wave infrared photodetector's dark current activation energy, which is significantly lower than the threshold voltage (energy) of the photoreceptor's feedback transistor and, thus, there is an incentive for the photodetector's dark current to be diffusion-limited. [ABSTRACT FROM AUTHOR]

We have performed a small-signal admittance analysis to extract trap parameters in an AlGaN/GaN high electron mobility transistor-on-Si. Whereas the admittance in the accumulation- and depletion-bias regimes is primarily due to the interface traps, the admittance near the threshold voltage and below is due to mono-energetic traps inside GaN. The density extracted for threading dislocation-related 1D traps at ≈ 0.22 eV below the GaN conduction band edge is similar to that previously reported by reverse-biased gate leakage analysis of the analyzed device. Our analysis suggests additional 1D traps of comparatively lower density ≈ 4 × 10 14 cm − 3 but considerably large capture cross section ≈ 8 × 10 − 14 cm 2 in the GaN layer at ≈ 0.31 eV below the conduction band. The AlGaN trap density is considerably larger near the AlGaN/GaN interface than in the bulk AlGaN. The AlGaN traps mainly contribute to the voltage stretch; their admittance contribution is negligible. Gate leakage dominates the conductance at lower frequencies. [ABSTRACT FROM AUTHOR]

The Bernards–Malliaras model, published in 2007, is the primary reference for the operation of organic electrochemical transistors (OECTs). It assumes that, as in most transistors, the electronic transport is drift only. However, in other electrochemical devices, such as batteries, the charge neutrality is accompanied by diffusion-only transport. Using detailed 2D device simulations of the entire structure while accounting for ionic and electronic conduction, we show that high ion density (>1019 cm−3) results in Debye screening of the drain–source bias at the electrodes' interface. Hence, unlike the drift-only current in standard FETs or low ion density OECTs, the current in high ion density OECTs is diffusion only. Also, we show that since in OECTs, the volumetric capacitor and the semiconductor are one, the threshold voltage has a different meaning than that in FETs, where the semiconductor and the gate-oxide capacitor are distinct entities. We use the above insights to derive a new model useful to experimentalists. Lastly, we fabricated PEDOT:PSS fiber-OECTs and used the results to verify the model. [ABSTRACT FROM AUTHOR]

In this paper, the p-GaN gate AlGaN/GaN high electron mobility transistors (HEMTs) with varying combinations of gate metal work function and gate geometry are fabricated and investigate the influence of gate leakage current (IGS) on the threshold voltage (VTH) and subthreshold swing (SS). The unique dependence of VTH and SS on gate geometry for different metals is observed, which is different from traditional field-effect transistors. A novel hybrid physics model, consisting of the traditional capacitance divider model and hole injection model, is proposed to explain this phenomenon, and the results exhibit an excellent agreement with the experimental data. The holes traverse the gate/p-GaN Schottky barrier by thermal emission or tunneling and inject into the p-GaN layer, generating the IGS. Expanding upon the traditional capacitance divider model, a portion of the injected holes accumulate at the p-GaN/AlGaN interface and induce the corresponding electrons at the AlGaN/GaN heterojunction, which promotes channel conduction. Hence, the transfer curves display the correlation between IGS and VTH as well as SS. The results show that high IGS can alleviate the instability of VTH caused by the lithographic overlay error, and simultaneously optimize SS. This work offers a novel perspective for examining the turn-on mechanism of p-GaN HEMTs, thereby contributing to device design. [ABSTRACT FROM AUTHOR]

A comprehensive quantitative root cause study of defect evolution leading to memory window closure from a charge balance and charge trapping perspective throughout all phases of a Si channel Hf0.5Zr0.5O2 (HZO) ferroelectric field-effect-transistor (FEFET) is reported. Starting with the first write pulse, an excessive SiO2 interlayer field is revealed that triggers the creation of defect levels Dit in excess of 1015 cm−2 eV−1 at the HZO–SiO2 interface screening ferroelectric (FE) polarization while enabling FE switching. Under subsequent early bipolar fatigue cycling (up to 104 cycles), defect creation commences at the SiO2–Si interface due to the high injected hole fluence (0.39 C/m2) during each stress pulse causing negative bias instability (NBI), which shifts the threshold voltage of the erase state VT,ERS by −0.3 V with accrual of permanently captured charge Nit of up to +5 × 10−3 C/m2 (3 × 1012 cm−2). Subsequently, Nit NBI generation at the SiO2–Si interface accelerates reaching levels of +7 × 10−2 C/m2, locking both FEFET program and erase drain current vs gate–source-voltage (ID–VGS) characteristics in the FEFET on-state inducing memory window closure at 105 cycles while FE switching (switched polarization Psw = 0.34 C/m2) remains essentially intact. These findings guide the down-selection toward suitable semiconductor/FE systems for charge balanced, reliable, and high endurance FEFETs. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a hydrogen-terminated diamond (H-diamond) field-effect transistor (FET) with Al2O3/CeB6 gate materials. The CeB6 and Al2O3 films have been deposited by electron beam evaporation technique, sequentially. For the 4/8/12/15 μm gate length (LG) devices, the whole devices demonstrate distinct p-type normally off characteristics, and all the threshold voltage are negative; all the absolute values of leakage current density are 10−4 A/cm2 at a VGS of −11 V, exhibiting a relatively low leakage current density compared with CeB6 FETs, and this further demonstrates the feasibility of the introduction of Al2O3 to reduce the leakage current density; the maximum drain–source current density is −114.6, −96.0, −80.9, and −73.7 mA/mm, which may be benefited from the well-protected channel. For the 12 μm LG devices, the saturation carrier mobility is 593.6 cm2/V s, demonstrating a good channel transport characteristic. This work may provide a promising strategy for the application of normally off H-diamond FETs significantly. [ABSTRACT FROM AUTHOR]

In this work, bottom-Schottky-structure InGaZnOx (IGZO) Schottky barrier diodes (SBDs) with sputtered PtOx anodes were fabricated and annealed in oxygen at different temperatures. Critical parameters and negative bias stress (NBS) stability of SBDs with different annealing temperatures are investigated. With the annealing temperature increases, the barrier height and rectification ratio of the SBDs exhibited a rising-then-declining trend, while the ideality factor slightly increased until 200 °C. The SBDs show up overall reliability except for a leakage current rising trend under light, which can be attributed to free electron generation from the ionized oxygen vacancy. Among all the SBDs, the 175 °C annealed ones exhibited the best overall performance, including a high barrier height of 0.89 eV, an ideality factor of 1.14, and a large rectification ratio of over 108. Compared to the initial SBDs, the annealed ones showed up great improvement in NBS stability except for the 200 °C annealed ones, which was permanently degraded and not able to recover to original states. According to experimental result analysis and IGZO material characteristics, a stability model based on the subgap trap transition from V O 2 + to VO and new V O 2 + creation was proposed, which applies to both the short-term and long-term NBS tests. The results above demonstrate that oxygen annealing at appropriate temperature is an effective method to improve both device performance and NBS stability for PtOx–IGZO SBDs. [ABSTRACT FROM AUTHOR]

In this work, three atomic layer deposition (ALD) approaches are used to deposit an Al2O3 gate insulator on n-GaN for application in vertical GaN power switches: thermal ALD (ThALD), plasma-enhanced ALD (PEALD), and their stacked combination. The latter is a novel method to yield the most ideal insulating layer. Also, the influence of an in situ NH3 or H2 plasma pre-treatment is studied. Planar MIS capacitors are used to investigate the electrical properties and robustness of the gate insulators. In vacuo x-ray photoelectron spectroscopy (XPS) is used to study the changes in chemical composition after every surface treatment. XPS shows that all plasma pre-treatments efficiently remove all carbon contamination from the surface, but only NH3 plasma is observed to additionally remove the native oxide from the n-GaN surface. The water precursor step in the ThALD process does not completely remove the CH3 ligands of the trimethylaluminum precursor step, which might electrically be associated with a reduced forward bias robustness. The O2 plasma step in the PEALD process is associated with the removal of carbon and a tremendous increase of the O content in the GaN surface region. Electrically, this strongly correlates to an enhanced forward bias robustness and an increased forward bias hysteresis, respectively. The ThALD/PEALD stack method mitigates the shortcomings of both ALD processes while maintaining its advantages. Electrical measurements indicate that the stack method alongside NH3 plasma pretreatment provides the best characteristics in terms of hysteresis, threshold voltage, forward bias robustness, and interface trap density of states. [ABSTRACT FROM AUTHOR]

We have systematically investigated effects of metal–semiconductor or insulator–semiconductor interfacial layers (ILs) in AlGaN/GaN devices, where AlO x , TiO x , or NiO x is employed as an IL. From capacitance–voltage characteristics of metal/IL/AlGaN/GaN devices with a metal–semiconductor IL between the gate metal and AlGaN, it is shown that the IL modulates the threshold voltage V th , attributed to the vacuum level step induced by the dipole of the IL. We find negative vacuum level steps for AlO x and TiO x ILs, and positive for NiO x , from which the IL dipole density is estimated for each IL material. The two-dimensional electron gas carrier concentration in the metal/IL/AlGaN/GaN devices is also modulated by the vacuum level step. On the other hand, from capacitance–voltage characteristics of metal/ Al 2 O 3 /IL/AlGaN/GaN devices with an insulator–semiconductor IL between Al 2 O 3 and AlGaN, the fixed charge density of the Al 2 O 3 /IL/AlGaN interface is evaluated by the Al 2 O 3 thickness dependence of V th . For AlO x and TiO x ILs, the fixed charge density is higher than that of the Al 2 O 3 /AlGaN interface with no IL, while lower for NiO x. The fixed charge density for an IL shows a positive correlation with the IL dipole density, suggesting that the fixed charge is related to the unbalanced IL dipole. Furthermore, using the conductance method, we find a low trap density of the Al 2 O 3 /IL/AlGaN interface for AlO x and NiO x ILs, in comparison with that of the Al 2 O 3 /AlGaN interface with no IL. [ABSTRACT FROM AUTHOR]

Gallium oxide (G a 2 O 3 ) is a promising ultra-wide bandgap material offering a large bandgap (> --> 4.7 eV) and high critical electric fields. The increasing demand for electronic devices for high-power applications in electric automobiles, high-performance computing, green energy technologies, etc., requires higher voltages and currents with enhanced efficiency. Vertical transistors, such as fin-shaped field-effect transistors (FinFETs) have emerged to meet the growing need with improved current handling capabilities, reduced resistance, and enhanced thermal performance. However, to fully exploit the Ga 2 O 3 power transistors, precise and reliable physics-driven models are crucial. Therefore, a comprehensive surface potential model has been developed in this work for a vertical Ga 2 O 3 FinFET. The electric potential across the channel is explained by analyzing the two-dimensional (2D) Poisson equation employing parabolic approximation. Such a surface potential model is instrumental in determining the performance of the Ga 2 O 3 FinFET as it affects the threshold voltage, the drain current, and fringing capacitance. Exploiting the surface potentials, a fringing capacitance model is derived which is crucial in analyzing the speed of the device in compact integrated circuits. In addition, statistical analysis of the Ga 2 O 3 FinFET using the Monte Carlo simulation technique is performed to determine the leakage current fluctuation due to doping variations. The validation of the analytical model with experimental results confirms the effectiveness and prospects of the developed models in the rapid development and characterization of next-generation high-performance vertical Ga 2 O 3 power transistors. [ABSTRACT FROM AUTHOR]

Viruses such as SARS-CoV, MERS-CoV, and SARS-CoV-2 have posed serious threats to humanity in recent decades, with the COVID-19 pandemic wreaking havoc on both health and the economy. Early detection of these viruses is crucial for mitigating their effect on the immune system. In this study, we propose a dielectric-modulated biosensor realized using junctionless negative capacitance (NC) FinFET with strained silicon (StrS) integration for label-free electrical detection of neutral and charged biomolecules. The biosensor design integrates StrS within the source/drain (S/D) extension region, characterized by a Gaussian doping profile. The device employs a uniaxial stress of 1.4 GPa applied along the channel direction, which modulates the band structure to enhance carrier mobility. Additionally, a ferroelectric (FE) layer is incorporated in the gate stack, introducing a NC effect. This configuration reduces the OFF current while increasing the ON current, thereby improving the selectivity of the sensor. A 'T-shaped' metal support is incorporated, featuring cavities on both sides for the biomolecule's accommodation. Our investigation focuses on the label-free detection of various biomolecules characterized by their equivalent dielectric constant (K), e.g. Streptavidin (K = 2.1), Biotin (K = 2.63), APTES (K = 3.57), Keratin (K = 8), etc. Discrimination between different biomolecules is achieved by analyzing variations in threshold voltage (V TH), OFF current, and I ON/ I OFF ratio as sensing metrics. The limit of detection (LoD) of the proposed sensor was meticulously estimated through a machine learning approach, achieving an impressive sensitivity with a calculated value of 0.47, quantified in terms of the ' K ' of the biomolecules. A comprehensive analysis also involves the sensitivity and selectivity analysis with different FE thicknesses. Our study found that Pyridine (K = 12) biomolecules have the highest V TH and OFF current sensitivity (189.57% and 85.51%, respectively), as well as the highest V TH and OFF current selectivity over Streptavidin (1.3 and 0.811, respectively) at FE thickness of 1.8 nm. Furthermore, this paper explores the impact of low-frequency noise (i.e. flicker noise) on the noise power spectral density (PSD) of the proposed biosensor in the presence of different biomolecules. Our findings reveal that an increase in the gate coupling capacitance corresponds to the rise in K of biomolecules, leading to a decrease in noise PSD ( S ID / I D 2 ) and a subsequent reduction in noise. Using well-calibrated TCAD models, the acquired results reveal that incorporating StrS leads to a ∼41% increase in the ON current over its baseline case. [ABSTRACT FROM AUTHOR]

This paper introduces a novel GaAs/GaSb polarity-controlled tunnel field-effect transistor (GaAs/GaSb PC-TFET)-based biosensor with high sensitivity for label-free biomolecule detection. The polarity-controlled concept is employed to create the drain/source region in the proposed structure, reducing fabrication complexity and cost. The electrical characteristics (drain current and threshold voltage) of the GaAs/GaSb PC-TFET biosensor change as different biomolecules are immobilized in the nano-cavity region. This study thoroughly investigates the ON-current sensitivity (S I ON ) and threshold voltage sensitivity (S V Th ) parameters of the proposed GaAs/GaSb PC-TFET biosensor. Findings indicate that the GaAs/GaSb PC-TFET biosensor exhibits higher S I ON and S V Th values ( 1.53 × 10 14 and 0.79) as compared to recently reported similar FET/TFET-based biosensors. The efficiency of the proposed biosensor is further examined by studying the impact of the molecule's charge density, non-ideality (steric hindrance and different fill factors), variation in cavity dimensions, temperature shifts, and noise on sensitivity. Additionally, selectivity, linearity, and transient response are analyzed to validate the proposed GaAs/GaSb PC-TFET biosensor's abilities. The assessment of all investigated results reveals that the proposed GaAs/GaSb PC-TFET biosensor is a promising candidate for biosensing applications. [ABSTRACT FROM AUTHOR]

To resist the advanced process variation and enable ultra-low power operation, static random-access memory (SRAM) undergoes an expansion stage. The most common type of memory is SRAM, which occupy more than 60% of the chip area. All memories have occupied more than 80% of the circuit area in that day's micro devices, and this trend is expected to continue. This paper develops into the deployment of SRAM using FinFET technology for implementation, with a primary objective of mitigating critical memory parameters, including parameters named as power dissipation, data retention and noise voltage. In this article, multiple simulations are carried out among conventional SRAM cells and FinFET based SRAM cells (6T, 7T, and 8T) utilizing the Cadence Virtuoso tool with a 45nm technology node. In modern era, FinFET is gaining increased preference over CMOS for high controllability of short-channel effects and flexible adjustment of threshold voltage (Vth) through the presence of a double gate. The thinner width of FinFET (Wfin) shows less degradation in performance in compared to thicker width of FET. To improve the circuit performance, the key factors like area, power and delay should be reduced. In the proposed SRAM cell using FinFET, power dissipation is lowered by 17% data retention voltage is reduced by 7% and noise voltage abridged up to 35% as compared to conventional SRAM cell. [ABSTRACT FROM AUTHOR]

Nanoscale Co/CoO/Co point contact devices are promising for spintronics, magnetic sensors, single-electron transistors, and memory devices. We fabricated Co/CoO/Co point contact devices and studied their random telegraph signal (RTS) characteristics at various temperatures. In the time domain, the current fluctuates asymmetrically with respect to zero bias, with RTS behavior emerging above a certain voltage threshold. In the frequency domain, the RTS power spectral density exhibits Lorentzian lines. As temperature increases from 50 to 300 K, two RTS behaviors are observed: at ≤100 K, the high current state dominates; at ≥200 K, the low current state prevails, with RTS absent at 150 K. Single exponential fitting shows that RTS state lifetimes decrease with temperature. The charge capture and release model explains the RTS origins and temperature-dependent behavior from an energy band perspective. This study provides insights into charge dynamics, single-electron transport, and the noise mechanisms affecting the reliability of nanoscale devices. [ABSTRACT FROM AUTHOR]

Polymer dispersed liquid crystals (PDLC) could function as an energy-efficient smart window, enabling the reversible transition between transparent and opaque states when applied bias voltages. However, the requirement for high switching voltages presents a challenge, resulting in severe energy consumption that contradicts objectives for sustainable energy conservation and emission reduction. Herein, this study synthesizes barium titanate/methyltrimethoxysilane/silver (BTO/MPTMS/Ag) composites successfully and incorporates it into the PDLC, designing for the low-energy-consumption smart window. Barium titanate nanowires (BTO NWs) enhance the dielectric constant of the PDLC film, while Ag nanoparticles (Ag NPs) exploit localized surface plasmon resonance (LSPR) to amplify the local electric field. Consequently, this synergistic effect of BTO NWs and Ag NPs reduces the threshold voltage and the saturation voltage to 10 V and 19 V, corresponding to decreases of 60 % and 62 %, respectively. Significantly, experiential results confirm that the incorporation of BTO/MPTMS/Ag nanoparticles does not affect the electro-optical nature of the PDLC film adversely. The work provides a promising approach for the preparation of advanced optical devices and energy-efficient equipment. [ABSTRACT FROM AUTHOR]