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In this work, three atomic layer deposition (ALD) approaches are used to deposit an Al2O3 gate insulator on n-GaN for application in vertical GaN power switches: thermal ALD (ThALD), plasma-enhanced ALD (PEALD), and their stacked combination. The latter is a novel method to yield the most ideal insulating layer. Also, the influence of an in situ NH3 or H2 plasma pre-treatment is studied. Planar MIS capacitors are used to investigate the electrical properties and robustness of the gate insulators. In vacuo x-ray photoelectron spectroscopy (XPS) is used to study the changes in chemical composition after every surface treatment. XPS shows that all plasma pre-treatments efficiently remove all carbon contamination from the surface, but only NH3 plasma is observed to additionally remove the native oxide from the n-GaN surface. The water precursor step in the ThALD process does not completely remove the CH3 ligands of the trimethylaluminum precursor step, which might electrically be associated with a reduced forward bias robustness. The O2 plasma step in the PEALD process is associated with the removal of carbon and a tremendous increase of the O content in the GaN surface region. Electrically, this strongly correlates to an enhanced forward bias robustness and an increased forward bias hysteresis, respectively. The ThALD/PEALD stack method mitigates the shortcomings of both ALD processes while maintaining its advantages. Electrical measurements indicate that the stack method alongside NH3 plasma pretreatment provides the best characteristics in terms of hysteresis, threshold voltage, forward bias robustness, and interface trap density of states. [ABSTRACT FROM AUTHOR]

In this work, we report on the fabrication of all-implanted β-Ga2O3 metal-oxide-semiconductor field-effect transistor (MOSFET) devices on semi-insulating (-201) β-Ga2O3 substrates. Through the use of multiple energy Si+ implantation and subsequent annealing, we were able to achieve high activation efficiencies up to 87% allowing to realize the active transistor channel and Ohmic contact regions with electrical properties comparable to homoepitaxial layers grown by metal-organic chemical vapor deposition. The fabricated β-Ga2O3 MOSFET devices featured excellent current modulation with on/off current ratios up to 109, maximum drain current densities of 180 mA/mm, and specific on-resistances of 1.5 mΩcm2. Furthermore, breakdown measurements in air of the non-field-plated MOSFET devices with a gate-to-drain distance of 2 μm showed a catastrophic breakdown at 332 V, which equals an average breakdown strength of 1.7 MV/cm. The outcome of this work emphasizes the high potential of this all-implantation approach for fabricating high-performing Ga2O3-based electronic devices for next-generation power electronics applications without the need of sophisticated high-quality epitaxial growth. [ABSTRACT FROM AUTHOR]

The development of processes for epitaxial growth of vertical gallium nitride (GaN) drift layers enabling 1.2 kV breakdown voltage on low‐cost sapphire substrates is presented in comparison to GaN bulk substrates. The targeted blocking capability demands drift layers with a thickness of 10 μm and low but controllable n‐type doping. Using a growth rate of 2.5 μm h−1 the concentration of unintentionally incorporated carbon is sufficiently low to adjust the n‐type carrier concentration to ≈1 × 1016 cm−3 for all types of substrates. To assess GaN drift region properties in terms of forward bias conductivity and reverse bias blocking strength, a quasi‐vertical p‐n‐diode structure is utilized. Bow reduction of GaN‐on‐sapphire structures is achieved using a stealth laser scribing process. Breakdown voltages higher than 1600 V and a specific on‐state resistance as low as 0.7 mΩ cm2 are obtained with diodes fabricated on GaN substrates. Similar structures grown on sapphire show breakdown voltages of about 1300 V due to higher levels of current leakage. Comparing different types of substrates, a direct correlation between dislocation density in the drift layer with the leakage current in p‐n diodes is deduced. [ABSTRACT FROM AUTHOR]

We present a detailed model of the static and dynamic gate leakage current in lateral β-Ga2O3 MOSFETs with an Al2O3 gate insulator, covering a wide temperature range. We demonstrate that (i) in the DC regime, current originates from Poole–Frenkel conduction (PFC) in forward bias at high-temperature, while (ii) at low temperature the conduction is dominated by Fowler–Nordheim tunneling. Furthermore, (iii) we modeled the gate current transient during a constant gate stress as effect of electron trapping in deep levels located in the oxide that inhibits the PF conduction mechanism. This hypothesis was supported by a TCAD model that accurately reproduces the experimental results. [ABSTRACT FROM AUTHOR]

In this paper, we extensively characterize and model the threshold voltage instability in lateral β-Ga2O3 MOSFETs with Al2O3 gate dielectric. Specifically, (i) the results indicate that the threshold voltage instability originates from electron trapping at gate dielectric border traps close to the Al2O3/β-Ga2O3 interface. (ii) Logarithmic kinetics were detected for both stress and recovery by means of a innovative fast-capacitance experimental setup, over more than seven decades of time; (iii) a generalized model, which is capable of accurately reproducing the experimental results, was proposed to explain this trend. [ABSTRACT FROM AUTHOR]