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In this work, three atomic layer deposition (ALD) approaches are used to deposit an Al2O3 gate insulator on n-GaN for application in vertical GaN power switches: thermal ALD (ThALD), plasma-enhanced ALD (PEALD), and their stacked combination. The latter is a novel method to yield the most ideal insulating layer. Also, the influence of an in situ NH3 or H2 plasma pre-treatment is studied. Planar MIS capacitors are used to investigate the electrical properties and robustness of the gate insulators. In vacuo x-ray photoelectron spectroscopy (XPS) is used to study the changes in chemical composition after every surface treatment. XPS shows that all plasma pre-treatments efficiently remove all carbon contamination from the surface, but only NH3 plasma is observed to additionally remove the native oxide from the n-GaN surface. The water precursor step in the ThALD process does not completely remove the CH3 ligands of the trimethylaluminum precursor step, which might electrically be associated with a reduced forward bias robustness. The O2 plasma step in the PEALD process is associated with the removal of carbon and a tremendous increase of the O content in the GaN surface region. Electrically, this strongly correlates to an enhanced forward bias robustness and an increased forward bias hysteresis, respectively. The ThALD/PEALD stack method mitigates the shortcomings of both ALD processes while maintaining its advantages. Electrical measurements indicate that the stack method alongside NH3 plasma pretreatment provides the best characteristics in terms of hysteresis, threshold voltage, forward bias robustness, and interface trap density of states. [ABSTRACT FROM AUTHOR]

The development of processes for epitaxial growth of vertical gallium nitride (GaN) drift layers enabling 1.2 kV breakdown voltage on low‐cost sapphire substrates is presented in comparison to GaN bulk substrates. The targeted blocking capability demands drift layers with a thickness of 10 μm and low but controllable n‐type doping. Using a growth rate of 2.5 μm h−1 the concentration of unintentionally incorporated carbon is sufficiently low to adjust the n‐type carrier concentration to ≈1 × 1016 cm−3 for all types of substrates. To assess GaN drift region properties in terms of forward bias conductivity and reverse bias blocking strength, a quasi‐vertical p‐n‐diode structure is utilized. Bow reduction of GaN‐on‐sapphire structures is achieved using a stealth laser scribing process. Breakdown voltages higher than 1600 V and a specific on‐state resistance as low as 0.7 mΩ cm2 are obtained with diodes fabricated on GaN substrates. Similar structures grown on sapphire show breakdown voltages of about 1300 V due to higher levels of current leakage. Comparing different types of substrates, a direct correlation between dislocation density in the drift layer with the leakage current in p‐n diodes is deduced. [ABSTRACT FROM AUTHOR]

The bias dependence of the external quantum efficiency (EQE) of bottom-illuminated Al0.5Ga0.5N/ AlN metal-semiconductor-metal photodetectors shows certain features which are directly related to the device geometry, i.e., the electrode design and the absorber layer thickness. Asymmetric detectors of any absorber thickness between 0.5 μm and 0.1 μm show a reduced EQE in reverse saturation. Furthermore, an enhanced EQE appears below the threshold either in reverse polarity for thick (i.e., 0.5 μm, 0.3 μm) or in forward polarity for thin (0.1 μm) AlGaN absorber layers. In order to understand the underlying physics of these phenomena, measured and simulated data are compared in the framework of a recently developed model for symmetric devices, taking into account defect-related non-radiative recombination and electric polarization effects. The electron capture time for recombination in the AlGaN absorber and the (background) donor density in the AlN buffer layer are the only parameters to be adjusted to reproduce all experimental trends qualitatively. [ABSTRACT FROM AUTHOR]

We compare the optical properties and device performance of unpackaged InGaN/GaN multiplequantum-well light-emitting diodes (LEDs) emitting at ~430 nm grown simultaneously on a high-cost small-size bulk semipolar (112 2) GaN substrate (Bulk-GaN) and a low-cost large-size (1122) GaN template created on patterned (1012) r-plane sapphire substrate (PSS-GaN). The Bulk-GaN substrate has the threading dislocation density (TDD) of ~105 cm-2-106cm-2 and basal-plane stacking fault (BSF) density of 0 cm-1, while the PSS-GaN substrate has the TDD of ~2 x 108 cm-2 and BSF density of ~1 x 10³ cm-1. Despite an enhanced light extraction efficiency, the LED grown on PSS-GaN has two-times lower internal quantum efficiency than the LED grown on Bulk-GaN as determined by photoluminescence measurements. The LED grown on PSS-GaN substrate also has about two-times lower output power compared to the LED grown on Bulk-GaN substrate. This lower output power was attributed to the higher TDD and BSF density. [ABSTRACT FROM AUTHOR]

We have studied the effect of continuous illumination with above band gap energy on the emission intensity of polar (Al)GaN bulk layers during the photoluminescence experiments. A temporal change in emission intensity on time scales from seconds to hours is based on the modification of the semiconductor surface states and the surface recombination by the incident light. The temporal behavior of the photoluminescence intensity varies with the parameters such as ambient atmosphere, pretreatment of the surface, doping density, threading dislocation density, excitation power density, and sample temperature. By means of temperature-dependent photoluminescence measurements, we observed that at least two different processes at the semiconductor surface affect the non-radiative surface recombination during illumination. The first process leads to an irreversible decrease in photoluminescence intensity and is dominant around room temperature, and the second process leads to a delayed increase in intensity and becomes dominant around T = 150-200 K. Both processes become slower when the sample temperature decreases from room temperature. They cease for T < 150K. Stable photoluminescence intensity at arbitrary sample temperature was obtained by passivating the analyzed layer with an epitaxially grown AlN cap layer. [ABSTRACT FROM AUTHOR]

A comprehensive study on top- and bottom-illuminated Al0.5Ga0.5N/AlN metal-semiconductor-metal (MSM) photodetectors having different AlGaN absorber layer thickness is presented. The measured external quantum efficiency (EQE) shows pronounced threshold and saturation behavior as a function of applied bias voltage up to 50V reaching about 50% for 0.1 lm and 67% for 0.5 μm thick absorber layers under bottom illumination. All experimental findings are in very good accordance with two-dimensional drift-diffusion modeling results. By taking into account macroscopic polarization effects in the hexagonal metal-polar +c-plane AlGaN/AlN heterostructures, new insights into the general device functionality of AlGaN-based MSM photodetectors are obtained. The observed threshold/saturation behavior is caused by a bias-dependent extraction of photoexcited holes from the Al0.5Ga0.5N/AlN interface. While present under bottom illumination for any AlGaN layer thickness, under top illumination this mechanism influences the EQE-bias characteristics only for thin layers. [ABSTRACT FROM AUTHOR]

In this study, the impacts of fabrication technology and epitaxial layer design on the transconductance (gm) of radio frequency AlGaN/GaN high‐electron‐mobility transistors (HEMTs) are examined. Optimization of the SiNx passivation and AlGaN barrier design of 150 nm gate HEMTs enhances the extrinsic (at Vds = 10 V) and intrinsic (at Vds = 15 V) transconductance from ≈0.47/0.65 to ≈0.62/1.1 S mm−1. Notably, an extrinsic gm of 0.70 S mm−1 at Vds = 5 V is achieved, setting a new benchmark for the extrinsic transconductance of AlGaN/GaN HEMTs designed for the K/Ka frequency range with a breakdown voltage exceeding 100 V. [ABSTRACT FROM AUTHOR]

In this study, we report on the application of multiple energy nitrogen ion implantation for the electrical isolation of electronic devices on monoclinic β-Ga2O3. By the introduction of uniformly distributed midgap damage-related levels in the Ga2O3 crystal lattice, we are able to increase the sheet resistances by more than 9 orders of magnitude to ≥1013 Ω/sq which remains stable up to annealing temperatures of 600 °C carried out for 60 s under a nitrogen atmosphere. At higher annealing temperatures, the damage-related trap levels are being removed causing a significant drop of the sheet resistance down to 4 × 105 Ω/sq for annealing temperatures of 800 °C. This effect is preceded by a structural recovery of the implantation damages via the recrystallization of the crystal lattice at already 400 °C as verified by x-ray diffraction measurements. The extracted activation energies of the deep states controlling the high resistivity of Ga2O3 after implantation are in the range of 0.7 eV, showing a strong correlation with the annealing temperature dependence of the sheet resistance and thus supporting the theory of a damage-induced isolation mechanism. [ABSTRACT FROM AUTHOR]

In this work, a vertical n‐channel MISFET homoepitaxially grown on ammonothermal n‐type GaN substrates by MOVPE is demonstrated. The MIS gate module consists of plasma enhanced atomic layer deposition of Al2O3 combined with in‐situ NH3 plasma surface pre‐treatment. An annealing step performed at 350 °C in N2 ambient drastically improves device performance. It reduces the ON‐state resistance from ≈12.0 k Ω mm to ≈150 Ω mm, increases the ON‐OFF ratio from 106 to 108, and lifts up Ids_max from  ≈ 0.25 to ≈ 40 mA mm−1. The threshold voltage is above +5 V and the median vertical off‐state blocking voltage strength is ≈68 V μm−1. Accumulated C–V characterization of planar MIS‐capacitors on n‐GaN gives insight to mechanisms boosting device performance after annealing. [ABSTRACT FROM AUTHOR]

The proposal, processing and performance of n+GaN/InGaN/AlGaN/GaN normally-off metal-oxide-semiconductor (MOS) HEMTs with a recessed 2-μm long gate/8-μm source-drain distance are presented. It is shown that by using a negative polarization charge at the InGaN/AlGaN interface together with 10-nm thick Al2O3 gate insulation, a threshold voltage VT increases by 3.6 V reaching a value of ∼1.6 V. Moreover, the combination of the gate recessing through the n+GaN cap and gate insulation lead to an invariant maximal drain current of about 0.25 A mm−1, as well as decreased gate leakage current in the order of ∼10−9 A mm−1. Analytical equations explain the predictive setting of VT up to 7 V with the oxide thickness tox increase, if holes compensate the negative polarization charge. By applying tox = 30 nm a VT ∼ 3 V was obtained; p-doping of the cap/barrier layers is suggested to reach the theoretically predicted scalability. [ABSTRACT FROM AUTHOR]