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An important use case for Vehicular Ad-hoc Networks (VANETs) is its application in the warning systems of emergency vehicles (EV). VANET-based vehicle-to-infrastructure (V2I) communication can be used to exchange important data and information between traffic lights and EVs, by means of transceivers at both ends. This communication helps in reducing the risks of accidents and also saves valuable time through an optimized orchestration of the traffic lights. This paper outlines the system design of an EV warning system that makes use of V2I communication. The system has been extensively studied in state-of-the-art simulators, such as SUMO and OMNeT++, in a huge variety of scenarios, where metrics for both time and safety have been collected. The results show that SafeSmart is highly effective in reducing trip times as well as increasing the overall safety of EVs in emergency scenarios. © 2013 IEEE., Safety of Connected Intelligent Vehicles in Smart Cities—SafeSmart Project, Emergency Vehicle Traffic Light Pre-Emption in Cities—EPIC

One important use case for Vehicular Ad-hoc Networks (VANETs) are applications related to emergency vehicles (EV). V2I (Vehicle-to-Infrastructure) communication can provide the infrastructure and protocol stack necessary to establish a communication channel between the transceivers in the EVs and the ones in the traffic lights, reducing accident risks and also help save valuable time. This paper outlines the system design of an EV warning system that makes use of V2I communication. A prototype of the system has been tested in a traffic simulation environment including EVs and traffic lights. To evaluate the system we performed a simulation and conducted a performance comparison between the travel times for EVs in normal traffic and when the system is in use. © 2020 IFIP., Funding text: ACKNOWLEDGMENT: The research leading to the results reported in this work has received funding from the Knowledge Foundation in the framework of SafeSmart ”Safety of Connected Intelligent Vehicles in Smart Cities” Synergy project (2019-2023), Swedish Foundation for Strategic Research (SSF) in the framework of Strategic Mobility Program (2019-2020), and the ELLIIT Strategic Research Network. This support is greatly acknowledged.

Networks-on-Chip (NoCs) are emerging as the way to interconnect the processing cores and the memory within a chip multiprocessor. As recent years have seen a significant increase in the number of cores per chip, it is crucial to guarantee the scalability of NoCs in order to avoid communication to become the next performance bottleneck in multicore processors. Among other alternatives, the concept of Wireless Network-on- Chip (WNoC) has been proposed, wherein on-chip antennas would provide native broadcast capabilities leading to enhanced network performance. Since energy consumption and chip area are the two primary constraints, this work is aimed to explore the area and energy implications of scaling a WNoC in terms of (a) the number of cores within the chip, and (b) the capacity of each link in the network. To this end, an integral design space exploration is performed, covering implementation aspects (area and energy), communication aspects (link capacity) and networklevel considerations (number of cores and network architecture). The study is entirely based upon analytical models, which will allow to benchmark the WNoC scalability against a baseline NoC. Eventually, this investigation will provide qualitative and quantitative guidelines for the design of future transceivers for wireless on-chip communication., Peer Reviewed, Postprint (author’s final draft)

[EN]: AD4G project is a subproject of a coordinated project named ARAMIS. The project aimed at contributing to the efficient design of adaptive analog, mixed-signal and Radio Frequency (RF) CMOS integrated circuits for multi-standard wireless transceivers. In particular, the project addressed the design of both RF front-ends and analog and mixed-signal back-end subsystems as well as their supporting design methodologies. The main activities carried out in the project were the following: Development of a systematic design methodology to allow the optimization of multi-standard transceivers in terms of system planning, block partitioning, adaptability, and minimization of the silicon area and power dissipation; Design of innovative RF front-ends capable of efficiently adapting to the different standards included in 4G systems as well as the different signal conditioning; Design of adaptive Analog/Digital interfaces, reconfigured at both architecture- and circuit- level, in order to allow the baseband processor to adapt its performance to the different standard specifications with optimized power consumption, [ES]: El proyecto es un subproyecto del proyecto coordinado ARAMIS, que tenía como objetivo fundamental el diseño sistemático de circuitos integrados CMOS adaptativos analógicos, de señal mixta y de Radio Frecuencia (RF) para sistemas de comunicación inalámbricos multi-estándar con aplicación en la cuarta generación (4G) de telefonía móvil. El proyecto incluyó tanto actividades metodológicas como de diseño de circuitos integrados, agrupadas en las siguientes tres líneas de trabajo: Desarrollo de metodologías de diseño para la optimización de transceptores inalámbricos con aplicación en sistemas de comunicación multi-estándar; Diseño de entrefases Analógico-Digitales (A/D) adaptativas y reconfigurables para sistemas de comunicación 4G; Diseño de cabeceras RF innovadoras, capaces de adaptar de forma eficiente sus prestaciones a las especificaciones requeridas por los estándares incluidos en 4G.

[EN]: AD4G project is a subproject of a coordinated project named ARAMIS. The project aimed at contributing to the efficient design of adaptive analog, mixed-signal and Radio Frequency (RF) CMOS integrated circuits for multi-standard wireless transceivers. In particular, the project addressed the design of both RF front-ends and analog and mixed-signal back-end subsystems as well as their supporting design methodologies. The main activities carried out in the project were the following: Development of a systematic design methodology to allow the optimization of multi-standard transceivers in terms of system planning, block partitioning, adaptability, and minimization of the silicon area and power dissipation; Design of innovative RF front-ends capable of efficiently adapting to the different standards included in 4G systems as well as the different signal conditioning; Design of adaptive Analog/Digital interfaces, reconfigured at both architecture- and circuit- level, in order to allow the baseband processor to adapt its performance to the different standard specifications with optimized power consumption, [ES]: El proyecto es un subproyecto del proyecto coordinado ARAMIS, que tenía como objetivo fundamental el diseño sistemático de circuitos integrados CMOS adaptativos analógicos, de señal mixta y de Radio Frecuencia (RF) para sistemas de comunicación inalámbricos multi-estándar con aplicación en la cuarta generación (4G) de telefonía móvil. El proyecto incluyó tanto actividades metodológicas como de diseño de circuitos integrados, agrupadas en las siguientes tres líneas de trabajo: Desarrollo de metodologías de diseño para la optimización de transceptores inalámbricos con aplicación en sistemas de comunicación multi-estándar; Diseño de entrefases Analógico-Digitales (A/D) adaptativas y reconfigurables para sistemas de comunicación 4G; Diseño de cabeceras RF innovadoras, capaces de adaptar de forma eficiente sus prestaciones a las especificaciones requeridas por los estándares incluidos en 4G

This paper introduces a frequency plan evaluation too] for multi-hand, multi-standard wireless transceivers. The implemented algorithm allows RF engineers to systematically analyze the effects of the intermodulation products as well as the harmonic components associated with the input signals, the local oscillator and interfering signals. The effect of the out of-band blockers is also evaluated. This provides very valuable information that helps finding the best intermediate frequency and filter bandwidths to the designer. This evaluation tool is part of a suite of tools called TACT, the purpose of which is to explore the design space of multi-standard radio transceivers. Simulation results on a multi-band WCDMA system verify the validity of the implemented frequency planning scheme., QC 20100907

A tester for testing multiconductor cable having a first tester is connectable to a first end of the multiconductor cable. The first tester produces one or more test signals individually on each conductor of the cable. A second tester is connectable to the second end of the cable at a remote location. The second tester monitors each of the plurality of separate conductors to detect the test signals produced by the first tester. Preferably, a first wireless transceiver is provided for the first tester that wirelessly transmits control signals to automatically coordinate testing procedure control. A second wireless transceiver joined to the second tester wirelessly transmits test result data.

The overall goal of this research project is to develop low-power personal communications transceiver hardware technologies, coupled with advanced systems techniques such as antenna diversity, channel coding, and adaptive power control, for achieving robust wireless digital data transmission over multipath fading channels. A frequency hopped, spread spectrum (FH/SS), code division, multiple access (CDMA) technique was chosen over other multiple access schemes because: (a) it provides an inherent immunity to multipath fading and (b) signal processing is performed at the hopping rate, which is much slower than the chip rate encountered either in a direct sequence (1)S) CDMA or time division, multiple access (TDMA) system, thereby potentially resulting in much lower receiver power consumption. The project is organized into four major tasks: (1) System Architecture/Performance Evaluation (Prof. C. Pottie) (2) Receiver Architecture/Signal Processing (Prof. H. Samueli) (3) Analog Systems/Circuits (Prof. A. Abidi) (4) Miniature Antenna Design (Prof. Y. Rahmat-Samii)

Předložená dizertační práce se zabývá hardwarovými nedokonalostmi rádiových transceiverů – zejména experimentálními měřicími test-bedy a technikami pro kompenzaci těchto nedokonalostí, ale na druhé straně také jejich využitím k zvýšení bezpečnosti při komunikaci mezi bezdrátovými zařízeními. Cílem první části práce je uvést danou problematiku, formulovat výzkumné otázky a poskytnout stručný přehled v oblasti hardwarových nedokonalostí a digitálních předzkreslovačů s nízkou výpočetní náročností, a dále seznámit čtenáře se základními metodami pro klasifikaci. Za nejdůležitější součást úvodní části práce je pak možné považovat přehled dosavadního vývoje v oblasti test-bedů pro experimenty s hardwarovými nedokonalostmi transceiverů v pásmu milimetrových vln. Jádro dizertační práce je tvořeno osmi vybranými publikovanými pracemi, doplněnými dílčími doplňujícími informacemi o provedených experimentech. Tři z těchto prací se zabývají využitím hardwarových nedokonalostí pro zvýšení bezpečnosti při komunikaci, dvě práce jsou zaměřeny na číslicové předzkreslení s nízkou výpočetní náročností, a zbývající tři publikace popisují měřicí test-bed v pásmu 60 GHz vytvořený na Ústavu radioelektroniky VUT v Brně., This thesis deals with the hardware imperfections of wireless transceivers – dominantly with the measurement setups and techniques for their compensation, but also with their exploitation providing the additional physical layer security. The first part of the thesis consists of brief introduction to the domain of research, formulation of research questions, and introductory part providing brief discussion of wireless front-end impairments, low-complexity digital predistorters, or basic classifiers. The most important section of this part then contains description of the state-of-the art mm-wave experimental setups. The core of the dissertation is composed as a selection of eight published papers complemented with the selected additional information on the hardware or experiments carried on. Three of the papers have dealt with RF impairments exploitation for transmitter authentication, two other focus on the implementation of low-complexity digital predistorters for power amplifier nonlinearity, and remaining three describe our millimeter-wave testbeds together with the achieved results of digital impairment compensation in 60 GHz band.

Předložená dizertační práce se zabývá hardwarovými nedokonalostmi rádiových transceiverů – zejména experimentálními měřicími test-bedy a technikami pro kompenzaci těchto nedokonalostí, ale na druhé straně také jejich využitím k zvýšení bezpečnosti při komunikaci mezi bezdrátovými zařízeními. Cílem první části práce je uvést danou problematiku, formulovat výzkumné otázky a poskytnout stručný přehled v oblasti hardwarových nedokonalostí a digitálních předzkreslovačů s nízkou výpočetní náročností, a dále seznámit čtenáře se základními metodami pro klasifikaci. Za nejdůležitější součást úvodní části práce je pak možné považovat přehled dosavadního vývoje v oblasti test-bedů pro experimenty s hardwarovými nedokonalostmi transceiverů v pásmu milimetrových vln. Jádro dizertační práce je tvořeno osmi vybranými publikovanými pracemi, doplněnými dílčími doplňujícími informacemi o provedených experimentech. Tři z těchto prací se zabývají využitím hardwarových nedokonalostí pro zvýšení bezpečnosti při komunikaci, dvě práce jsou zaměřeny na číslicové předzkreslení s nízkou výpočetní náročností, a zbývající tři publikace popisují měřicí test-bed v pásmu 60 GHz vytvořený na Ústavu radioelektroniky VUT v Brně., This thesis deals with the hardware imperfections of wireless transceivers – dominantly with the measurement setups and techniques for their compensation, but also with their exploitation providing the additional physical layer security. The first part of the thesis consists of brief introduction to the domain of research, formulation of research questions, and introductory part providing brief discussion of wireless front-end impairments, low-complexity digital predistorters, or basic classifiers. The most important section of this part then contains description of the state-of-the art mm-wave experimental setups. The core of the dissertation is composed as a selection of eight published papers complemented with the selected additional information on the hardware or experiments carried on. Three of the papers have dealt with RF impairments exploitation for transmitter authentication, two other focus on the implementation of low-complexity digital predistorters for power amplifier nonlinearity, and remaining three describe our millimeter-wave testbeds together with the achieved results of digital impairment compensation in 60 GHz band.

Předložená dizertační práce se zabývá hardwarovými nedokonalostmi rádiových transceiverů – zejména experimentálními měřicími test-bedy a technikami pro kompenzaci těchto nedokonalostí, ale na druhé straně také jejich využitím k zvýšení bezpečnosti při komunikaci mezi bezdrátovými zařízeními. Cílem první části práce je uvést danou problematiku, formulovat výzkumné otázky a poskytnout stručný přehled v oblasti hardwarových nedokonalostí a digitálních předzkreslovačů s nízkou výpočetní náročností, a dále seznámit čtenáře se základními metodami pro klasifikaci. Za nejdůležitější součást úvodní části práce je pak možné považovat přehled dosavadního vývoje v oblasti test-bedů pro experimenty s hardwarovými nedokonalostmi transceiverů v pásmu milimetrových vln. Jádro dizertační práce je tvořeno osmi vybranými publikovanými pracemi, doplněnými dílčími doplňujícími informacemi o provedených experimentech. Tři z těchto prací se zabývají využitím hardwarových nedokonalostí pro zvýšení bezpečnosti při komunikaci, dvě práce jsou zaměřeny na číslicové předzkreslení s nízkou výpočetní náročností, a zbývající tři publikace popisují měřicí test-bed v pásmu 60 GHz vytvořený na Ústavu radioelektroniky VUT v Brně., This thesis deals with the hardware imperfections of wireless transceivers – dominantly with the measurement setups and techniques for their compensation, but also with their exploitation providing the additional physical layer security. The first part of the thesis consists of brief introduction to the domain of research, formulation of research questions, and introductory part providing brief discussion of wireless front-end impairments, low-complexity digital predistorters, or basic classifiers. The most important section of this part then contains description of the state-of-the art mm-wave experimental setups. The core of the dissertation is composed as a selection of eight published papers complemented with the selected additional information on the hardware or experiments carried on. Three of the papers have dealt with RF impairments exploitation for transmitter authentication, two other focus on the implementation of low-complexity digital predistorters for power amplifier nonlinearity, and remaining three describe our millimeter-wave testbeds together with the achieved results of digital impairment compensation in 60 GHz band.