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Copyright of Information & Control is the property of Gai Kan Bian Wei Hui and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The lithography process in semiconductor dynamic random-access memory (DRAM) fabrication plants (fabs) is usually a major bottleneck, and reticle scheduling is complicated by process-specific constraints such as diversity of the product mix and rapidly changing deadlines. This study proposes a three-phase scheduling framework to solve the multi-objective reticle scheduling problem, reducing capacity loss, maintaining line balance and meeting customer demand. The genetic algorithm (GA) and the technique for order preference by similarity to ideal solution (TOPSIS) are used to optimize the scheduling with a trade-off among the multiple objectives. This study tests the proposed framework based on a real semiconductor DRAM (fab) in Taiwan, which has two unrelated parallel machines in its lithography process. The study finds that the proposed framework results in better scheduling reports, reduced computation times and improvements in the overall performance of lithography equipment. [ABSTRACT FROM AUTHOR]

Semiconductor fabrication is the process of manufacturing semiconductor devices, typically integrated circuits (ICs) such as microprocessors and memory. This involves transferring circuit diagrams onto a silicon wafer using photomasks and photoresists. After a series of fabrication processes, ICs are created on the wafer surface and then diced into individual chips, which are packaged and tested with quality control procedures to become the final products. Virtual reality (VR) simulates imaginary experiences or environments difficult to achieve in the real world through human senses and immersive equipment, allowing users to interact in a virtual 3D space in real time, making it well suited for applications in science education and industrial training. This study transforms the essential knowledge of advanced semiconductor manufacturing processes into an easily understandable virtual teaching module, thereby creating educational resources for high school and college students. The objective is to enhance their scientific and technological literacy, yielding substantial benefits for the general public. This study utilized VR technology to simplify and clarify the knowledge about the semiconductor manufacturing process, making it more engaging for learners. The virtual teaching module's learning content includes an overview of wafer preparation, semiconductor fabrication, chip packaging, and IC testing. Users can interact with the virtual teaching module and conduct virtual experiments to enhance their understanding by trial and error. Experimental results show that it can improve students' learning achievement and learning motivation. Therefore, the virtual teaching module is suitable for high‐school students and the general public to understand semiconductor technology and its applications. The effectiveness of the virtual teaching module is heavily dependent on the availability and quality of VR hardware and software. Limited access to advanced VR equipment or technical issues could have affected the learning experience, thereby influencing the learning outcomes. [ABSTRACT FROM AUTHOR]

Copyright of Control Theory & Applications / Kongzhi Lilun Yu Yinyong is the property of Editorial Department of Control Theory & Applications and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In the current industry, quality inspection in semiconductor manufacturing is of immense significance. Significant achievements have been made in fault diagnosis in fabricated semiconductor wafer manufacturing due to the development of machine learning. Since real-time intermediate signals are non-linear and time-varying, the signals undergo various distortions due to changes in equipment, material, and process. This leads to a drastic change in information in intermediate signals. This paper presents a fault diagnosis model for semiconductor manufacturing processes using a generative adversarial network (GAN). The study aims to address the challenges associated with efficient and accurate fault identification in these complex processes. Our approach involves the extraction of relevant components, development of a paired generator model, and implementation of a deep convolutional neural network. Experimental evaluations were conducted using a comprehensive dataset and compared against six existing models. The results demonstrate the superiority of our proposed model, showcasing higher accuracy, specificity, and sensitivity across various shift tasks. This research contributes to the field by introducing a novel approach for fault diagnosis, paving the way for improved process control and product quality in semiconductor manufacturing. Future work will focus on further optimizing the model and extending its applicability to other manufacturing domains. [ABSTRACT FROM AUTHOR]

In the current industry, quality inspection in semiconductor manufacturing is of immense significance. Significant achievements have been made in fault diagnosis in fabricated semiconductor wafer manufacturing due to the development of machine learning. Since real-time intermediate signals are non-linear and time-varying, the signals undergo various distortions due to changes in equipment, material, and process. This leads to a drastic change in information in intermediate signals. This paper presents a fault diagnosis model for semiconductor manufacturing processes using a generative adversarial network (GAN). The study aims to address the challenges associated with efficient and accurate fault identification in these complex processes. Our approach involves the extraction of relevant components, development of a paired generator model, and implementation of a deep convolutional neural network. Experimental evaluations were conducted using a comprehensive dataset and compared against six existing models. The results demonstrate the superiority of our proposed model, showcasing higher accuracy, specificity, and sensitivity across various shift tasks. This research contributes to the field by introducing a novel approach for fault diagnosis, paving the way for improved process control and product quality in semiconductor manufacturing. Future work will focus on further optimizing the model and extending its applicability to other manufacturing domains. [ABSTRACT FROM AUTHOR]

Semiconductor wafer fabrication is a complicated and time-consuming production process in the semiconductor manufacturing industry. It is very important for the manufacturer to come up with production plans that can most efficiently utilise the manufacturing equipment and fulfil customer orders placed in a planning horizon. Because of the complexity of the manufacturing processes, it is necessary to use high-fidelity discrete-event simulations to provide accurate estimates of delivery lead time for any given production plan. However, high-fidelity simulations are time-consuming, and thus decision-makers may only evaluate a small number of production plans once customer orders are received. In this paper, we propose the use of a multi-fidelity simulation optimisation approach to efficiently evaluate and select the best production plan from a large set of alternative plans under consideration. We develop an open queue approximation model for a wafer fabrication system and then use the low-fidelity estimates of lead times obtained from the approximation model in a recently developed multi-fidelity simulation optimisation method. Simulation experiment results show that the multi-fidelity approach significantly improves the computational efficiency of simulation-based production planning. [ABSTRACT FROM AUTHOR]

The wafer transfer robot is a key part of integrated circuit equipment which performs the transit of wafers precisely, quickly and steadily. The dynamic accuracy of the manipulator of the wafer transfer robot directly affects the quality of transferring and processing wafers and even the scheduling and control of the cluster tools. Thus, it is essential to study the influence of the dynamic accuracy of the manipulator of wafer transmission robots on the scheduling and control of cluster tools. In this paper, single-arm cluster tools are taken as the research object. The horizontal torsional vibration equations of the manipulator of the $R$ - $\theta $ robot are constructed, and the torsional vibration attenuation characteristics of the manipulator are analyzed. Based on the torsional vibration equations, the intrinsic relationships between the dynamic accuracy of the manipulator and the waiting times of the manipulator are explored when the manipulator loads and unloads the wafers. Then the two-stage approach is proposed for the scheduling and control of single-arm cluster tools. The first stage determines the minimum waiting times of the manipulator according to the intrinsic relationships between the dynamic accuracy of the manipulator and the waiting times of the manipulator when the manipulator is waiting for loading and unloading wafers in each processing module and load lock. The second stage achieves the scheduling optimization and control of single-arm cluster tools with dynamic accuracy constraints and wafer residency time constraints by establishing a mathematical programming model for the scheduling and control of single-arm cluster tools. Finally, illustrative examples are presented to analyze the influence of the dynamic accuracy of the manipulator on the scheduling and control of single-arm cluster tools.

Copyright of China Mechanical Engineering is the property of Editorial Board of China Mechanical Engineering and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Optimal cyclic scheduling problems of wafer-residency-time-constrained dual-arm cluster tools in wafer fabrication are challenging and remain to be fully solved. Existing studies assume that all processing modules (PMs) of a required type are used to process the same type of wafers. This sometimes brings unneeded conservativeness to scheduling results, because we may be able to make a tool schedulable by reducing the number of PMs in some steps if the original one is not. In some cases, we may use fewer PMs to reach the same result if the original one is schedulable, thus saving energy and other production resources. This work selects a proper number of PMs of needed types to process wafers while ensuring the highest productivity of a wafer-residency-time-constrained dual-arm cluster tool. It proposes the necessary and sufficient conditions under which a tool is schedulable. It then develops a polynomial-complexity algorithm that finds an optimal cyclic schedule. Examples are given to show its superiority over existing ones, thus advancing this field of cluster tool scheduling greatly and helping semiconductor producers to realize the green manufacturing of wafers. [ABSTRACT FROM AUTHOR]

Objectives Peak exposure to extremely low-frequency magnetic fields (ELF-MF) among semiconductor workers was characterized by type of factory, operation, and job. Methods A portable EMDEX meter was used to monitor the ELF-MF exposure of 117 semiconductor workers who are involved in wafer fabrication (fab) and assembly operations. ELF-MF measurements were logged every 3 s and categorized by process and job or activity during working hours. Two values of 0.5 and 1 μT were adopted subjectively as cutoff values of peak exposure levels based on a literature review. Results All semiconductor workers who were involved in diffusion, ion implanter operation, module, and chip test were exposed to ELF-MF higher than 0.5 μT during their entire working time. Engineers who maintained electric facilities in the semiconductor operations were exposed to the highest ELF-MF peak levels (2.5 μT on average above 0.5 μT and 3.6 μT on average above 1 μT). Operators working in chip testing showed the highest daily contribution of their peak levels to their daily average ELF-MF exposure levels (98.1% and 83.9%). In contrast, chemical mechanical planarization engineers, wafer test operators, and administrative workers outside clean rooms showed average exposure to less than 0.5 μT and a low proportion of duration of time exposed above either the 0.5 μT or 1 μT peak level points, along with a low daily contribution of peak exposure levels (16.0, 11.9, and 18.7%). Conclusions Most of the activities and working locations next to machines generating ELF-MF in semiconductor operations showed high contributions of ELF-MF peak exposure to daily exposure dose despite their relative minor fraction of workers' daily time. [ABSTRACT FROM AUTHOR]

To address the issues of cracking and cleavage commonly encountered during conventional mechanical processing of gallium oxide (Ga 2 O 3) crystals using several methods, such as outer circle cutting and diamond wire sawing, this study proposed a liquid-immersion wire-cut electrical discharge machining (WEDM) technique. This study also revealed that the segregation phenomena during the growth of Ga 2 O 3 crystals resulted in non-uniform resistivity within the crystal, leading to the failure of traditional spray-type electro-discharge wire-cutting techniques. To overcome this limitation, the feasibility of the liquid-immersion WEDM technique was proposed, and an experimental platform was established. Resistivity measurements of the cut surfaces of Ga 2 O 3 in kerosene immersion revealed a reduction of approximately 99.2 % in the resistivity difference. This result shows that the formation of carbon films during processing can effectively compensate for the intrinsic non-uniform resistivity. An equivalent circuit model for liquid-immersion WEDM of Ga 2 O 3 crystals in kerosene was developed. Thermodynamic and kinetic analyses were conducted on hydrocarbon decomposition reactions in kerosene at discharge temperatures. The results confirmed that decomposition reactions could occur during the discharge process. A truncation experiment for Ga 2 O 3 ingots was conducted, and a method using single-crystal silicon for electrical assistance in the processing of 1-inch wafers was proposed. The experimental results showed that liquid-immersion WEDM of Ga 2 O 3 crystals in kerosene effectively suppressed cracking and cleavage, achieving a processing accuracy within 50 μm and successfully producing a 1-inch circular Ga 2 O 3 wafer, with the machining accuracy improved by approximately 66.6 % compared to diamond wire cutting. • This paper proposes a method for the liquid-immersion wire-cut electrical discharge machining (WEDM) technique of gallium oxide crystals. And kerosene was used as processing medium. • An equivalent circuit model for liquid-immersion WEDM of Ga 2 O 3 crystals in kerosene was developed. Thermodynamic and kinetic analyses were conducted on hydrocarbon decomposition reactions in kerosene at discharge temperatures. • A truncation experiment for Ga 2 O 3 ingots was conducted, and a method using single-crystal silicon for processing of 1-inch wafers was proposed, achieving a processing accuracy within 50 μm. [ABSTRACT FROM AUTHOR]

Cluster tools play a significant role in the entire process of wafer fabrication. As the width of circuits in semiconductor chips shrinks down to less than 10nm, strict operational constraints are imposed on the operations of cluster tools in order to ensure the quality of processed wafers. Particularly, wafer residency time constraints and chamber cleaning requirements are commonly seen in etching, chemical vapor deposition, coating processes, etc. They make the scheduling problem of cluster tools more challenging. This work aims to provide a solution for dual-arm cluster tools with wafer residency time constraints and chamber cleaning requirements. To do so, it proposes a novel virtual wafer-based scheduling method. By this method, under a steady state, a PM processes either a real or virtual wafer at a time. When a PM processes a virtual one, its chamber can perform a cleaning operation. In this way, we can meet not only the strict residency time constraints for real wafers, but also innovatively meet chamber cleaning requirements. Based on such a novel scheduling method, an efficient binary integer programming model is established to optimize the throughput of cluster tools. Finally, experiments are performed to show the efficiency and effectiveness of the proposed method. Note to Practitioners—To ensure wafer quality in semiconductor manufacturing, engineers have to impose wafer residency time constraints and chamber cleaning requirements on the operations of cluster tools. In order to tackle their scheduling problem with these constraints, this work proposes a novel method based on the use of virtual wafers. Under a one-cyclic schedule obtained for time-constrained cluster tools without chamber cleaning requirements, virtual wafers are loaded into the tool such that when a PM processes a virtual wafer, a chamber cleaning operation can be performed in practice. The key to solve this scheduling problem is to find a wafer loading sequence with the highest performance in terms of cycle time. To do so, this work establishes an efficient binary integer programming model to search for such a solution. Since the obtained solution is a periodical wafer loading sequence based on a one-wafer cyclic schedule, it can be easily implemented. Therefore, this work has a high practical value to numerous semiconductor manufacturers. [ABSTRACT FROM AUTHOR]

In smart manufacturing, engineers typically analyze unexpected real-time problems using digitally cloned discrete-event (DE) models for wafer fabrication. To achieve a faster response to problems, it is essential to increase the speed of DE simulations because making optimal decisions for addressing the issues requires repeated simulations. This paper presents a hierarchical aggregation/disaggregation (A/D) method that substitutes complex event-driven operations with two-layered abstracted models—single-group mean-delay models (SMDMs) and multi-group MDMs (MMDMs)—to gain simulation speedup. The SMDM dynamically abstracts a DE machine group’s behaviors into observed mean-delay constants when the group converges into a steady state. The MMDM fast-forwards the input lots by bypassing the chained processing steps in multiple steady-state groups until it schedules the lots for delivery to subsequent unsteady groups after corresponding multi-step mean delays. The key component, the abstraction-level converter (ALC), has the roles of MMDM allocation, deallocation, extension, splitting, and controls the flow of each group’s input lot by deciding the destination DE model, SMDM, and MMDMs. To maximize the reuse of previously computed multi-step delays for the dynamically changing MMDMs, we propose an efficient method to manage the delays using two-level caches. Each steady-state group’s ALC performs statistical testing to detect the lot-arrival change to reactivate the DE model. However, fast-forwarding (FF) results in incorrect test results of the bypassed group’s ALCs due to the missed observations of the bypassed lots. Thus, we propose a method for test-sample reinitialization that considers the bypassing. Moreover, since a bypassed group’s unexpected divergence can change the multi-step delays of previously scheduled events, a method for examination of FF history is designed to trace the highly influenced events. This proposed method has been applied in various case studies, and it has achieved speedups of up to about 5.9 times, with 2.5 to 8.3% degradation in accuracy.

Nowadays, cluster tools tend to concurrently process multiple types of wafers with similar recipes in order to improve their utilization and flexibility in semiconductor manufacturing. Different wafer types may have different wafer flow patterns, resulting in that cluster tools are deadlock-prone. It is challenging to develop a general method to solve the deadlock problem of cluster tools without restriction on the wafer types. This work aims at solving such a challenging problem for single-arm cluster tools. To do so, a general Petri net model is developed for single-arm cluster tools. Given the wafer flow patterns of all wafer types to be processed in a single-arm cluster tool, such a Petri net model can be easily obtained by defining the relationship between places and transitions. Then, a control method by using self-loops is presented to prevent the model from deadlocks during the evolutions from the initial state to the final state. Furthermore, such a control method is proved to be optimal. Illustrative examples are given to verify the proposed method at last.

In wafer fabrication, it is imperative to minimize the transient process of cluster tools for the sake of on-demand and preventive maintenance. Due to the trend of multi-type and small-batch production, transient processes appear more and more frequently. Thus, the optimization problems of transient processes have gained increasing attention from both industry and academia. The requirement for wafer revisiting tend to complicate this problem significantly. However, only a few studies take such a challenge for cluster tools with wafer revisiting. This paper focuses on the schedule optimization of transient processes for dual-arm cluster tools with wafer revisiting. To accelerate transient processes, including both start-up and close-down ones, we adopt a program evaluation and review technique to analyze and harness a cluster tool’s state evolution. We then propose computationally efficient algorithms to speed up transient processes. Finally, we provide illustrative examples to show their applications and validate their effectiveness.

In order to improve the prompt delivery reliability of the semiconductor wafer fabrication system, a big data analytics (BDA) is designed to predict wafer lots’ cycle time (CT), which is composed by four parts: data acquisition, data pre-processing, data analysing and data prediction. Firstly, the candidate feature set is constructed to collecting all features by analysing the material flow of wafer foundry. Subsequently, a data pre-processing technique is designed to extract, transform and load data from wafer lot transactions data-set. In addition, a conditional mutual information-based feature selection process is proposed to select key feature subset to reduce the dimension of data-set through data analysing without pre-knowledge. To handle the large volumes of data, a concurrent forecasting model is designed to predict the CT of wafer lots in parallel as well. According to the numerical analysis, the predict accuracy of the presented BDA improves clearly with the increase in data size. And, in the large-scale data-set, the BDA has higher accuracy than linear regression and back-propagation network in CT forecasting. [ABSTRACT FROM PUBLISHER]

Real-time process monitoring is a vital technique to maintain safety and quality in the wafer fabrication processes. Hence, statistical process monitoring methods such as statistical process control chart, principal component analysis have been widely applied in wafer fabrication. However, these methods often suffer from the performance degradation problem caused by run-to-run (R2R) variations such as uneven duration and R2R drifts. In this paper, we propose a real-time monitoring framework for continuous wafer fabrication processes with uneven duration and R2R drifts. In this framework, processes are divided into several phases and further aligned in a real-time manner to solve the uneven duration problem. Then, R2R drifts are compensated by a down-sampling seasonal autoregressive integrated moving average model and a moving window multi-batch forecast strategy. Finally, multiphase multiway principal component analysis models are built on the compensated data to monitoring the processes. The efficiency of this framework is demonstrated by a case study on a plasma etch process. The results indicate that the proposed framework can diminish the influence of R2R variations and improve the monitoring model performance. [ABSTRACT FROM AUTHOR]

Nowadays, wafer fabrication in semiconductor manufacturing is highly dependent on cluster tools. A cluster tool is equipped with several process modules (PMs) and a wafer handling robot. When the tool is operating, generally each PM is processing a wafer, and the robot is responsible for delivering the wafers from one PM to another. Thus, when a wafer is completed in a PM, the robot may be busy for performing other tasks such that it cannot immediately unload the completed wafer in the PM, resulting in that the wafer has to stay there for some extra time. The processing time of a wafer together with its delay time for waiting for the robot’s arrival for unloading is defined as wafer residency time in a PM. However, a long wafer delay time may deteriorate its quality. Therefore, it is highly desired and important to reduce the wafer delay time at each step as much as possible. This work aims to tackle this important issue for single-arm cluster tools (SACTs). Specifically, by using a Petri net model, this work analyzes the steady-state operational behavior of an SACT under the backward and earliest starting strategies. It is found that there must exist wafer delay time at the steps in the upstream of the bottleneck step, and such wafer delay time can be reduced by properly adjusting the robot waiting time. Thus, three algorithms are developed to reduce the wafer delay time at each step as much as possible by properly assigning the robot idle time. Finally, the application of the proposed method is illustrated by using examples. Note to Practitioners—In a modern semiconductor fab, there are hundreds of cluster tools for wafer fabrication. To ensure wafer quality, it is important to reduce the wafer delay time in PMs of cluster tools after a wafer is processed since the high temperature, chemical gas, and particles in the PMs may damage the wafer. To do so, this work proposes three algorithms with polynomial complexity to assign the robot idle time as robot waiting time such that the wafer delay time in PMs can be reduced as much as possible. Furthermore, the obtained schedule by these algorithms is optimal in terms of the cycle time. Besides, the developed algorithms can be easily embedded into the controller of cluster tools by facility engineers. Therefore, this work has a practical value. [ABSTRACT FROM AUTHOR]

Speeding up the simulation of discrete-event wafer-fabrication models is essential for fast decision-making to handle unexpected events in smart semiconductor manufacturing because decision-parameter optimization requires repeated simulation execution based on the current manufacturing situation. In this paper, we present a runtime abstraction-level conversion approach for discrete-event fab models to gain simulation speedup. During the simulation, if the fab's machine group model reaches a steady state, then the proposed method attempts to substitute this group model with a mean-delay model (MDM) as a high abstraction level model. The MDM abstracts detailed event-driven operations of subcomponents in the group into an average delay based on the queuing modeling, which can guarantee acceptable accuracy in predicting the performance of steady-state queuing systems. To detect the steadiness, the proposed abstraction-level converter (ALC) observes the queuing parameters of low-level groups to identify the statistical convergence of each group's work-in-progress (WIP) level. When a group's WIP level is converged, the output-to-input couplings between the models are revised to change a wafer-lot process flow from the low-level group to a MDM. When the ALC detects lot-arrival changes or any wafer processing status change (e.g., a machine-down), the high-level model is switched back to its corresponding low-level group model. During high-to-low level conversion, the ALC generates dummy wafer-lot events to re-initialize the machine states. The proposed method was applied to various case studies of wafer-fab systems and achieved simulation speedups up to about 4 times with 0.6 to 8.3% accuracy degradations.

A fuzzy dynamic-prioritization agent-based system was developed in this study to improve the forecasting of the cycle time of a job in a wafer fabrication plant (wafer fab). In this system, multiple fuzzy agents forecast the cycle time of a job from various viewpoints, after which the aggregation and evaluation agent aggregates these fuzzy cycle time forecasts using an innovative operator (i.e., the fuzzy weighted intersection) into a single representative value. Subsequently, the optimization agent varies the authority levels of the fuzzy cycle time forecasting agents to optimize the forecasting performance. A practical example was used to evaluate the effectiveness of the fuzzy dynamic-prioritization agent-based system. The experiment results indicated that the fuzzy dynamic-prioritization agent-based system outperformed three rival methods in improving forecasting accuracy. In addition, the forecasting performance could be enhanced by discriminating the authority levels of the fuzzy cycle time forecasting agents. [ABSTRACT FROM AUTHOR]

Copyright of Control Theory & Applications / Kongzhi Lilun Yu Yinyong is the property of Editorial Department of Control Theory & Applications and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In semiconductor wafer fabrication (wafer fab), wafers go through hundreds of process steps on a variety of processing machines for electrical circuit building operations. One of the special features in the wafer fabs is that there exist batch processors (BPs) where several wafer lots are processed at the same time as a batch. The batch processors have a significant influence on system performance because the repetitive batching and de-batching activities in a reentrant product flow system lead to non-smooth product flows with high variability. Existing research on the BP control problems has mostly focused on the local performance, such as waiting time at the BP stations. This paper attempts to examine how much BP control policies affect the system-wide behavior of the wafer fabs. A simulation model is constructed with which experiments are performed to analyze the performance of BP control rules under various production environments. Some meaningful insights on BP control decisions are identified through simulation results. [ABSTRACT FROM AUTHOR]

Copyright of China Mechanical Engineering is the property of Editorial Board of China Mechanical Engineering and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This research presents several heuristics to optimise the location of crossovers in a conveyor-based automated material handling system (AMHS) for a semiconductor wafer fabrication facility. The objective is to determine the location of crossovers that minimises the total cost of the expected work-in-process on the conveyor and the cost of installing and operating the AMHS with the crossovers. The proposed heuristics are integrated with a queuing-based analytical model incorporating practical hardware considerations of the AMHS, such as turntables and crossovers. To illustrate the proposed heuristics’ practical application they are applied to SEMATECH's virtual wafer fabrication facility. Experimental results demonstrate that under a wide variety of operating conditions and cost scenarios the local improvement heuristic is able to identify the optimal solution and outperform other commonly used heuristics for layout design such as genetic algorithms. [ABSTRACT FROM PUBLISHER]

This paper investigates a new scheduling problem of multiple orders per job (MOJ) in a three-machine flowshop consisting of an item-processing machine, a lot-processing machine and a batch-processing machine, for a semiconductor manufacturing operation that must form a layer on the wafers. The three-machine flowshop MOJ scheduling problem deals with sequencing customer orders, assigning orders to jobs, and then combining the formed jobs into batches. Genetic algorithms are presented for this scheduling problem to minimise the total weighted tardiness (TWT), in the presence of non-zero order ready times, different order due dates, different order weights and unequal order sizes. Extensive experiments were performed to compare the proposed genetic algorithm (GA)-based approach with the benchmark heuristics presented in previous studies. The experiments led to the conclusions that the GA-based approach is significantly superior over other heuristics in terms of TWT and can find near-optimal solutions in an acceptable amount of computation time. [ABSTRACT FROM AUTHOR]

Capacity planning is crucial to the investment and performance of wafer fabs. This research proposes a practical procedure to calculate the required number of machines with serial and batch processing characteristics, respectively. Several formulae are first presented. Five heuristic algorithms are then proposed to determine the lower bound, the upper bound, and the near-optimal of the number of machines of the type with capability constraint. Data from real foundry fabs are used in a case study to determine the required number of 64 types of equipment and to evaluate the performance of the proposed procedure. The algorithm using the best ratio of production efficiency and equipment cost to select the machine type with capability constraint results in the least required number of machines, the highest machine utilisation, and the lowest equipment investment. An AutoSched AP simulation model is used to evaluate if a wafer fab using the calculated number of machines of each type can result in a preset monthly output rate. Simulation results indicate that the proposed procedure can quickly and accurately calculate the required number of machines leading to the required monthly production target. Fab managers can use this tool to conduct what-if analysis for equipment investment alternatives. [ABSTRACT FROM AUTHOR]

Based on the assumption of infinite capacity, a Capacity Requirements Planning System (CRPS) is developed for twin fabs of wafer fabrication. Several shared equipments exist only in one of the twin fabs linked by an Inter-Fab Material Handling System. CRPS consists of four major modules. WIP-Pulling Module pulls work-in-process (WIP) that is the closest to the end of the process route to meet the Master Production Schedule. Workload Accumulation Module then calculates the expected equipment loading in different time buckets. If WIP cannot meet the Master Production Schedule (MPS) requirement, new wafer lots need to be released. Wafer Release Time Module is used to determine the release time of new lots by evaluating their expected equipment loading at the twin fabs on various time buckets. According to the lot release time, Wafer Start Fab Module can be used to evaluate the expected loading for each of the twin fabs and determine the start fab to optimise the workload balance among these twin fabs on various days. Based on experimental design, simulation results show that CRPS can balance the equipment loading between the twin fabs with shared equipment, on various days, and across various equipments at various levels of demands. [ABSTRACT FROM AUTHOR]

Understanding the factors associated with the flow-time of wafer production is crucial for workflow design and analysis in wafer fabrication factories. Owing to wafer fabrication complexity, the traditional human approach to assigning the due-date is imprecise and prone to failure, especially when the shop status is dynamically changing. Therefore, assigning a due-date to each customer order becomes a challenge to production planning. The paper proposes a constraint-based genetic algorithm approach to determine the flow-time. The flow-time prediction model was constructed and compared with other approaches. Better computational effectiveness and prediction results from the constraint-based genetic algorithm are demonstrated using experimental data from a wafer-manufacturing factory. [ABSTRACT FROM AUTHOR]

The accurate cycle time (CT) prediction of the wafer fabrication remains a tough task, as the system level of work in process (WIP) is fluctuant. Aiming to construct one unified CT forecasting model under dynamic WIP levels, this paper proposes a transfer learning method for finetuning the predicted neural network hierarchically. First, a two-dimensional (2D) convolutional neural network was constructed to predict the CT under a primary WIP level with the input of spatial-temporal characteristics by reorganizing the input parameters. Then, to predict the CT under another WIP level, a hierarchical optimization transfer learning strategy was designed to finetune the prediction model so as to improve the accuracy of the CT forecasting. The experimental results demonstrated that the hierarchically transfer learning approach outperforms the compared methods in the CT forecasting with the fluctuation of WIP levels.

Copyright of Control Theory & Applications / Kongzhi Lilun Yu Yinyong is the property of Editorial Department of Control Theory & Applications and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

With the reduction of wafer batch size on account of the diversification and individuation of consumption demands, increasing importance has been attached to the schedulability and controllability of the cluster tools with multiple wafer types being concurrently processed, while the corresponding research is seldom and still open. This paper is devoted to addressing the steady-state scheduling of single-arm cluster tools with multiple wafer types and residency time constraints. Inspired by the definition of wafer flow pattern for the single wafer type, a novel description for the multiple wafer types is introduced. For the sake of efficiency and simplicity, the multiplex backward sequence is proposed. To balance the workload of process steps, a virtual module technology with a two-tiered architecture is implemented. Furthermore, several sufficient and necessary conditions are derived to verify the schedulability of the system. Finally, an efficient algorithm is presented to find the periodic steady-state schedule, and its practicability and availability are validated by the given illustrative examples. Note to Practitioners—Cluster tools are a kind of highly automated, flexible, and integrated equipment applied widely in diversified semiconductor fabrication processes. Due to the strictness of processing constraints and unavailability of in-built buffers, it is challenging to effectively operate cluster tools. For a higher utilization of processing modules, fabs tend to concurrently process several kinds of wafers with dissimilar recipes in a cluster tool. However, the related scheduling and control problems remain open. With residency time constraints, this paper addresses the scheduling problems of single-arm cluster tools with multiple wafer types. By dissecting the mechanism of mixed-processing of multiple wafer types, several formal conditions are obtained to test the schedulability. Based on the multiplex backward sequence, a cyclic scheduling approach to single-arm cluster tools with multiple wafer types is presented. With the proposed method, schedulability conditions can be readily checked and a periodic schedule can be found easily. Thus, it can be applied to solve practical application problems. [ABSTRACT FROM AUTHOR]

Since last decade, the cluster tool has been mainstream in modern semiconductor manufacturing factories. In general, the cluster tool occupies 60% to 70% of production machines for advanced technology factories. The most characteristic feature of this kind of equipment is to integrate the relevant processes into one single machine to reduce wafer transportation time and prevent wafer contaminations as well. Nevertheless, cluster tools also increase the difficulty of production planning significantly, particularly for shop floor control due to complicated machine configurations. The main objective of this study is to propose a short-term scheduling model. The noteworthy goal of scheduling is to maximize the throughput within time constraints. There are two modules included in this scheduling model—arrival time estimation and short-term scheduling. The concept of the dynamic cycle time of the product’s step is applied to estimate the arrival time of the work in process (WIP) in front of machine. Furthermore, in order to avoid violating the time constraint of the WIP, an algorithm to calculate the latest time of the WIP to process on the machine is developed. Based on the latest process time of the WIP and the combination efficiency table, the production schedule of the cluster tools can be re-arranged to fulfill the production goal. The scheduling process will be renewed every three hours to make sure of the effectiveness and good performance of the schedule.

In semiconductor wafer fabrication (wafer fab), wafers go through hundreds of process steps on a variety of processing machines for electrical circuit building operations. One of the special features in the wafer fabs is that there exist batch processors (BPs) where several wafer lots are processed at the same time as a batch. The batch processors have a significant influence on system performance because the repetitive batching and de-batching activities in a reentrant product flow system lead to non-smooth product flows with high variability. Existing research on the BP control problems has mostly focused on the local performance, such as waiting time at the BP stations. This paper attempts to examine how much BP control policies affect the system-wide behavior of the wafer fabs. A simulation model is constructed with which experiments are performed to analyze the performance of BP control rules under various production environments. Some meaningful insights on BP control decisions are identified through simulation results.

Most defect signatures on wafers are caused by faulty tools. If these defects are not captured by in-line inspection tools or sampled during Defect Review-SEM, they are carried over multiple processing steps and discovered at the end of the fabrication procedure. Wafers with different defect signatures discovered at the end of the fabrication procedure are, most often, processed through same faulty tools. The fabrication paths of most defective wafers converge at some point to form a common sub-path before they disperse again. Usually, faulty tools in this common path cause most of the different defect signatures discovered at the end of the fabrication procedure. Process engineers would need to trace in reverse the fabrication paths to identify this common path to repair its tools. We introduce in this paper a defect diagnostic system called IDFP that can identify the common fabrication path that caused most of the defectivities on wafers discovered at the end of the fabrication procedure. We evaluated the quality of IDFP by experimentally comparing it with two systems. Results revealed marked improvement.