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This article comprehensively reviews and studies CMOS transformer tank voltage‐controlled oscillators (VCOs) designed to improve the frequency tuning range (FTR) and minimize phase noise (PN) across a broad frequency range, particularly for mm‐wave and fifth‐generation applications. The study focuses on enhancing the performance of the oscillators to meet the demanding requirements of these advanced applications. This study thoroughly investigates and compares various strategies to increase the FTR, minimize PN, and reduce power dissipation in transformer tank VCOs. The aim is to establish fundamental guidelines for implementing transformer‐based tank VCOs. The study comprehensively reviews and analyzes the overall architecture of transformer‐based tank VCOs, presenting a detailed examination of the methods employed to enhance VCO performance. Additionally, the study illustrates the impact of the coupling factor on the VCO's performance parameters, detailing and demonstrating the overall tank circuit quality factor (Q) and resonator coupling factor (κ). A thorough understanding of PN methodology and the limitations of FTR has led to the development of innovative architectures. These include transformer‐based capacitive feedback (FB) oscillators with resistively adjusted variable inductors, as well as class‐F and inverse class‐F VCOs. These novel architectures contribute significantly to the improvement of oscillator performance. [ABSTRACT FROM AUTHOR]

The main objective of this paper is to present novel applications of two recently proposed CMOS transconductors in realizing voltage mode/current mode Tow–Thomas (TT)-equivalent biquads and a linear voltage-controlled oscillator (VCO), all exhibiting a number of advantages over the previously known circuits to realize the same functions. The workability of all the propositions has been demonstrated by SPICE simulation results using TSMC 0. 1 8 μ m CMOS technology parameters. [ABSTRACT FROM AUTHOR]

A novel active-inductor based VCO design, employing a 180 nm TSMC technology, is postulated in this work. The coarse frequency is obtained in this VCO system by regulating the MOS-based active inductor. This design provides a high oscillation frequency of 3.7 GHz and a tuning range of 99.25% when the voltage ranges from 1 to 2 V. The total power consumed by this active-inductor based VCO varies from 0.7 mW to 33.32 mW within the specified range. The achieved phase noise is − 107 dBc/Hz at 1 MHz offset frequency. The figure of merit measured is − 162.15 dBc/Hz. The results demonstrate that the proposed VCO functions more effectively than the existing VCOs. [ABSTRACT FROM AUTHOR]

A low-power single-core 24.5-to-29.1 GHz CMOS LC voltage-controlled oscillator (VCO) is presented. The proposed VCO uses an innovative differential cross-coupled architecture in which an additional pair is connected to the main pair to increase the effective transconductance, resulting in lower power consumption and reduced phase noise (PN). The proposed VCO is fabricated in a 1P9M standard CMOS process and sustains oscillation at 29.14 GHz with power consumption as low as 455 μW (650 μA from a 0.7 V supply), which is ~20% lower than a conventional CMOS LC VCO without Gm-enhanced differential pairs built through the same process (700 μA from 0.8 V supply). When consuming 880 μW (1.1 mA from 0.8 V), the proposed VCO exhibits a tuning range of 4.6 GHz (from 24.5 GHz to 29.1 GHz). Moreover, it exhibits a measured phase noise (PN) better than −106.5 dBc/Hz @ 1 MHz and −132.0 dBc/Hz @ 10 MHz, with figure-of-merit (FoM) results of 195.2 dBc/Hz and 200.3 dBc/Hz, respectively. [ABSTRACT FROM AUTHOR]

The study presents 1D discrete map (DM) to describe the dynamics of the oscillator with chaotic pulse position modulation. The model circuit has pulse voltage-controlled oscillator and feedback loop with a threshold of pulse rate coding, which performs nonretriggerable monostable multivibrator. DM is based on the analysis of this circuit using a simple approximation of the frequency modulation, which includes a threshold condition on the pulse period and sigmoid function of rate coding. The model circuit and DM demonstrate dynamic chaos in a wide range of control parameters. The transition to the chaos occurs by a jump either from a fixed point (tangent bifurcation) or from a limit cycle. An experimental (digital–analog) circuit of the chaotic pulse oscillator, in which the feedback unit is a monostable multivibrator with a microcontroller, is implemented. The maximum Lyapunov exponent and the maximum entropy of DM are on the edge of chaos and are close to the well-known Bernoulli shift map, the analogy with which is discussed. [ABSTRACT FROM AUTHOR]

In this paper, we present a fully integrated circuit without inductance implementing Chua's chaotic system. The circuit described in this study utilizes the SMIC 180 nm CMOS process and incorporates a multi-path voltage-controlled oscillator (VCO). The integral-differential nonlinear resistance is utilized as a variable impedance component in the circuit, constructed using discrete devices from a microelectronics standpoint. Meanwhile, the utilization of a multi-path voltage-controlled oscillator ensures the provision of an adequate oscillation frequency and a stable waveform for the chaotic circuit. The analysis focuses on the intricate and dynamic behaviors exhibited by the chaotic microelectronic circuit. The experimental findings indicate that the oscillation frequency of the VCO can be adjusted within a range of 198 MHz to 320 MHz by manipulating the applied voltage from 0 V to 1.8 V. The circuit operates within a 1.8 V environment, and exhibits power consumption, gain–bandwidth product (GBW), area, and Lyapunov exponent values of 1.0782 mW, 4.43 GHz, 0.0165 mm2, and 0.6435∼1.0012, respectively. The aforementioned circuit design demonstrates the ability to generate chaotic behavior while also possessing the benefits of low power consumption, high frequency, and a compact size. [ABSTRACT FROM AUTHOR]

This paper displays a voltage-controlled oscillator (VCO) with high performance implemented in 0.18 µm CMOS. The proposed CMOS VCO adopts a current-reused method, analog coarse and fine tuning mechanisms, and an adaptive overdrive voltage control structure to increase the overall performance, such as the power dissipation, phase noise, and tuning range, and has a robust start-up condition. The current-reused complementary structure with higher transistor transconductances is to save power consumption; the analog coarse and fine tuning mechanisms are to effectively widen the tuning range; and the adaptive overdrive voltage control technique is to change the transconductances of the transistors to improve power consumption by reasonably biasing the gate and body terminals in a class-AB mode to adjust the threshold voltage of the NMOS transistors. The proposed CMOS VCO adopts the class-AB mode to improve the overall performance and the start-up condition. The figure-of-merit (FOM) and FOM with tuning range (FOMT) are used in evaluating the CMOS VCO performance. The measured phase noise at 1 MHz and 10 MHz offsets is –130.34 dBc/Hz and –150.96 dBc/Hz at the 3.38 GHz operating frequency, respectively. The proposed CMOS VCO has a tuning range between 2.85 and 3.62 GHz corresponding to 23.8% for the fifth-generation (5G) wireless communication applications. The proposed CMOS VCO core using a 1.4-V supply consumes 7.5 mW DC power. The FOMs and FOMTs at 1- and 10-MHz offsets are −192.2, −192.8, −199.7, and −200.3 dBc/Hz, respectively, from the 3.38 GHz output frequency. [ABSTRACT FROM AUTHOR]

A complementary metal oxide semiconductor (CMOS) voltage‐controlled oscillator (VCO) using a tail current source modulated with the output frequency is presented to achieve low phase noise with low power consumption at the K‐band. Differentially modulated current sources, which reduce flicker noise by the feedback of the VCO outputs, contribute to an overall reduction in the phase noise of the VCO using the electromagnetic‐based fully symmetrical design. The proposed LC VCO with a 3‐bit switched capacitor bank for a wide tuning range was fabricated on the size of 0.4 × 0.57 mm2 using a 65‐nm CMOS process. The measurement results of the proposed VCO showed a frequency tuning range from 22.57 to 25.3 GHz, and a phase noise of −108.48 dBc/Hz at a 1‐MHz offset frequency with a power consumption of 8.27 mW at a supply voltage of 1.2 V. The calculated figure of merit (FoM) and FoM with the tuning range were −186.48 and −187.67 dBc/Hz, respectively. [ABSTRACT FROM AUTHOR]

Summary: The research and development on solid‐state source generators have been making progress on chip, aiming to generate low noise, high output power, and high DC‐to‐RF energy efficiency in the millimeter‐wave (mmW) and terahertz (THz) domains. In particular, their full integration in silicon technologies, such as advanced complementary‐metal‐oxide‐semiconductor processes, has motivated the design of low cost, high performance, and miniature integrated circuits (ICs). This manuscript focuses on providing a general overview of recent progress on solid‐state signal source operating beyond 60 GHz till the THz region, from the perspective of operating principle, design metrics, state‐of‐the‐art performance, testing results, and their applications in emerging mmW/THz systems. Finally, with the use of fully integrated source generators, several design arts are highlighted to showcase the recent advances of ICs toward millimeter‐wave and THz radiation, imaging, coupled oscillator network (CON), and communication. Potential future research directions enabled by mmW/THz signal sources will be envisioned. [ABSTRACT FROM AUTHOR]

This article presents a design of a VCO‐based ADC based on n‐type metal oxide thin‐film transistor (TFT). The TFTs are fabricated on a glass substrate using Indium Zinc Oxide technology. The VCO‐based ADC consists of a VCO, a level shifter and a sampling circuit, while the VCO is composed of a charge‐discharge cell and an inverter chain. The ADC has a 1.464 mm 2 area, 0.89 mW power consumption, an output frequency range of 1.41 KHz/V tuning sensitivity, 1.8% maximum linear error and achieves a SNDR of 34.2 dB in the case of an input signal of 1.5 Hz and a sampling rate of 20 S/s. [ABSTRACT FROM AUTHOR]

This paper deals with the design of a current-reuse active inductor. Current-reuse active inductor-based voltage-controlled oscillator (CRAI-VCO) with a wide tuning range is designed based on the proposed active inductor. The tuning range of VCO is from 1.25 to 2.5 GHz giving a tuning percentage of 68% at a power consumption of 5 mW. The phase noise obtained is −100 dBc/Hz. The post-layout simulations are carried out in Cadence Virtuoso using UMC 180 nm RFCMOS technology. The circuit occupies an active area of 143 µm × 148 µm. The figure of merit of VCO considering the frequency tuning range is −177.3 dBc/Hz comparable to other state-of-the-art VCO designs. [ABSTRACT FROM AUTHOR]

In this study, a 94 GHz PLL chip was designed using the integer-N PLL structure, and the results of a high-temperature test for the chip are discussed. The 94 GHz PLL was designed to exhibit a phase noise of −90 dBc/Hz or less at a 1 MHz offset frequency using a 0.13 μm SiGe BiCMOS process. In addition, a high-temperature test of the MIL-STD-331C standard was conducted on a manufactured 94 GHz SiGe PLL chip mounted on a test board. As a result of the test, the chip total current change before and after the high-temperature test was 4.7 %, and the phase noise changes of both 94 GHz VCO and PLL were 2.3 dB. These results confirm that, even after the high-temperature test, the flattening of the low-frequency noise was well maintained because the VCO noise was filtered by the PLL. [ABSTRACT FROM AUTHOR]

In this paper, we present a fully integrated circuit without inductance implementing Chua’s chaotic system. The circuit described in this study utilizes the SMIC 180 nm CMOS process and incorporates a multi-path voltage-controlled oscillator (VCO). The integral-differential nonlinear resistance is utilized as a variable impedance component in the circuit, constructed using discrete devices from a microelectronics standpoint. Meanwhile, the utilization of a multi-path voltage-controlled oscillator ensures the provision of an adequate oscillation frequency and a stable waveform for the chaotic circuit. The analysis focuses on the intricate and dynamic behaviors exhibited by the chaotic microelectronic circuit. The experimental findings indicate that the oscillation frequency of the VCO can be adjusted within a range of 198 MHz to 320 MHz by manipulating the applied voltage from 0 V to 1.8 V. The circuit operates within a 1.8 V environment, and exhibits power consumption, gain–bandwidth product (GBW), area, and Lyapunov exponent values of 1.0782 mW, 4.43 GHz, 0.0165 mm2, and 0.6435∼1.0012, respectively. The aforementioned circuit design demonstrates the ability to generate chaotic behavior while also possessing the benefits of low power consumption, high frequency, and a compact size.

This paper presents a Q-band image-rejection receiver using a 65 nm CMOS technology. For a high image-rejection ratio (IMRR), the Q-band receiver employs the Hartley architecture which consists of a Q-band low-noise amplifier, two down-conversion mixers, a 90° hybrid coupler, and two IF baluns. In addition, a Q-band fundamental voltage-controlled oscillator (VCO) and a frequency divider chain divided by 256 are integrated into the receiver for LO. A charge injection technique is employed in the mixers to reduce the DC power while maintaining a high conversion gain and linearity. The VCO adopts a cross-coupled topology to secure stable oscillation with high output power in the Q-band. The frequency divider chain is composed of an injection-locked frequency divider (ILFD) and a multi-stage current-mode logic (CML) divider to achieve a high division ratio of 256, which facilitates the LO signal locking to an external phase-locked loop. An inductive peaking is employed in the ILFD to widen the locking range. The Q-band image-rejection receiver exhibits a peak conversion gain of 16.4 dB at 43 GHz. The IMRR is no less than 35.6 dBc at the IF frequencies from 1.5 to 5 GHz. [ABSTRACT FROM AUTHOR]

Low-phase noise and wideband phased-locked loops (PLLs) are crucial for high-data rate communication and imaging systems. Sub-millimeter-wave (sub-mm-wave) PLLs typically exhibit poor performance in terms of noise and bandwidth due to higher device parasitic capacitances, among other reasons. In this regard, a low-phase-noise, wideband, integer-N, type-II phase-locked loop was implemented in the 22 nm FD-SOI CMOS process. The proposed wideband linear differential tuning I/Q voltage-controlled oscillator (VCO) achieves an overall frequency range of 157.5–167.5 GHz with 8 GHz linear tuning and a phase noise of −113 dBc/Hz @ 100 KHz. Moreover, the fabricated PLL produces a phase noise less than −103 dBc/Hz @ 1 KHz and −128 dBc/Hz @ 100 KHz, corresponding to the lowest phase noise generated by a sub-millimeter-wave PLL to date. The measured RF output saturated power and DC power consumption of the PLL are 2 dBm and 120.75 mW, respectively, whereas the fabricated chip comprising a power amplifier and an integrated antenna occupies an area of 1.25 × 0.9 mm2. [ABSTRACT FROM AUTHOR]

This paper presents a K-band CMOS cross-coupled pair voltage-controlled oscillator (VCO) that utilizes the varactor-only capacitor network. The proposed circuit features low parasitics and a compact capacitor network, such that the varactor in the analog tuning path directly affects the oscillation frequency with a large gain of the VCO, and the varactor in the digital tuning path results in minimal noise sources, thus achieving low phase noise for the automotive FMCW radar application. This VCO was designed using TSMC 65 nm technology, and the post-layout simulation results show a stable oscillation across 18–19.2 GHz, a minimum phase noise of −105.9 and −128 dBc/Hz at 1- and 10-MHz offset frequencies while dissipating 21 mW of power from a 1 V supply. Furthermore, no notable variations in phase noise are observed across the oscillation frequency tuning range. It reveals a figure of merit (FOM) of −178.3 dBc/Hz while using a varactor-only capacitor array and occupying a small chip area. [ABSTRACT FROM AUTHOR]

A voltage-controlled oscillator (VCO) is one of the key modules of the phase-locked loop (PLL) microsystem, and it is easy to bombard using high-energy particles in a radiation environment, resulting in the single-event effect. In order to improve the anti-radiation ability of the PLL microsystems used in the aerospace environment, a new voltage-controlled oscillator hardened circuit is proposed in this work. The circuit consists of delay cells with an unbiased differential series voltage switch logic structure with a tail current transistor. By reducing sensitive nodes and using the positive feedback of the loop, the recovery process of the VCO circuit to the single-event transient (SET) is reduced and accelerated, so as to reduce the sensitivity of the circuit to the single-event effect. The simulation results based on the SMIC 130 nm complementary metal–oxide–semiconductor (CMOS) process show that the maximum phase shift difference of the PLL with the hardened VCO is reduced by 53.5%, which shows that the hardened VCO structure can reduce the sensitivity of the PLL to the SET and improve the reliability of the PLL in the radiation environment. [ABSTRACT FROM AUTHOR]

This work presents a complementary PMOS NMOS voltage-controlled power oscillator (VCO) based on a high quality (Q) factor off-chip inductor in 130 nm CMOS process. The proposed VCO achieves a frequency tuning range of 166% from 393 MHz to 4.17 GHz and this wide tuning range is divided into six bands where each band is also sub-divided into three bands using a single switching voltage. The proposed design takes into consideration the effect of the bond wire that is used to connect the off-chip inductor with the VCO core moreover, the measured SNP files of the off-chip inductors are utilized to ensure accurate results. This technique improves the figure of merit (FoM) by 4–25 dB compared to the conventional inductor VCO. Using six different values of the off-chip inductors, the proposed VCO works in six bands with a tuning range of 166%, and a minimum phase noise of − 127 dBc/Hz @ 1 MHz offset frequency 2.2 GHz carrier. Furthermore, the proposed VCO draws 1.37 mA from 1.1 V supply voltage and has a minimum achieved Figure-of-Merit (FOM) equal to -193 dBc/Hz with a maximum output power of 4.25 dBm. The VCO core area equals 0.07 mm 2 , while the total chip area including RF pads and output buffers is 0.437 mm 2 . [ABSTRACT FROM AUTHOR]

The current trend of increasing the complexity of hardware accelerators to improve their functionality is highlighting the problem of sharing a high-frequency clock signal for all integrated modules. As the clock itself is becoming the main limitation to the performance of accelerators, in this manuscript, we present the design of an asymmetric Ring Oscillator-Voltage-Controlled Oscillator (RO-VCO) based on the Current Mode Logic architecture. The RO-VCO was designed on commercial-grade 65 nm CMOS technology, and it is capable of driving large capacitance loads, avoiding the need for additional buffers for clock-trees, reducing the silicon area and power consumption. The proposed RO-VCO is composed of three closed-loop differential and asymmetrical stages, and it is able to tune the working frequency in the range from 4.72 GHz to 6.12 GHz. The phase noise and a figure of merit of −103.2 dBc/Hz and −186 dBc/Hz were obtained at 1 MHz offset from the 5.5 GHz carrier. In this article, the analytical model, full custom schematic, and layout of the proposed RO-VCO are presented and discussed in detail together with the experimental electrical and thermal characterization of the fabricated device. [ABSTRACT FROM AUTHOR]

This brief proposes a digital LDO (Low DropOut regulator) with a built-in non-linear VCO (Voltage Controlled Oscillator) to achieve both the fast transient response and low power operation. This on-chip VCO generates a clock signal whose frequency is a non-linear symmetric function of the output voltage error. Here, we propose a design technique to realize the symmetric frequency generation with low power consumption. We demonstrate a design example of LDO using our proposed technique in a commercial 65 nm low-power CMOS process. We evaluate the LDO using transistor-level simulation using HSPICE. It achieves 0.03- $11 ~\mu \text{A}$ of quiescent current with an input voltage range of 0.6-1.2 V and an average current efficiency of 99.68% across $50\times $ load range. [ABSTRACT FROM AUTHOR]

In this paper, a fully integrated memristive Chua's chaotic circuit based on the voltage-controlled oscillator is proposed. The memristor replaces the nonlinear diode, and the VCO (voltage-controlled oscillator) replaces the LC oscillator, eliminating the need for diodes, resistors, capacitors, and other complex circuit structures. The proposed chaotic circuit occupies a small chip area, only 0.0045 mm 2 , and achieves low power consumption of 2.8267 mW. The chaotic circuit is fabricated using the SMIC 180 nm CMOS process. The simulation results demonstrate that the VCO circuit can generate a frequency output ranging from 358 MHz to 1.1 GHz by varying Vc from 0 V to 2.8 V, with a power supply of 3.3 V. The value range of the Lyapunov index is 1.015 ∼ 1.03. The circuit offers advantages such as a stable power supply, low power consumption, and a small chip area. • The fully Integrated circuit memristive of a new Chua's system is designed. • The circuit does not have an inductance but forced by the voltage controlled oscillator. • Chaos is obtained in a chip with small area and low power consumption. [ABSTRACT FROM AUTHOR]

We describe in this paper an improved ring voltage-controlled oscillator (VCO) showing a reduced phase noise while allowing an extended frequency tuning range. The phase noise improvement is obtained through the minimized contribution of tuning line noise while maintaining a rail-to-rail swing. The proposed VCO features a linear tuning characteristic yielding a constant gain over a wide range of operating frequencies. An analytical model is extracted resulting in closed-form expressions for the VCO phase noise. Employing the analytical expressions, the contributed noise and phase noise limitations are fully addressed, and all the effective factors are investigated. The VCO prototype was fabricated in a 0.35 $\mu \text{m}$ CMOS process. It consumes 0.903 mW from a 3.3 V supply when running at its maximum oscillation frequency of 9.37 MHz. The measured VCO phase noise is −147.57 dBc/Hz at 1 MHz offset from the 9.37 MHz oscillation frequency, and the circuit occupies a silicon area of 0.005 mm2. A state-variable MATLAB® model of a time-based sensor interface has been developed including the impact of phase noise nonideality. The system-level simulations demonstrate that the PLL-based sensor interface exploiting the proposed VCO characteristics can achieve a 88.43 dB signal-to-noise ratio over a 1-kHz bandwidth.

A broadband 77/79 GHz transmitter (TX) front-end for automotive long range radar (LRR) and short range radar (SRR) applications is presented in this paper. To achieve the best system performance one new TX architecture with two specifically designed voltage controlled oscillators (VCOs) is implemented in a 28 nm CMOS technology. Furthermore, the degradation of the VCO phase noise due to the TX integration is analyzed in detail and solutions to minimize the impacts are proposed and verified. Experimental results of a 20 GHz push-push VCO1 measured at the 77 GHz TX output show a continuous tuning range of 4.75 GHz, a coarse tuning range of 3.2 GHz and an average phase noise of −100 dBc/Hz @ 1 MHz, while a 26 GHz VCO2 with third harmonic signal extraction achieves a continuous and coarse tuning range of 7.5 GHz and 4.2 GHz with an average phase noise of −96 dBc/Hz @ 1 MHz at 79 GHz TX output. Moreover, a record pushing performance of $\rm { 100 MHz/V at 77/79 GHz TX output has been achieved according to the authors’ best knowledge. The whole TX chip consumes about 860 mW from a single 2.1 V supply while providing more than 16 dBm output power over the whole frequency band.

This paper reports an approach to designing compact high-efficiency millimeter-wave fundamental oscillators operating above the fmax/2 of the active device. The approach takes full consideration of the nonlinearity of the active device and the finite quality factor of the passive devices to provide an accurate and optimal oscillator design in terms of the output power and efficiency. The 213-GHz single-ended and differential fundamental oscillators in 65-nm CMOS technology are presented to demonstrate the effectiveness of the proposed method. Using a compact capacitive transformer design, the single-ended oscillator achieves 0.79-mW output power per transistor (16μm ) at 1-V supply and a peak dc-to-RF efficiency of 8.02% (VDD=0.80 V) within a core area of 0.0101 mm2, and a measured phase noise of -93.4 dBc/Hz at 1-MHz offset. The differential oscillator exhibits approximately the same performance. A 213-GHz fundamental voltage-controlled oscillator (VCO) with a bulk tuning method is also demonstrated in this paper. The measured peak efficiency of the VCO is 6.02% with a tuning range of 2.3% at 0.6-V supply.

In this letter, a parallel‐feedback dual‐band voltage‐controlled oscillator (DVCO) with low phase noise and a wide tuning range is proposed. The DVCO is composed of two tunable filters associated with four switches and an active device. By controlling four switches, the oscillation frequency can be switched and oscillated in one of two bands. The employed tunable filter with maintained passband shape and wide frequency tuning range (FTR) is beneficial to designing wideband DVCO with low phase noise. Owing to the maintained frequency response, the sharp phase variation and high in‐band group delay can be maintained during the filter tuning process, which can enhance the phase noise improvement. Moreover, the sharp phase variation can realize the phase compensation in a wide FTR when tuning the DVCO. To develop a DVCO with a simple circuit scheme, the two‐pole tunable filters with two different FTRs are designed. For verification, the proposed DVCO is designed, manufactured, and measured. The measurement results show that each band of the DVCO has a tuning range of 1.97–2.58 GHz (27.8%) and 2.934–3.468 GHz (16.7%), respectively. For the lower band, the phase noise at 100 kHz and 1 MHz frequency offset is better than −99.2 and −126.4 dBc/Hz, respectively. While for the upper band, the phase noise at 100 kHz and 1 MHz frequency offset is better than −101.2 and −127.4 dBc/Hz, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a 9.4 ~ 20.6 GHz low‐noise phase‐locked loop (PLL) in 0.13‐μm SiGe BiCMOS technology for 5G applications. To achieve the wideband and phase noise performance simultaneously, a four‐core Colpitts voltage‐controlled oscillato array with 2‐bit switched capacitors and 2‐bit‐control bias currents is used in the PLL loop. In order to optimize the programmable frequency divider accurately, the injection‐locking behavior model of the dual‐mode prescaler is quantitatively analyzed, which is proved to be effective through the tape‐out. The fabricated proposed PLL achieves the average phase noise of −100.5 dBc/Hz at 1‐MHz offset, wideband locking range of 74.7% and the high FOMT of 183.3 dBc/Hz. It occupies an area of 8.4 mm2, and its maximum power consumption is 319.7 mW. [ABSTRACT FROM AUTHOR]

In this article, low phase noise microwave oscillators based on elliptic resonators have been reported. Eight different designs of elliptic oscillators in various frequency bands such as L and X have been compared with each other and the results of them have been presented. The parameters such as active devise, elliptic resonator, oscillation frequency, output power, phase noise, and figure-of-merit are considered. In the end, the low phase noise X-band oscillator based on elliptic filter and branchline coupler is having better results of phase noise among the other elliptic microwave oscillators. [ABSTRACT FROM AUTHOR]

A set of monolithic integrated circuits (MICs) in the 22–25 GHz range based on gallium nitride nanoheterostructures on sapphire substrates is designed, produced, and studied at Mokerov Institute of Ultra High Frequency Semiconductor Electronics (IUHFSE), Russian Academy of Sciences. Models of transceiver paths (TPs)of short-range radar stations (up to 10 m) and communication channels are assembled based on the manufactured MICs. The results of measuring the microwave characteristics of models of the receiving-transmitting paths are presented. The possibility of using the developed MICs in communication channels with digital and analog modulation is established. [ABSTRACT FROM AUTHOR]

Low-phase noise and wideband phased-locked loops (PLLs) are crucial for high-data rate communication and imaging systems. Sub-millimeter-wave (sub-mm-wave) PLLs typically exhibit poor performance in terms of noise and bandwidth due to higher device parasitic capacitances, among other reasons. In this regard, a low-phase-noise, wideband, integer-N, type-II phase-locked loop was implemented in the 22 nm FD-SOI CMOS process. The proposed wideband linear differential tuning I/Q voltage-controlled oscillator (VCO) achieves an overall frequency range of 157.5–167.5 GHz with 8 GHz linear tuning and a phase noise of −113 dBc/Hz @ 100 KHz. Moreover, the fabricated PLL produces a phase noise less than −103 dBc/Hz @ 1 KHz and −128 dBc/Hz @ 100 KHz, corresponding to the lowest phase noise generated by a sub-millimeter-wave PLL to date. The measured RF output saturated power and DC power consumption of the PLL are 2 dBm and 120.75 mW, respectively, whereas the fabricated chip comprising a power amplifier and an integrated antenna occupies an area of 1.25 × 0.9 mm2.

A voltage-controlled oscillator (VCO) is one of the key modules of the phase-locked loop (PLL) microsystem, and it is easy to bombard using high-energy particles in a radiation environment, resulting in the single-event effect. In order to improve the anti-radiation ability of the PLL microsystems used in the aerospace environment, a new voltage-controlled oscillator hardened circuit is proposed in this work. The circuit consists of delay cells with an unbiased differential series voltage switch logic structure with a tail current transistor. By reducing sensitive nodes and using the positive feedback of the loop, the recovery process of the VCO circuit to the single-event transient (SET) is reduced and accelerated, so as to reduce the sensitivity of the circuit to the single-event effect. The simulation results based on the SMIC 130 nm complementary metal–oxide–semiconductor (CMOS) process show that the maximum phase shift difference of the PLL with the hardened VCO is reduced by 53.5%, which shows that the hardened VCO structure can reduce the sensitivity of the PLL to the SET and improve the reliability of the PLL in the radiation environment.

Internet-of-Things (IoT) devices are compact and low power. A voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) benefits from scaled CMOS transistors in representing analog signals in the time domain and therefore meets those demands. However, we find the potential drawback of VCO-based ADCs for the electromagnetic susceptibility (EMS) to RF disturbances that are essentially present in an IoT environment. It is exhibited that the single and even differential designs of VCO-based ADC suffer from the EMS by RF disturbance, which behaves differently from the known common-mode noise rejection. A 28 nm CMOS 11-bit VCO-ADC prototype exhibits sensitivity against RF signals in the widely used 2.4 GHz frequency band. [ABSTRACT FROM AUTHOR]

Five new structures of linear fractional-order voltage-controlled oscillators (FO-VCOs) utilizing only Multiplication-Mode Current Conveyors (MMCCs) and canonic numbers of all grounded passive elements (AGPEs) are presented in this paper. The derivation procedure has been detailed along with the relevant nonideal analysis. The work also presents three fractional-order cases of the oscillators and brings out the effects of port nonidealities and port parasitics on the performance of presented FO-VCOs. The workability of all the five new FO-VCOs has been validated on PSPICE utilizing library files of AD844 and AD835 for realizing MMCC employed in the FO-VCOs. For all the three special fractional-order cases, the simulation results have been tabulated along with relevant MATLAB plots that facilitate comparison among oscillation parameters and the fractional order. The harmonic distortion figures have been found out by Fourier analysis. Experimental workability of a VCO, employing MMCC realized with AD835 and AD844 of our investigation is included to support hardware functionality. [ABSTRACT FROM AUTHOR]

A sub-sampling phase-locked loop (SSPLL) with a sub-sampling delay-locked loop is presented to extend the loop bandwidth and achieve the low jitter. A falling-edge tuning loop is added to align the falling edge of the reference clock with the rising one of the output clock. The proposed SSPLL is realized in a $0.18 {\mu }\text{m}$ CMOS process and its active area is 0.185mm2. At the output frequency of 2.2GHz, the proposed SSPLL achieves an in-band phase noise of −111.83dBc/Hz and −116.41dBc/Hz at 100kHz and 4MHz offset frequency respectively with a division ratio of 44. Its root-mean-square jitter integrated from 10kHz to 100MHz is 655fs. The measured reference spur is −50.3dBc. [ABSTRACT FROM AUTHOR]

Conventional von Neumann architectures cannot successfully meet the demands of emerging computation and data-intensive applications. These shortcomings can be improved by embracing new architectural paradigms using emerging technologies. In particular, Computation-In-Memory (CiM) using emerging technologies such as Resistive Random Access Memory (ReRAM) is a promising approach to meet the computational demands of data-intensive applications such as neural networks and database queries. In CiM, computation is done in an analog manner; digitization of the results is costly in several aspects, such as area, energy, and performance, which hinders the potential of CiM. In this article, we propose an efficient Voltage-Controlled-Oscillator (VCO)-based analog-to-digital converter (ADC) design to improve the performance and energy efficiency of the CiM architecture. Due to its efficiency, the proposed ADC can be assigned in a per-column manner instead of sharing one ADC among multiple columns. This will boost the parallel execution and overall efficiency of the CiM crossbar array. The proposed ADC is evaluated using a Multiplication and Accumulation (MAC) operation implemented in ReRAM-based CiM crossbar arrays. Simulations results show that our proposed ADC can distinguish up to 32 levels within 10 ns while consuming less than 5.2 pJ of energy. In addition, our proposed ADC can tolerate ≈30% variability with a negligible impact on the performance of the ADC. [ABSTRACT FROM AUTHOR]

In this paper, physical implementations and measurement results are presented for several Voltage Controlled Oscillators that were designed using a fully-automated, layout- and variability-aware optimization-based methodology. The methodology uses a highly accurate model, based on machine-learning techniques, to characterize inductors, and a multi-objective optimization algorithm to achieve a Pareto-optimal front containing optimal circuit designs offering different performance trade-offs. The final outcome of the proposed methodology is a set of design solutions (with their GDSII description available and ready-to-fabricate) that need no further designer intervention. Two key elements of the proposed methodology are the use of an optimization algorithm linked to an off-the-shelf simulator and an inductor model that yield EM-like accuracy but with much shorter evaluation times. Furthermore, the methodology guarantees the same high level of robustness against layout parasitics and variability that an expert designer would achieve with the verification tools at his/her disposal. The methodology is technology-independent and can be used for the design of radio frequency circuits. The results are validated with experimental measurements on a physical prototype.

A radar transceiver with two transmitters (TXs) and two receivers (RXs) is reported in 22 nm fully depleted silicon-on-insulator (FDSOI) CMOS. It includes a novel 200 MHz bandwidth 80 GHz phase-locked loop (PLL) based on a single-sideband (SSB) upconverter and an 11 GHz bandwidth phase-frequency detector to achieve >8 GHz locking range with record phase noise of −97, −103, and −113 dBc/Hz at 100 kHz, 1 MHz, and 10 MHz offset, respectively, and rms jitter < 40 fs. Stepped-frequency chirps with orthogonal frequency-division multiplexing (OFDM) modulation covering the 152–160 GHz range were demonstrated in a through-the-air loopback link along with a record settling time < 30 ns, limited by the test equipment. The RXs have an IIP3 of −8 dBm, SSB noise figure between 7.5 and 10 dB and a conversion gain of 15 dB, controllable from the LNA back gate over a range of 12 dB. The OP1 dB and $P_{\mathrm {SAT}}$ of the power amplifier (PA) in each TX are 5 and 9 dBm, respectively. The IQ amplitude mismatch and phase error of each RX are < 0.5 dB and 1°, respectively, while the $P_{\mathbf {out}}$ mismatch between the TXs is < 1 dB. The sensor consumes 1.13 W, with 300 mW by the PLL, 275 mW by the 160 GHz local oscillator (LO)-tree, 190 mW by each TX, and 87.5 mW by each RX. [ABSTRACT FROM AUTHOR]

Negative differential resistance (NDR) is inherent in many electronic devices, in which, over a specific voltage range, the current decreases with increasing voltage. Semiconductor structures with NDR have several unique properties that stimulate the search for technological and circuitry solutions in developing new semiconductor devices and circuits experiencing NDR features. This study considers two-terminal NDR electronic circuits based on multiple-output current mirrors, such as cascode, Wilson, and improved Wilson, combined with a field-effect transistor. The undoubted advantages of the proposed electronic circuits are the linearity of the current-voltage characteristics in the NDR region and the ability to regulate the value of negative resistance by changing the number of mirrored current sources. We derive equations for each proposed circuit to calculate the NDR region's total current and differential resistance. We consider applications of NDR circuits for designing microwave single frequency oscillators and voltage-controlled oscillators. The problem of choosing the optimal oscillator topology is examined. We show that the designed oscillators based on NDR circuits with Wilson and improved Wilson multiple-output current mirrors have high efficiency and extremely low phase noise. For a single frequency oscillator consuming 33.9 mW, the phase noise is −154.6 dBc/Hz at a 100 kHz offset from a 1.310 GHz carrier. The resulting figure of merit is −221.6 dBc/Hz. The implemented oscillator prototype confirms the theoretical achievements. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model of a closed-loop frequency-locked loop (FLL) based on a two-stage voltage-controlled oscillator (VCO) is proposed. Switch capacitor technology is used to accelerate the conversion speed of the frequency-to-voltage converter for reducing the locking time. The VCO is reduced to the minimum two-stage delay ring structure for outputting high-frequency signals with less variation caused by process, voltage, and temperature drift. Based on the strategy that focuses on the optimization of the loop bandwidth, a low jitter GHz clock with a wide swing and a strong capacitive load driving ability is realized. The proposed FLL is implemented in TSMC 0.35 μm 3.3 V CMOS process. From the experimental results, the output frequency is ranged from 750 MHz to 1.27 GHz, and the RMS jitter of the output clock is less than 36 ps under 1.039 GHz. The generated low-jitter clock is suitable for GHz gating applications in single-photon detection. [ABSTRACT FROM AUTHOR]