Search

A functionally complete Boolean operator is sufficient for computational circuits of arbitrary complexity. We connected YES (buffer) with NOT (inverter) and two NOT four-way junction (4J) DNA gates to obtain IMPLY and NAND Boolean functions, respectively, each of which represents a functionally complete gate. The results show a technological path towards creating a DNA computational circuit of arbitrary complexity based on singleton NOT or a combination of NOT and YES gates, which is not possible in electronic computers. We, therefore, concluded that DNA-based circuits and molecular computation may offer opportunities unforeseen in electronics. [ABSTRACT FROM AUTHOR]

A functionally complete Boolean operator is sufficient for computational circuits of arbitrary complexity. We connected YES (buffer) with NOT (inverter) and two NOT four-way junction (4J) DNA gates to obtain IMPLY and NAND Boolean functions, respectively, each of which represents a functionally complete gate. The results show a technological path towards creating a DNA computational circuit of arbitrary complexity based on singleton NOT or a combination of NOT and YES gates, which is not possible in electronic computers. We, therefore, concluded that DNA-based circuits and molecular computation may offer opportunities unforeseen in electronics.

All-optical devices have demonstrated a broad range of applications in the communication field. These devices serve as the fundamental building blocks of sophisticated integrated circuits. By integrating these devices into fields such as signal processing, chip design, and network computations, it is possible to achieve a much more efficient device. This paper describes the design of all-optical logic gates such as NAND, NOR, and XNOR using a plasmonic-based Y-shaped power combiner. The combiner employs the concept of linear interference to generate the desired logic gates. The work is simulated and analysed using MATLAB and finite-difference time domain method. The current work is framed within a 60 µm2 area which is less than the size of the existing structures. The parameters characterising insertion loss, transmission efficiency, and extinction ratio are calculated and compared to those of a variety of other designs. [ABSTRACT FROM AUTHOR]

In the field of hardware security, the physical unclonable function (PUF) is known as a significant advancement for its unique and unclonable outputs, serving as a 'digital fingerprint' for electronic devices. This distinctiveness is crucial for high-security tasks such as device authentication and cryptographic key generation. The PUF's input-output combinations, known as challenge-response pairs (CRPs), are essential to its functionality. Although the Ring Oscillator (RO) PUF is notable for its security advantages and straightforward implementation, it's considered a 'weak' PUF due to its limited CRPs, highlighting a demand for more robust and secure PUF designs. This paper introduces a novel configurable inversion unit (CIU), integrating two universal logic gates, NAND and NOR, to be utilized in building various configurable ring oscillator (CRO) PUF models. Using the newly proposed CIU, we introduce two distinct CRO-PUF configurations. The first one includes 16-ring oscillators, while the second has 8-ring oscillators. A modified version of this CIU is introduced to increase the size of CRPs that a PUF can handle. A comprehensive assessment process of these configurations underscores the superior performance of these models across various parameters, including reliability, distinctiveness, balance, bit-aliasing, and randomness. • MUX-based CRO PUFs mainly utilize inverters and XOR gates. • XOR gates in CRO-PUFs, with/without MUXs, boost RO-PUF efficacy. • Few CRO-PUF designs use NAND/NOR universal gates. • More ring oscillators in PUFs link to better security. [ABSTRACT FROM AUTHOR]

In this study, the design of digital logic gates and circuits in ternary logic is presented. The ternary logic is observed to be a better alternative to the traditional binary logic because it offers faster computations, smaller chip area, and lesser interconnects. Thus, it allows designing the low‐complex, high‐speed, and energy‐efficient circuits in future digital design. A novel technique is proposed to design the ternary logic gates using multi‐threshold graphene nanoribbon field‐effect transistors (GNRFETs). The GNRFET threshold voltage is controlled by the width of the graphene nanoribbon, which is defined by the dimer lines number. Three different inverters are designed namely standard, positive, and negative inverters along with the basic and universal logic gates. Additionally, the ternary half adder and full adder are proposed that further helps to design the complex arithmetic circuits. All the proposed ternary logic circuits have been extensively simulated in SPICE for functional verification and performance analysis. The performance of the proposed ternary logic circuits is compared with the existing designs presented in the literature. The comparison results show that the propagation delay and circuit area of GNRFET‐based circuits are reduced with an average of 41.3 and 64%, respectively, than the existing ternary circuits. [ABSTRACT FROM AUTHOR]

Abstract Electronics on paper enable some specific applications out of conventional ones which require innovative approaches and concepts on the design of devices and systems. Within this context, this work demonstrates that a unique set of characteristics can be combined in planar dual‐gate oxide–based field effect transistors with a back floating electrode using paper simultaneously as substrate and dielectric. The working principle of these transistors relies on the formation of electric double layers at the semiconductor/paper and paper/back floating electrode interfaces (associated to ions displacement within the paper) that can be disturbed by a voltage applied at a secondary gate, by the back floating potential or by the combination of both. This feature allows for the control of the on‐voltage of the transistors, from depletion to enhancement mode, for instance. Moreover, this specific characteristic allows the implementation of universal logic gates (NAND and NOR) using only one transistor, by setting the proper combination of the voltage level applied at each gate. This way a simple and universal device architecture can be envisaged towards the simplification of the production of low power electronic systems on paper.

Electronics on paper enable some specific applications out of conventional ones which require innovative approaches and concepts on the design of devices and systems. Within this context, this work demonstrates that a unique set of characteristics can be combined in planar dual-gate oxide-based field effect transistors with a back floating electrode using paper simultaneously as substrate and dielectric. The working principle of these transistors relies on the formation of electric double layers at the semiconductor/paper and paper/back floating electrode interfaces (associated to ions displacement within the paper) that can be disturbed by a voltage applied at a secondary gate, by the back floating potential or by the combination of both. This feature allows for the control of the on-voltage of the transistors, from depletion to enhancement mode, for instance. Moreover, this specific characteristic allows the implementation of universal logic gates (NAND and NOR) using only one transistor, by setting the proper combination of the voltage level applied at each gate. This way a simple and universal device architecture can be envisaged towards the simplification of the production of low power electronic systems on paper. [ABSTRACT FROM AUTHOR]

We show two universal, Boolean, deterministic logic schemes based on binary noise timefunctions that can be realized without time-averaging units. The first scheme is based on a new bipolar random telegraph wave scheme and the second one makes use of the recent noise-based logic which is conjectured to be the brain's method of logic operations [Phys. Lett. A373 (2009) 2338-2342]. Error propagation and error removal issues are also addressed. [ABSTRACT FROM AUTHOR]

In this paper we have proposed a simplified design and visualization approach. It can be used to implement Boolean functions given in the form of minterms primarily using 2-input Universal NAND gates. Then it can be extended easily for NAND gates with any number of inputs. We name the novel approach μ-graph Method. This basically presents a compact data structure for representing circuits with 2-input NAND gates. One can use this approach to generate 2-input NAND-based digital circuits from any pre-optimized logic function, without hard brainstorming. Necessary supports behind the idea are also given along with. The circuit design will be done on the optimized form of the given Boolean function, but the number of NAND gates, however, is not optimized in this design approach. [ABSTRACT FROM AUTHOR]

Proper control of the voltage applied at both gates of a planar dual‐gate field effect transistor (FET) using a cellulose matrix as the dielectric makes it possible to operate them either in depletion or enhancement mode. In article number 1800423, Luís Pereira, Elvira Fortunato, Rodrigo Martins, and co‐workers demonstrate the implementation of universal logic gates (NAND and NOR) using only one transistor, by setting the appropriate combination of the voltage level applied at each gate. [ABSTRACT FROM AUTHOR]