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Switched capacitor multilevel inverters (SCMLIs) became a popular DC-to-AC converter due to their unique features like self-capacitor voltage balancing and self-output voltage boosting abilities over conventional multilevel inverters in recent years. However, recently developed SCMLIs suffer from higher component counts, lower voltage boosting factors, higher total standing voltage, and the requirement of isolated DC sources for generating high-quality output voltage level waveform. These drawbacks make the inverter costly, complex, and bulky. To address these drawbacks of SCMLIs, a novel SCMLI is proposed in this paper. The proposed SCMLI can realise 17 output voltage levels with a higher boosting factor. In addition, the proposed SCMLI uses lower switches, driver circuits, capacitors, and diodes than similar SCMLIs. The proposed SCMLI also offers a cheaper cost function per output voltage level per boosting factor compared to others. A thorough description of the proposed inverter's operating principle, voltage stress analysis, and capacitor selection procedure have been discussed. The proposed inverter's cascaded form has been constructed and analysed for various DC source configurations. An extensive simulation study of 17-level SCMLI in MATLAB/Simulink platform and an experimental investigation on a 17-level laboratory prototype validate the proposed SCMLI's merits and effectiveness. [ABSTRACT FROM AUTHOR]

This paper proposes a systematic approach to enhance the performance of a 21‐level asymmetrical multilevel inverter (MLI) with less power electronics switches and DC voltage sources. In the first step (Configuration 1), the voltage level is improved at the cost of DC‐link voltage utilization. In the second step (Configuration 2), the ratio of the DC‐link voltages is modified to improve the utilization of DC‐link voltage, with an insignificant reduction of voltage levels as compared to Configuration 1. Finally, another modification of the MLI configuration is proposed (Configuration 3), by incorporating an H‐bridge in place of a T‐type module for further improvement of DC source utilization and increasing the number of voltage levels. Thus, Configuration 3 improves the inverter's total standing voltage (TSV) and efficiency. To reduce the number of DC sources, the output voltage levels are obtained in Configuration 3 by adding and subtracting the input DC sources. Moreover, conducting switches are reduced to minimize conduction loss and maximize efficiency. The DS1103‐based digital controller is used to verify the performance of the proposed configurations, which are compared with the literature‐based MLI models. [ABSTRACT FROM AUTHOR]

This article describes a 17-level switched-capacitor-based eight-times-boosting gain inverter. The inverter is made up of a DC power source, thirteen switches, three diodes, and three capacitors. The inverter produces seventeen steps during each cycle and crosses the zero line two times in one complete cycle. The proposed inverter has its polarity change mechanism; it is not necessary to use an H-bridge. Three self-balancing capacitors make up this construction. The capacitors automatically balance voltage by connecting in series/parallel to the input voltage source. Logic gates can generate gate pulses with the phase disposition pulse-width modulation technique, which helps to preserve capacitor voltage balance at the same time. The proposed structure was compared to recent papers, analyzing factors including voltage gain, DC sources, semiconductor devices, cost function, and TSV. The proposed configuration offers cost effectiveness and fewer semiconductor devices for providing a 17-level output with sufficient voltage gain. Also, to reduce the capacitor inrush current, soft charging is used. Additionally, the proposed structure's power losses were examined, confirming its efficiency. Finally, an experimental prototype was tested to analyze and validate the suggested structure's performance under various situations. Results show the proposed structure performs well under steady and dynamic situations. [ABSTRACT FROM AUTHOR]

Summary: Multilevel inverters (MLIs) are widely used in various sectors of power electronics. Some major benefits of using MLI are the high‐quality voltage output, harmonic reduction, and efficiency. However, MLIs also bear a range of disadvantages including an excessive number of components, high total standing voltage (TSV), and complicated control scheme. Thus, a novel cross‐switched neutral point clamped (CSNPC) nine‐level inverter is proposed. Many of the suggested MLIs use a large number of DC supplies and additional switches that are not fully utilized and generate high power loss. However, the proposed MLI topology has a smaller number of power electronic switches and DC supplies, leading to higher energy efficiency. Moreover, a simplified high frequency modulation technique, named hysteresis‐band‐based discontinuous pulse width modulation (DPWM) is devised to control the proposed MLI. This modulation scheme has effectively minimized capacitor voltage imbalance. Furthermore, the designed structure is extendable to a modular MLI, without any additional H‐bridge circuit. To verify its benefits over other recent similar types of MLIs, a thorough comparison is presented for the number of components and power losses. The proposed MLI has showed 95.54% efficiency, and the modular CSNPC can achieve a total harmonic distortion (THD) of 6.43%. [ABSTRACT FROM AUTHOR]

A novel single-phase 29-level asymmetrical switched-diode multilevel inverter (MLI) topology is presented in this paper with a reduced number of components. The developed topology can able to generate a maximum of 29-levels of output voltage using unequal DC sources. The basic 15-level MLI is developed and then further developed to 29-levels. The proposed topology reduces the circuit components, size and cost of the system. Apart from the several benefits of MLIs, reliability and accuracy plays a vital role because of the existence of more components count to reduce THD value. This can be considered as a major challenge employed to boost reliability without altering the best THD value. Various parameters are realized for both basic 15-level and the proposed 29-level switched-diode MLIs like total standing voltage (TSV), power loss, efficiency and cost function (CF). As the proposed MLI is undergone in dynamic load variations, the experimental results show the variations from R-load to L-load and L-load to R-load and it is found that the inverter is found to be stable throughout its operation. Experimental THD is represented, which is similar to the simulation THD which is under IEEE standards. TSV and cost factor of the proposed MLI is determined and is compared with several existing topologies and is observed to be cost-effective. A precise comparison is made on various parameters using graphical depiction.. The simulation for the proposed topology is done in MATLAB/Simulink and the experimental verification is done using the hardware prototype model under several conditions. [ABSTRACT FROM AUTHOR]

This article presents a novel multilevel inverter (MLI) based on a basic unit of switched capacitor structure(SCS). The proposed SCS produces a multi-step DC-boosted output voltage using a few devices. This basic SCS unit is then used to develop a cross-switched structure. A crossed-switch structure combines several basic units to develop a larger unit that can produce a greater step level of output for a better sinusoidal signal and makes the system self-polarity change. The proposed system is configured by combining two SCS units, which produce less total standing voltage (TSV) across switches than other earlier proposed systems and generate 17-level output voltage with a boosting of 4 times. A simple pulse width modulation system is created to control the gating switches using logic gates. This work introduces the working principle of the basic unit topology, determines the required capacitance, power loss calculation, and efficiency curve, and presents experimental results on a scaled-down laboratory prototype to confirm the feasibility of the proposed design. After comparing the suggested converter to other current topologies, a thorough analysis shows that it is superior.

This work introduces an 11-level switched-capacitor multilevel inverter (SCMLI) designed for solar photo-voltaic (PV) applications, capitalizing on the growing popularity of multilevel inverters due to their superior power quality. With a 1.67- times boosting capability, the proposed SCMLI employs 10 switches, 2 DC supplies, and 2 capacitors to achieve an 11-level output voltage waveform. The topology requires only seven driver circuits, incorporating 2 bidirectional switches and 3 complementary pairs of switches. The proposed inverter has intrinsic capacitor self-balancing features since the capacitors are connected across the DC voltage source at different times throughout a basic cycle to charge the capacitors at a level of input voltage. A thorough comparison between the topology and recently developed SCMLI's has been presented. The comparison demonstrates the effectiveness in terms of switches, capacitors, sources, efficiency, total standing voltage (TSV), and boosting capacity. To experimentally validate its performance, the suggested SCMLI undergoes testing using a frequency-based switching method. The topology exhibits low total harmonic distortion (THD) of 7.65% in its output voltage waveform and 0.89% in the output current waveform. [ABSTRACT FROM AUTHOR]

This article describes a 17-level switched-capacitor-based eight-times-boosting gain inverter. The inverter is made up of a DC power source, thirteen switches, three diodes, and three capacitors. The inverter produces seventeen steps during each cycle and crosses the zero line two times in one complete cycle. The proposed inverter has its polarity change mechanism; it is not necessary to use an H-bridge. Three self-balancing capacitors make up this construction. The capacitors automatically balance voltage by connecting in series/parallel to the input voltage source. Logic gates can generate gate pulses with the phase disposition pulse-width modulation technique, which helps to preserve capacitor voltage balance at the same time. The proposed structure was compared to recent papers, analyzing factors including voltage gain, DC sources, semiconductor devices, cost function, and TSV. The proposed configuration offers cost effectiveness and fewer semiconductor devices for providing a 17-level output with sufficient voltage gain. Also, to reduce the capacitor inrush current, soft charging is used. Additionally, the proposed structure’s power losses were examined, confirming its efficiency. Finally, an experimental prototype was tested to analyze and validate the suggested structure’s performance under various situations. Results show the proposed structure performs well under steady and dynamic situations.

This work introduces an 11-level switched-capacitor multilevel inverter (SCMLI) designed for solar photo-voltaic (PV) applications, capitalizing on the growing popularity of multilevel inverters due to their superior power quality. With a 1.67-times boosting capability, the proposed SCMLI employs 10 switches, 2 DC supplies, and 2 capacitors to achieve an 11-level output voltage waveform. The topology requires only seven driver circuits, incorporating 2 bidirectional switches and 3 complementary pairs of switches. The proposed inverter has intrinsic capacitor self-balancing features since the capacitors are connected across the DC voltage source at different times throughout a basic cycle to charge the capacitors at a level of input voltage. A thorough comparison between the topology and recently developed SCMLI’s has been presented. The comparison demonstrates the effectiveness in terms of switches, capacitors, sources, efficiency, total standing voltage (TSV), and boosting capacity. To experimentally validate its performance, the suggested SCMLI undergoes testing using a frequency-based switching method. The topology exhibits low total harmonic distortion (THD) of 7.65% in its output voltage waveform and 0.89% in the output current waveform.

Summary: Multilevel inverter is a practical power electronic design that has motivated a great deal of ever‐increasing interest. In this article, a new design of basic module‐based multilevel is proposed. The article conceptualized minimizing the number of power semiconductor devices, losses, and total blocking voltage and hence the cost. The proposed inverter structure consists of both a polarity generator and a level generator unit. To investigate the eminence of the proposed topology, an exhaustive comparative study with other existing topologies is presented. The proposed inverter can be utilized for both symmetrical and asymmetrical configurations. The extended cascaded structure of the proposed topology is discussed for generating a higher level of voltages and five algorithms for asymmetrical configuration are introduced to select input dc voltages. This article presents the operating principle, modulation strategy, total standing voltage calculation, cost function, and losses calculation. The efficacy of the proposed cascaded multilevel inverter has been substantiated experimentally. The proposed structure can be efficiently used in medium‐/high‐voltage applications like electrical drives as well as renewable energy resource‐based grid‐connected systems. [ABSTRACT FROM AUTHOR]

This paper proposes a step-up 3-Ф switched-capacitor multilevel inverter topology with minimal switch count and voltage stresses. The proposed topology is designed to provide five distinct output voltage levels from a single isolated dc source, making it suitable for medium and low-voltage applications. Each leg of the proposed topology contains four switches, one power diode, and a capacitor. The switching signals are also generated using a staircase universal modulation method. As a result, the proposed topology will operate at both low and high switching frequencies. To highlight the proposed topology's advantages, a comparison of three-phase topologies wasperformed in terms of the switching components, voltage stress, component count per level factor, and cost function withthe recent literature. The topology achieved an efficiency of about 96.7% with dynamic loading, and 75% of the switches experienced half of the peak output voltage (VDC), whereas the remaining switches experienced peak output voltage (2VDC) as voltage stress. The MATLAB/Simulink environment was used to simulate the proposed topology, and a laboratory prototype was also built to verify the inverter's theoretical justifications and real-time performance. [ABSTRACT FROM AUTHOR]

This multilevel inverter type summarizes an output voltage of medium voltage based on a series connection of power cells employing standard configurations of low-voltage components. The main problems of cascaded switched-capacitor multilevel inverters (CSCMLIs) are the harmful reverse flowing current of inductive loads, the large number of switches, and the surge current of the capacitors. As the number of switches increases, the reliability of the inverter decreases. To address these issues, a new CSCMLI is proposed using two modules containing asymmetric DC sources to generate 13 levels. The main novelty of the proposed configuration is the reduction of the number of switches while increasing the maximum output voltage. Despite the many similarities, the presented topology differs from similar topologies. Compared to similar structures, the direction of some switches is reversed, leading to a change in the direction of current flow. By incorporating the lowest number of semiconductors, it was demonstrated that the proposed inverter has the lowest cost function among similar inverters. The role of switched-capacitor inrush current in the selection of switch, diode, and DC source for inverter operation in medium and high voltage applications is presented. The inverter performance to supply the inductive loads is clarified. Comparison of the simulation and experimental results validates the effectiveness of the proposed inverter topology, showing promising potentials in photovoltaic, buildings, and domestic applications. A video demonstrating the experimental test, and all manufacturing data are attached.

This work proposes a new multilevel inverter consisting of basic and submultilevel units. The basic unit is made-up of four isolated dc voltage sources, two bidirectional switches and ten unidirectional switches. To increase the number of the output voltage levels, a cascaded architecture based on series connection of sub-multilevel is proposed. The proposed inverter utilizes two algorithms to determine the values of dc voltage sources. Number of IGBTs, dc voltage sources, gate driver circuits, variety of dc voltage sources and peak standing voltage on the switches are calculated and their optimization to produce maximum number of levels in output voltage is investigated. To examine advantages of the proposed inverter, the topology is compared with other topologies. The results show superiority of proposed topology over most conventional topologies, in number of circuit components. Finally, to confirm the performance of the proposed multilevel inverter, experimental results of a 25-level inverter prototype are provided.

A new three phase multilevel inverter with reduced number of components count is proposed in this paper. This inverter is designed using a single DC source per phase to generate multiple level output voltage which makes it suitable for low and medium voltage applications, including ac-coupled renewables or energy storages. A generalized circuit configuration is shown in this paper following which the number of output voltage level can be increased as per expectation. Although, each element endures the voltage stress equivalent to the input DC voltage, the value of total standing voltage (TSV) is reduced by the utilization of minimized number of components with respect to the number of series connected capacitors. Further, staircase modulation scheme is used to generate the switching signals. Hence, the proposed inverter can be operated at low switching frequency with optimal output current harmonic distortion which decreases switching losses and suppresses power factor falling. In order to validate the theoretical explanations and practical performances of the proposed inverter, the hypothesis is simulated for 9, 13 and 39 output voltage level inverters for three phase with a line voltage total harmonic distortion (THD) of 6.06%, 4.16% and 2.10% respectively in MATLAB/Simulink and a 5-level single phase laboratory prototype is implemented in the laboratory.

Multilevel inverters (MLI) are now becoming an important element for medium-voltage high-power applications. A low switch count MLIs are more popular due to their high efficiency, low cost, and easy control for the output having a higher number of levels. A new MLI topology for single-phase applications based on switched dc voltage source with reduced switch count is proposed in the paper. The presented topology is developed with the constraints of lesser blocking voltage of the switches with a higher number of levels at the output using a lower number of components. The proposed topology can also work in the symmetrical and asymmetrical configuration. Selective harmonic elimination (SHE) technique is applied to synthesize the staircase output voltages with eliminations of lower order harmonics by optimized computation of angles for switching operation. The comparative studies with the MLIs recommended in recent times show the importance of the proposed MLI structure in terms of reduced switch count and lower voltage stresses across switches in both asymmetrical and symmetrical configurations. The experimental results are presented to confirm the performance of the proposed topology.

This paper proposes a step-up 3-Ф switched-capacitor multilevel inverter topology with minimal switch count and voltage stresses. The proposed topology is designed to provide five distinct output voltage levels from a single isolated dc source, making it suitable for medium and low-voltage applications. Each leg of the proposed topology contains four switches, one power diode, and a capacitor. The switching signals are also generated using a staircase universal modulation method. As a result, the proposed topology will operate at both low and high switching frequencies. To highlight the proposed topology’s advantages, a comparison of three-phase topologies wasperformed in terms of the switching components, voltage stress, component count per level factor, and cost function withthe recent literature. The topology achieved an efficiency of about 96.7% with dynamic loading, and 75% of the switches experienced half of the peak output voltage (VDC), whereas the remaining switches experienced peak output voltage (2VDC) as voltage stress. The MATLAB/Simulink environment was used to simulate the proposed topology, and a laboratory prototype was also built to verify the inverter’s theoretical justifications and real-time performance.

The apparent advantages of Multilevel Inverter (MLI) topologies in handling medium and high power with less loss in switching and lower harmonic distortion in an output voltage waveform makes it better than the conventional inverter. However, the MLI topologies utilize a large number of DC power supplies and power semiconductor devices. They also have a higher value of total standing voltage (TSV). Moreover, capacitor voltage balancing problems, self-voltage boosting inability, and complex control techniques require a relook and improvement in their structure. More recently, Switched-Capacitor Multilevel Inverter (SCMLI) topologies have been proposed to overcome the shortcomings of MLIs. In this paper, a generalized structure for a single-phase switched capacitor multilevel inverter (SCMLI) with self-voltage boosting and self-voltage balancing capability is proposed. A detailed analysis of a general structure of SCMLI is presented. The comparative analysis of the structures is carried out with recently reported topologies to demonstrate superiority. An optimized low-frequency modulation controls the output voltage waveform. The simulation and experimental results are included in the paper for single-unit symmetric (9-level voltage) and asymmetric (17-level voltage) configurations. [ABSTRACT FROM AUTHOR]

Most of the switched capacitor multi‐level inverters (SC‐MLIs) are designed with a single isolated voltage source and capacitors where voltage levels are obtained by the addition of these sources only. The common problems arise in SC‐MLIs are an unequal number of conducting paths, higher voltage drop across capacitors, sum of total inverter DC link voltages across the highest voltage rated switches and higher total standing voltage (TSV). The motivation of this work is to design a hybrid generalized SC‐MLI with reduced components aiming to maintain a constant voltage across the capacitors, to achieve higher voltage gain with minimum components used, minimum conducting paths, lower TSV, cost‐effective and an efficient inverter. A generalised SC‐MLI structure is also proposed, which can multiply the voltage across the capacitors in a binary asymmetrical manner. The design parameters of the proposed hybrid SC‐MLI topology are compared with the recently developed SC‐MLIs in terms of the number of switches, capacitors, TSV, conducting switches and industrial components cost to prove its superiority and effectiveness of the proposed inverter. The experimental prototype of a specimen 9‐level and 17‐level inverters are implemented using DS1103 and the corresponding results are presented. [ABSTRACT FROM AUTHOR]

A novel asymmetrical nine-level inverter topology using only six switches along with its generalized structure are presented in this paper. The proposed reduced switch multilevel inverter topology makes use of a lower total standing voltage for a required output voltage as compared to the existing ones. One of the major advantages of the proposed multilevel inverter over other existing topologies is that, the circuit can be extended to a higher-level inverter, by cascading a few proposed inverter modules and can also be extended to the three-phase structure very easily, thereby making the inverter structure simple. In addition to this, the proposed inverter module does not require any additional H-bridge circuit to obtain the negative voltage levels for AC voltage, resulting in reduced voltage stress on the switches. This paper also incorporates an effective technique to determine the total standing voltage as well as the switching and conduction losses of the inverter. The MATLAB/Simulink based proposed nine-level as well as an 81-level inverters are modeled and the simulation results are presented. An experimental prototype of nine-level inverter using six switches is developed and tested to validate the simulation results. [ABSTRACT FROM AUTHOR]

In this paper, a novel 15 level symmetric switched capacitor multilevel inverter (SCMLI) structure is proposed first. The structure is developed by using 3 non-isolated DC power sources. The capacitors utilized in the structure can be charged to the summation of all the power supplies by turning ON the minimum number of switching devices. After that a generalized structure of the proposed SCMLI is developed. The voltage and current stresses for different switches of the proposed general structure are discussed. The selection procedure of switched capacitors for the proposed 15 level inverter is presented for resistive and resistive-inductive load conditions. A detailed comparison study of the proposed structure with other recently developed structures shows that the proposed structure requires reduced number of components and the number of switches in the conducting path as compared to other SCMLI structures for generating an output voltage level. Further, the overall cost of the proposed and suggested topologies has been compared based on a cost function (CF). It has been observed that the proposed structure is more cost effective as compared to others. An extensive experimental study conducted on a 15 level SCMLI laboratory prototype proves the effectiveness and merits of the proposed structure. [ABSTRACT FROM AUTHOR]

The apparent advantages of Multilevel Inverter (MLI) topologies in handling medium and high power with less loss in switching and lower harmonic distortion in an output voltage waveform makes it better than the conventional inverter. However, the MLI topologies utilize a large number of DC power supplies and power semiconductor devices. They also have a higher value of total standing voltage (TSV). Moreover, capacitor voltage balancing problems, self-voltage boosting inability, and complex control techniques require a relook and improvement in their structure. More recently, Switched-Capacitor Multilevel Inverter (SCMLI) topologies have been proposed to overcome the shortcomings of MLIs. In this paper, a generalized structure for a single-phase switched capacitor multilevel inverter (SCMLI) with self-voltage boosting and self-voltage balancing capability is proposed. A detailed analysis of a general structure of SCMLI is presented. The comparative analysis of the structures is carried out with recently reported topologies to demonstrate superiority. An optimized low-frequency modulation controls the output voltage waveform. The simulation and experimental results are included in the paper for single-unit symmetric (9-level voltage) and asymmetric (17-level voltage) configurations.

Nowadays, the multilevel inverter has gained huge attention and has become more popularized in high voltage and high-power applications with low harmonics. As the number of output voltage increases, the harmonic content of the output voltage waveform decreases. In this paper, a comparison of cascaded H-bridge and cross-switched multilevel inverters for 7, 9, 15, 21 levels will be carried out. The different control techniques that will be used for carrying out comparisons are space vector pulse width modulation (SPVPWM), sinusoidal pulse width modulation (SPWM), and third harmonic injection pulse width modulation (THI-PWM) respectively. Here, the seven-level inverter is discussed mainly and can be extended to any number of levels.