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III-Vs like GaN and InP are the most promising substrates for high performance RF, photonics, and power electronics. However, III-V processing has been a gating factor in achieving smaller features and better devices. A primary cause of this setback has been large feature sizes resulting from limitations of older equipment. Older equipment must be used because it is compatible with III-V wafer sizes, which are smaller, costlier, and of lower quality compared to silicon wafers. To use the same cutting-edge tools and systems that silicon has immensely benefited from, III-V wafers must be made in a 300 mm format so that they can be processed in the same facilities as Si wafers. This thesis proposes and demonstrates one method of reconstituting gallium nitride (GaN) to create a large wafer that can be processed using large wafer tooling. Investigating these techniques also develops thermocompression bonding process capability that can be transferred to eventual III-V to Si vertical monolithic integration. For example, a GaN power amplifier can be vertically bonded (3D stacked) to a silicon dielet, decreasing the scale of power delivery networks by almost 1000x (from mm scale to �m scale). However, integration of gold into active silicon devices would require significant reliability study that is outside the scope of this work.In this thesis, GaN on (111) silicon was chosen as a starting III-V material. After dicing, these dielets were bonded face-to-face to a (100) silicon handler with a gold-to-gold thermocompression bonded interface. The bulk of the dielet thickness is silicon, and it is removed with a hydrofluoric acid, nitric acid, and acetic acid etch (HNA). This leaves behind a thin (< 1 �m) film of III-V substrate, which is planarized and passivated with plasma enhanced chemical vapor deposition (PECVD) oxide and chemical mechanical planarization (CMP). The techniques developed in this thesis can be adapted to reconstitute other III-V materials, like GaN on sapphire, indium phosphide (InP), and gallium arsenide (GaAs).

Cu-Cu direct interconnects are highly desirable for the microelectronic industry as they allow for significant reductions in the size and spacing of microcontacts. The main challenge associated with using Cu is its tendency to rapidly oxidize in air. This research paper describes a method of Cu passivation using a self-assembled monolayer (SAM) to protect the surface against oxidation. However, this approach faces two main challenges: the degradation of the SAM at room temperature in the ambient atmosphere and the monolayer desorption technique prior to Cu-Cu bonding. In this paper, the systematic investigation of these challenges and their possible solutions are presented. The methods used in this study include thermocompression (TC) bonding, X-ray photoelectron spectroscopy (XPS), shear strength testing, scanning electron microscopy (SEM), and energy dispersive X-ray spectroscopy (EDX). The results indicate nearly no Cu oxidation (4 at.%) for samples with SAM passivation in contrast to the bare Cu surface (27 at.%) after the storage at −18 °C in a conventional freezer for three weeks. Significant improvement was observed in the TC bonding with SAM after storage. The mean shear strength of the passivated samples reached 65.5 MPa without storage. The average shear strength values before and after the storage tests were 43% greater for samples with SAM than for the bare Cu surface. In conclusion, this study shows that Cu-Cu bonding technology can be improved by using SAM as an oxidation inhibitor, leading to a higher interconnect quality.

Silicon-based microchannel technology offers unmatched performance in the cooling of silicon pixel detectors in high-energy physics. Although Si–Si direct bonding, used for the fabrication of cooling plates, also meets the stringent requirements of this application (its high-pressure resistance of ~200 bar, in particular), its use is reported to be a challenging and expensive process. In this study, we evaluated two alternative bonding methods, aiming toward a more cost-effective fabrication process: Si-Glass-Si anodic bonding (AB) with a thin-film glass, and Au-Au thermocompression (TC). The bonding strengths of the two methods were evaluated with destructive pressure burst tests (0–690 bar) on test structures, each made of a 1 × 2 cm2 silicon die etched with a tank and an inlet channel and sealed with a plain silicon die using either the AB or TC bonding. The pressure resistance of the structures was measured to be higher for the TC-sealed samples (max. 690 bar) than for the AB samples (max. 530 bar), but less homogeneous. The failure analysis indicated that the AB structure resistance was limited by the adhesion force of the deposited layers. Nevertheless, both the TC and AB methods provided sufficient bond quality to hold the high pressure required for application in high-energy physics pixel detector cooling.

New wide bandgap semiconductors with high working temperature demand interconnect materials that can serve at high temperature. The copper nanoparticle paste is a potential alternative interconnect material. However, it is confronted with the problem of copper oxidation. In this article, commercial copper nanoparticles with average diameter of 100 nm were first simply treated with lactic acid to remove the surface oxide and the resulting cupric lactate on the surface can prevent the oxidation of copper. Then the nanoparticles were mixed with 3-dimethylamino-1,2-propanediol to prepare an anti-oxidative copper paste. The sintered films of the paste showed good electrical conductivity. The paste can be used for Cu–Cu thermocompression bonding at low temperature in air. The shear strength of the Cu/paste/Cu samples reached 28.7 ± 1.6 MPa after thermocompression at 225 °C under 8 MPa in air. The coalescence of the copper nanoparticles and the connection between copper nanoparticles and bulk copper surface were observed.

The choice of metals, bonding conditions and interface purity are critical parameters for the performance of metal–metal bonding quality for quantum cascade lasers (QCLs). Here, we present a novel approach for the thermocompression bonding of Cu–Cu thin films on GaAs-based waveguides without having any oxide phase, contamination or impurities at the interface. We designed a hybrid system in which magnetron sputtering of Ta, thermal evaporation of Cu and Cu–Cu thermocompression bonding processes can be performed sequentially under high vacuum conditions. GaAs/Ta/Cu and Cu/Ta/GaAs structures were thermocompressionally bonded in our in-situ homebuilt bonding system by optimizing the deposition parameters and bonding conditions. The grown thin film and the obtained interfaces were characterized using x-ray diffraction (XRD), scanning electron microscopy (SEM) and energy-dispersive x-ray spectroscopy (EDX) techniques. The optimum Ta and Cu films’ thicknesses were found to be about 20 nm and 500 nm, respectively. EDX analysis showed that the Ta thin film interlayer diffused into the Cu structure, providing better adhesivity and rigidity for the bonding. Additionally, no oxidation phases were detected at the interface. The best bonding quality was obtained when heated up to 430 °C with an applied pressure of 40 MPa during bonding process.

The apparent saturation of aggressive Moore’s law scaling of semiconductor technologies is pushing the boundaries of traditional packaging and integration schemes to accommodate the ever-growing data bandwidth and heterogeneity demands. In this article, we demonstrate the silicon-interconnect fabric (Si-IF) technology as a superior alternative to conventional printed circuit boards (PCBs) to enhance system scaling. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform to assemble and integrate massive wafer-scale systems. In this technology, dielets are closely assembled on the Si-IF at small interdielet spacings ( $\leq 50~\mu \text{m}$ ) using fine-pitch ( $\leq 10~\mu \text{m}$ ) die-to-substrate interconnects allowing for tight integration on a system-level package. To achieve these fine-pitch interconnects, a novel assembly technique using solder-less direct metal–metal [copper–copper (Cu–Cu)] thermal compression bonding was developed. Using this process, sub-10- $\mu \text{m}$ -pitch interconnects with a low specific contact resistance of $\leq 0.7~\Omega \cdot \mu \text{m}~^{\mathrm{ 2}}$ and high shear force of 90 N for 4-mm 2 dies were successfully demonstrated. Moreover, these fine-pitch interconnects combined with the small interdie spacing provide a large number of parallel short links ( $\leq 500~\mu \text{m}$ ) with low loss (≤2 dB) for interdielet communication that is comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) protocol at low link latency ( $23\times $ higher data bandwidth, 3– $65\times $ lower latency, and 5– $40\times $ lower energy per bit compared to existing integration schemes.

Thermal compression bonding (TCB) has been widely used in flip chip bonding processes for three-dimensional integrated packaging. Therefore, studying the TCB process and solder joint structure is significant for improving reliability. In this study, a Ni layer was deposited between the Cu/Sn-3.5Ag solder bumps of upper and lower chips, and TCB process tests were carried out at different bonding temperatures, forces and times. The solder height at the top and bottom of the copper pillar were recorded. Through the establishment of a mathematical analysis model, the relationship between the solder joint height and maximum stress was analyzed theoretically, and the trend of the shear stress and solder joint height was obtained from die shear tests. Then, the solder joint morphology, strength and microstructure composition of the microbumps were observed after aging. Our results showed that the growth rate of intermetallic compounds (IMCs) for Cu/Sn-3.5Ag microbumps with a 25 μm diameter was 2.5 times those with a 100 μm diameter and that the Ni barrier layer prevented the diffusion of Cu in Sn-3.5Ag solder. In addition, the Ni layer improved the strength of the Cu/Sn-3.5Ag joints after aging. Finally, with extended aging time, the fracture site was found to move from the solder region to the Cu6Sn5 layer for the Cu/Sn-3.5Ag samples, while it remained at the Sn-3.5Ag/IMC interface for the Cu/Ni/Sn-3.5Ag samples.

During friction welding of Al alloy to steel, the metallurgical reaction of Al and Fe can be occurred under the coupling effect of heat and rotational plastic flow. However, the detailed role of them in contributing intermetallic compounds (IMCs) development remains largely unknown, causing the significant impediment in further tailoring IMCs. In this regard, a thermal compression bonding process was elaborately designed to highlight the influence of frictional flow on the formation of IMCs in friction welding. From the results, it was revealed in friction welding process, frictional flow significantly promoted the formation of sub-micron sized IMCs along weld interface, since in thermal compression bonded specimens, a significantly thinner IMCs were confirmed. Due to the non-uniform distribution of heat and plastic flow rate at different regions along interface, an inhomogeneous distribution of IMCs in terms of thickness was also identified in friction welded joint. Additionally, the frictional flow and stirring effect of Al alloy also resulted in the convex on friction surface at steel side stripped into Al alloy, enhancing the appearance of IMCs particles. Therefore, frictional plastic flow was supposed to predominately contribute to the growth of IMCs in friction welding of Al alloy to steel.

Thermocompression bonding (TCB) is an important process in electronic packaging and is widely seen as a promising technology for miniaturized electronic devices. However, this process usually yields a lower throughput compared to more conventional mass-reflow processes, mainly because the thermal distribution uniformity across the bonding plane, as required for reliable joints, is achieved with longer bonding dwell times. Higher throughputs could be achieved by reducing the dwell time and increasing the heating rates, but this comes at the cost of higher temperature variations between the center and edges of the bonded component, leading to defects such as nonwet or bridged. Reliable temperature distribution measurements are thus needed to eliminate these joint defects. We present a novel method of temperature measurements to quantify the thermal limits of the TCB process. A microfabricated sensor with high temporal and spatial resolution was designed and fabricated for in situ temperature profile measurements up to 250 °C. This work aims to evaluate the influence of different heating rates on the temperature distribution across the chip surface, as well as on the resulting bonding quality. The bonding quality was assessed by the evaluation of bonding pull strength and interfacial defect characterization. The results demonstrate that slow heating rates (50 °C/s) lead to bridge defects and high heating rates (>80 °C/s) induce nonwetting defects in the solder joints. The solder joint defects can be related to the temperature uniformity measurements performed with the RTD sensor, thus providing a mean to more efficiently optimize the TCB heating rate in industrial processes.

MEMS atomic vapor cells have a large variety of applications in chip-scale atomic devices such as clocks, gyroscopes or magnetometers. These cells are usually hermetically sealed by anodic bonding of borosilicate to silicon, a proven and reliable method, yet showing specific limitations such as inherent oxygen contamination of the cavity or limitation to a few combinations of materials. As an alternative, we report on the successful wafer-level fabrication of cells sealed by Cu-Cu thermocompression bonding. This alternative technique allows to overcome the constraints of anodic bonding while allowing a new variety of other materials. Characterization of the bonding quality is presented as well as a spectroscopic characterization in view of use for chip-scale atomic clocks (CSACs). [2019-0151]

Internet of Things (IoT) accelerated by the rapid progress of 5G is bringing a lot of challenges to semiconductor packaging technologies. In particular, flip-chip bonding technology is strongly required to realize ultrafine-pitch products, such as network, graphic, and artificial intelligence (AI) processors. Thermal compression bonding (TCB) with pre-applied underfill materials, such as nonconductive paste or nonconductive film (NCF), has been expected as one of the effective solutions for these applications for a long time. Nevertheless, the actual availability is still limited due to its high process cost. In other words, innovative breakthrough to achieve reasonable TCB cost is necessary to support the expansion of IoT. So far, some kinds of multiple die bonding processes represented by collective bonding have been proposed and demonstrated with conventional NCFs. However, it is becoming clear that the conventional NCFs optimized as fast cure type are very difficult to have enough processability for the multiple bonding processes due to mismatch between reactivities of the materials and bonding process conditions. That is why the new NCF dedicated to the multiple die bonding processes has been developed in this article. The developed NCF was designed to survive long-time thermal exposure on a bonding stage so that the collective bonding could be completed with reasonable process margin. To achieve target specifications, this article has started with the design of a new resin composition applied to the developed NCF. Then, basic properties required for NCFs, such as thermal stability and electrical insulation, were investigated in feasibility studies. Finally, TCB was demonstrated, and reliable solder joints were formed without any abnormality even after extended thermal exposure on the bonding stage. Moreover, it was found that the developed NCF might have the potential to achieve void-free encapsulation by pressure curing.

The thermocompression bonding of conductive polymer films was investigated to achieve a flexible wiring and packaging technique for organic and flexible electronics. Conductive polymer poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS) films were successfully bonded together by thermocompression even at rather low temperatures of 50–100 °C, especially through surface activation treatment using ultraviolet light irradiation. After thermocompression, the PEDOT:PSS films maintained their ohmic electrical conductivity even though the adhered interface had a contact resistivity of less than 1.3 Ω cm2. To examine the applications to electrical bonding, PEDOT:PSS patterns were fabricated on polyethylene naphthalate (PEN) substrates, and the bonding force after thermocompression was investigated. The adhesiveness of bonding was highly improved, and the films were strongly adhered at a bonding temperature of ~100 °C, which was lower than the glass transition temperature (Tg: 160 °C) of the PEN substrates. X-ray photoelectron spectroscopy (XPS) analysis of both the PEDOT:PSS and PEN surfaces and the attenuated total reflectance FT-IR (ATR-FT-IR) for the PEN surfaces indicated that the oxidized species of alcohol and carboxylate were generated after the surface activation process. These chemical species can form hydrogen bonds or covalent bonds that provide robust bonding interfaces. The thermocompression bonding of conductive polymer films was investigated to achieve a flexible wiring and packaging technique for flexible electronics. Conductive polymer poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS) films were successfully bonded together by thermocompression, especially through surface activation treatment using ultraviolet light irradiation. After thermocompression, the PEDOT:PSS films maintained their ohmic electrical conductivity even through the adhered interface. The surface state analysis of the PEDOT:PSS indicated that the oxidized species were generated after the surface activation process. These chemical species can interact each other and provide robust bonding interfaces.

Diffusion is one of the most critical and key factor for achieving low temperature and low pressure thermocompression bonding. In this work, we propose a novel concept of modifying density conditions within the Cu films. The density of film was varied by varying the DC bias applied for the sputter deposition. While two samples of different densities are brought in contact with each other, Cu atoms from the thin film having higher density of atoms tends to interdiffuse into the thin film having lower density. Optimal dc biasing conditions for pair of wafers were figured out based on the pre-bonding characterizations and it yielded an excellent bonding at Sub 100 °C. No observable bond interface X-TEM images and bond strength of 164 MPa confirmed the quality of bonding. Furthermore, bonded structure undergone various reliability tests include multiple current stressing test, temperature cycling test and relative humidity test confirms Cu-Cu bonding using surface density gradient engineering is stable and promising candidate for future 3D IC integration applications.

A bonding technology using electroplated Au microstuds for ultraviolet (UV) light-emitting diodes (LEDs) has been investigated. Au studs with diameter, height, and pitch of about 15, 8, and $30~\mu \text{m}$ , respectively, were electroplated on standard UV LED chips on wafer level. The parameters for the thermocompression bonding (temperature, force, and time) were varied, and a critical temperature for bonding was identified. The electroplating process, in particular the plating base, strongly influences the adhesion of the Au microstuds and, therefore, the strength of the bond. Electro-optical measurements of bonded UVB LEDs as well as thermal resistance measurements and simulations of the devices show that Au–Au thermocompression bonding, using Au microstuds, can result in devices whose performance is similar to those fabricated using the conventional bonding technology of soldering with Au–Sn paste. Hence, the use of Au microstuds is an interesting alternative for bonding UV LED chips due to the ease of implementation, the stability of the bond, the comparable thermal resistance to Au–Sn, as well as the possibility to realize more complex and smaller chip geometries.

As the distance between the copper pillars and the size of the solder continues to shrink, the solder joints are subjected to extremely high current density and thermal energy density. This paper is aiming to analyze the electromigration reliability of solder joint with different shapes. Both experiment and finite element method (FEM) analysis were performed to investigate the Mean-time-to-failure(MTTF) of solder joints. Firstly, finite element models of solder joints were established. And then, the current density, temperature, and stress distribution in the solder joints were analyzed according to the model. After that, the chip samples were made by thermal compression bonding. The electromigration experiments were carried out at 150°C, and the interface evolution of solder joints with different shapes was analyzed. Finally, the modified Black's formula was adopted to calculate the MTTF of three different solder joints. According to the calculation results, it can be obtained that cylinder-shaped solder joints have better electromigration reliability than hourglass-shaped bumps and barrel-shaped bumps.

Thermal compression bonding provides a good solution for the packaging of micro-LED chips, greatly increases the resolution of micro-led, and can achieve higher density integration and better display effect. In order to study the thermomechanical reliability and display stability of micro-LED devices under thermal cycling load and working power load, this paper first explains the limitation of thermal expansion coefficient (CTE) mismatch on the size of flip chip devices by mathematical method, and proposes a low temperature indium bump flip chip bonding technology which can overcome this defect. Then, the finite element model is established to study the influence of different metal bump materials on the reliability of micro-LED devices under thermal cycling load, and the display stability is analyzed combined with the wavelength drift characteristics of micro-LED devices.

Glass is an ideal material for microfluidic chips because of its pressure resistance, chemical stability, optical transparency, and thermal stability. Two-layer or three-layer microfluidic glass chips, composed of one or two cover layers and one structural layer, have been widely applied to two-dimensional microfluidic systems. Due to the fabrication difficulties in aligning and bonding multiple glass layers, multi-layer glass chips (more than three layers) are underutilized, although they are essential to deliver more complicated microfluidic functionalities and achieve more accurate microfluidic manipulations. This work proposes a fabrication process based on rapid laser cutting of single glass layers and one-time thermocompression bonding of multi-layer chips and demonstrated it with a five-layer microfluidic chip for three-dimensional (3D) hydrodynamic focusing. The pressure and temperature are the key parameters for multi-layer bonding, which are experimentally determined to be 0.4 MPa and 605 ℃. Five-layer glass microfluidic chips could be fabricated within 6 h with a bonding strength of 0.6 MPa. This simple, easy-to-operate fabrication method for the rapid production of multi-layer glass microfluidic chips will be conducive to the wide application of multi-layer microfluidic glass chips.

Stretchable electrodes based on elastomer like Polydimethylsiloxane (PDMS) have been utilized as the more conformal interface with soft tissues in recent years, but most connection methods between stretchable electrodes and flexible flat cable (FFC) are time-consuming and unreliable, such as printing conductive paste on the bonding pads or clamping this area to the connector. In this work, the efficient thermocompression bonding with the aid of thermal release tape is developed, and the high yield is achieved before and after stretching to 20%. This method is especially suitable for the high-precision polymer-based electrodes on the soft elastomer substrate.

Moore's law has been slowed down in transistor scaling, but the demands of high computing processing does not cool down and the data rate transmission is growing exponentially in each day. The surge in high data rate causes present DDR4 memories succumb to this horrendous needs. High bandwidth memories (HBM) are then developed to fulfill these requirements. The upended trends drive up chiplets integrated package evolution. Presently most of these chiplets integrated packages are either homogeneously or heterogeneously packed together using 2.5D or Fan-Out-Multi-Chip Module. And these packages contain of micro bump pitches at the range of $40\sim 55 \mu \mathrm{m}$ . While HBM package are either stacked by 4 or 8 heights of memories dies with bump pitch of $40 \mu \mathrm{m}$ . Hybrid bond are then developed for much higher I/O density. However, hybrid bond technology has better economic values for bump pitch which is equal or below than $10 \mu \mathrm{m}$ . There is a grey area of bump pitch between $10\ \mu \mathrm{m}$ to $55\ \mu \mathrm{m}$ . Shall this package be assembled by hybrid bonding, reflow soldering, or thermal compression bonding (TCB)? The main challenges of this fine micro bump interconnections come with bump coplanarity, Kirkendall void formation and capillary underfill flow between the chip to chip spaces. This paper provides the answers to these challenges. A 3D package with $20 \mu \mathrm{m}$ bump pitch using chip to wafer stacking is developed. There are two test vehicles: TV 1 and TV 2 under the same conditions of $6.5^{\ast} 10.1\ \text{mm}^{2}$ in top chip, $10.1^{\ast} 11.1\ \text{mm}^{2}$ in bottom chip, $13\ \mu \mathrm{m} (\text{diameter})/20\ \mu \mathrm{m}$ (pitch) bump. TV 1 uses solder reflow as stacking technology while TV 2 uses TCNCF (Thermal Compression Non Conductive Film.) Two types of bonding technologies are applied for comparison, which are solder reflow and thermal compression bonding (TCB). The test vehicle consists of 2 stacked chips, with die thickness of $70 \mu\mathrm{m}$ each. Top chip is first singulated and then placed on second chip at a wafer formed. Prior to the placement, the bump coplanarity is collected prior to placement. The chip-to-wafer bonding are then established by reflow soldering and TCB. Underfill is dispensed to the chip to chip gap is characterized. Optimized underfill materials are then applied to subsequent process. Followed by molding and grinding top chip to $70\ \mu \mathrm{m}$ thick. The stacked up chip modules are then placed on substrate using conventional flip chip process. The final packages are first electrically tested then stressed up to 10 times reflows and high temperature storage at 150 °C for 1000 hours. At the interim of readouts, the units were electrically verified prior to cross section. With the optimized conditions, 3D package has been successfully passed above thermal stress without Kirkendall void formation. In this paper, results of the bump coplanarity, characterization of underfill flow, and Kirkendall void inside the micro bump are presented and discussed. Cross-section of the micro bump before and after reliability tests will be shared.

We introduce a new packaging technology termed as Direct Bonded Heterogeneous Integration (DBHi) where a Si-bridge is directly bonded to and in between processor chips using Cu pillars, allowing high-bandwidth low-latency low-power communication between the chips. The DBHi package structure, test vehicle design, and bond and assembly details are first described. The test vehicle package consists of chips with standard interconnect pitch where they join to a laminate chip-carrier and fine-pitch pads in the region where the chips joins to a bridge. The bridge has Cu pillars correspondingly mating to the pads on the chips. The bond and assembly sequence starts with first joining the silicon chips and bridge using a thermocompression bonding process followed by a mass reflow join of the chips to the laminate. The assembly is then underfilled and capped using specialized techniques. Mechanical modeling was extensively used to simulate the DBHi structure and assembly process to allow material selection and reliability prediction. The mechanical models were calibrated using warpage measurements. The stress/strain reliability metrics of the DBHi package are compared to a non-bridge package of the same dimensions. Results show that the main focus should be directed towards ensuring a robust assembly process as the standard reliability stress/strain metrics of the DBHi package are very similar to a non-bridge package. Thermal measurements using chip heaters and temperature sensors were conducted to calibrate a numerical thermal model of the DBHi package. The thermal model was exercised to show the relation between the allowable chip and bridge power densities for the particular package size and cooling conditions. DBHi test packages were created using the best-known assembly process and then measured for continuity performance. A variety of inter- and intra-bridge daisy chain nets were incorporated into the test vehicle for continuity measurements. Post-assembly continuity measurements demonstrated a robust assembly process for multiple rounds of assembly. Reliability performance was demonstrated using standard JEDEC tests of thermal cycling, aging, and temperature/humidity.

Cu/insulating material hybrid bonding technology was a promising process for high performance three-dimensional integrated package. A novel polyimide (PI) and thermal compression bonding (TCB) process were proposed for chip to wafer hybrid bonding. The new PI was developed by re-designing key components of the formulation. It showed high adhesion after TCB and high reliability performance. For the PI to PI bonding process evaluation, there were not any visible voids after pre-bonding at 250-350 °C and after TCB at 300 °C. Cu/PI co-planarization process was confirmed, and the PI showed a practical removal rate even though the PI was cured at high temperature. Furthermore, the PI showed highly smooth surface after CMP.

In this manuscript, we are demonstrating a flux-less thermal compression bonding (TCB) process for large area (≥ 900 mm2) die-to-wafer assemblies in ambient as well as nitrogen environment using an in-situ formic acid (FA) vapor treatment method. A localized mini-environment is created by using a custom-designed shroud, which is mounted on the bondhead and allows delivery of FA vapors in very close proximity of the bonding surfaces. The shroud design ensures uniform distribution of reducing vapors over the entire bonding area e.g. 900 mm2. We show that our flux-less TCB approach results in excellent interfacial bonds, which are equally comparable to the conventional flux-based TCB processes. The most distinct feature of this flux-less process is total avoidance of post-TCB clean-up step.

In this work, a 3D Die-Stack on Substrate (3D-DSS) bonding process has been developed to demonstrate a 3D die stack that has been joined to a mixed pitch ( $5\ \mu\mathrm{m}\ /\ 75\ \mu \mathrm{m}$ ) high density interconnect laminate. By using the 3D-DSS process with thermal compression bonding, the thin bottom die with the TSVs can be bonded to a thick top die by being held flat with a silicon vacuum stage. This study used a semiconductor die that consisted of mixed pitch ( $55\ \mu\mathrm{m}\ /\ 75\ \mu \mathrm{m}$ ) Cu pillars with a SnAg solder cap. The dimension of the high-density laminate was $35 \text{mm} \times 35\ \text{mm}$ and it had thin film high density layers on standard build up layer. The thin film layers are directly integrated to one side of a conventional substrate. A major challenge for this technology lies in the interconnection reliability. To address that, sub-modeling of the interconnects was performed. The stresses in the solder micro-bump, back-end-of-the-line (BEOL) and the vias in the wiring level is presented. A selective cross-sectional analysis was used to study the geometry of the micro-bump connections after forming the 3D die stack on the advanced ground rule laminate. The analysis confirmed that mixed pitch solder joints along the perimeter of chips were joined with full wetting and no bridging.

Moore's law of transistor scaling over the past few decades warrant a paradigm shift in packaging and integration methodologies. Silicon interconnect fabric (Si-IF) technology is a wafer-scale, fine pitch, package less, heterogeneous integration platform that enables high package density by supporting dielet assembly at fine spacing. In Si-IF technology, bare dielets are assembled on a prewired silicon wafer using thermal compression bonding (TCB) at a small inter-dielet spacing ( $\leqslant 100\ \mu \mathrm{m}$ ) using fine pitch die-wafer interconnects ( $\leqslant 10\ \mu \mathrm{m}$ ). This enables Si-IF technology to support high power systems on a wafer. A novel high-power delivery architecture enabling 40–60 kW power delivery to a 300 mm wafer is outlined. Prototype results for power delivery are presented.

Direct metal-metal thermocompression bonding (TCB) process is necessary to scale the bump pitches to $\leq 10\mu\mathrm{m}$ as previously demonstrated using Copper(Cu) to Copper TCB on Silicon Interconnect Fabric (Si-IF). However, to extend the bonding process to a wafer level assembly of dielets, passivation of exposed Cu is necessary throughout the bonding process. In this work, we explore Copper-to-Gold TCB process to address the problem of Cu oxidation on Si-IF substrate prior to bonding. Any exposed copper the Si-IF is capped with Titanium (Ti) and Gold (Au) of thickness 20 nm and 200 nm respectively. This gold coating prevents any oxidation of copper on the substrate irrespective of the TCB temperature. First, the Cu-Au phase diagram was analysed to get an estimate of the parameters necessary for diffusion between Au and Cu during TCB. Next, bonding tests were performed, in which $2\mathrm{X}2\ \text{mm}^{2}$ dielets with copper pads were bonded to blanket Au capped Cu samples. We found Cu to Au thermocompression bonding to be feasible, even when the Si-IF substrate was exposed to high temperatures (≈100°C) for several hours. With optimization of bonding force and time, the shear force required to remove die from the substrate was found to be ≈ 110 N. In addition, the reliability of the bonded structures were investigated through high temperature storage testing. Post high temperature storage at 125 °C for two weeks, the shear strength was found to vary within 10% of its pre-storage value. Using the optimized process, daisy chain dielets terminated with Cu pads were bonded to Au capped Cu pillars on the Si-IF. We observed 100% connectivity across all the testable daisy chains. The average specific contact resistance of each pillar was found to be $0.762\ \Omega-\mu\mathrm{m}^{2}$ which is close to that of pure Cu-Cu TCB based daisy chains. The gold capping eliminates the problem of Cu oxidation on Si-IF substrate and therefore this bonding mechanism can be extended to achieve full wafer dielet population even on large 300 mm Si-IF substrates.

We used nanoindentation method to evaluate the mechanical properties of two solders, Sn-57.6Bi-0.4Ag (melting point 138°C) and Sn-3.0Ag-0.5Cu (SAC305, melting point 217°C), used in thermal compression bonding. The following conditions were used to determine the optimum bonding conditions: 190, 210, and 230°C and 2, 2.5, and 3 MPa for Sn-57.6Bi-0.4Ag; and 280, 300, and 320°C and 3, 5, and 7 MPa for SAC305. The solder hardness decreased as the bonding temperature increased, which demonstrated that bonding strength decreases with grain growth, in accordance with the Hall-Petch equation. Increased stiffness and elastic modulus were also observed alongside larger grains. Nanoindentation, which can accurately measure small parts for fine pitch packaging, is expected to be an effective technique for determining mechanical properties of a sample.

The main development challenge of low temperature hybrid bonding technology is the oxidation of Cu surface. The schemes to achieve the high-quality surface condition of Cu before bonding is urgently demanded. In this study, four acid solutions, including sulfuric acid (H 2 SO 4 ), hydrochloric acid (HCl), acetic acid (CH 3 COOH) and citric acid (C 6 H 8 O 7 ), were chosen as wet pretreatment approaches to remove Cu oxides based on the respective chemical reactions. To investigate the influence of these acid solutions on bonding surface, different acid immersion times are examined and the XPS analysis is conducted to check the surface component composition. Next, thermal compression bonding (TCB) is conducted after the Cu oxide removal process, followed by various analyses, including SAT analysis to validate bonding results, FIB and SEM analyses to inspect bonding interface, and pull test to measure bonding strength. The results of analyses verify the ability of different wet pretreatment to improve Cu-Cu bonding.

Semiconductor package sizes are getting smaller and bump pitches narrower while the number of input/output (I/O) continues to increase. The traditional flip-chip process, which assembles the chip with copper (Cu) pillar interconnects to the substrate using a mass reflow technique faces several hurdles as package dimensions become more challenging. These include high stress between low-k die and substrate, die shift, and die cracking when the pitch is narrower than $\mathrm{100}\ \mu\mathrm{m}$ . The thermocompression bonding (TCB) process can help overcome these challenges. Pre-applied underfills like non-conductive paste (NCP) and non-conductive film (NCF) enable the TCB process. NCP is applied directly on the substrate, while NCF is applied on the wafer prior to TCB. This paper discusses the key material properties and TCB parameters that are critical for good solder joint formation and void-free gap-filling. During the NCP TCB process, void issues are common and several factors (e.g. dispensing volume and pattern, bonding parameters and material properties) contribute to void formation. In this study, different dispensing patterns were evaluated to better understand this issue. Based on the experimental results, specific patterns appear to help reduce voiding. In terms of TCB process, focus was on the effect of bond speed on void performance. The speed of pushing out the NCP clearly affected the flow of NCP & void performance. Similarly, TCB process for NCF also require setting the right bond parameters to ensure good solder joints and zero void performance. Three key parameters were studied for bond optimization: bond force, contact temperature, and ramp rate. A wide range of bond forces, contact temperatures, and ramp rates were chosen for the experiments. After performing the TCB process, joint shape and void performance via CSAM were evaluated. Based on the study, an optimal condition was identified for better application performance. Subsequently, reliability tests such as MSL (85° C/85% RH) and uHAST were conducted.

The Silicon-Interconnect Fabric (Si-IF) is a wafer-scale platform in which bare dies are heterogeneously bonded to copper pillars using a thermal compression bonding (TCB) process. Electrical characteristics of interconnects in Si-IF are comparable to standard back-end wiring levels. A method of off-wafer communication via a high-bandwidth, low loss, high signal integrity connector can complement the Si-IF's excellent electrical characteristics for communication between the Si-IF and a PCB or another Si-IF. For standard packaged dies, signals and power are often delivered through ball grid arrays (BGAs) in which the package is soldered to a PCB. For wafer-scale systems, however, the large area of such a BGA would be prohibitively unreliable due to the coefficient of thermal expansion (CTE) mismatch between silicon and the PCB. Additionally, high inductance limits I/O data rates, particularly problematic in signaling through wire bonds. In this work we propose solutions for high-speed signal delivery and power delivery using the FlexTrate™ platform. For signal delivery we propose a flexible, high-speed connector which we call FlexCon. FlexCon consists of copper wiring over a grounded SU-8 dielectric on a highly flexible poly-dimethyl siloxane (PDMS) substrate. FlexCon is bonded via solder at either end, with one end at the edge of the Si-IF and the other bonded to a PCB or another Si-IF. Signals are transmitted through FlexCon differentially at up to 32 GHz per channel. Thermal stresses at the solder joints are minimal due to the low Young's modulus of the PDMS substrate. For power delivery, we propose the Compliant Power Platform. Here, the PCB onto which the Si-IF is mounted is segmented into smaller PCBs, embedded within PDMS, and interconnected using the FlexTrate™ process. The small area of the PCB segments mitigates thermal stresses due to CTE mismatch, enabling power delivery to the Si-IF using standard BGAs connected to through-wafer vias (TWVs) while significantly reducing stress in solder joints. Here, we present an electrical characterization of the FlexCon and an analysis of the proposed Compliant Power Platform.

In this work, a novel biocompatible flexible heterogeneous integration platform has been developed. Using thermal compression bonding and conductive adhesive, three different functional devices, including sensing array, analog front-end chip, and LED array, are integrated on the flexible biocompatible substrate. Moreover, the whole exposed area of the platform is designed to be processed with biocompatible material. Thus, this structure is a promising integration scheme for the biomedical applications. Bending tests and reliability tests have been also performed to validate the feasibility of this flexible heterogeneous integration platform.

We modified an epoxy with silane to improve the bondability and thermal properties of a non-conductive adhesive (NCA) for fine-pitch thermocompression (TC) bonding. The main objectives of this modification were to improve the silica dispersion in the NCA and its wettability to achieve a low coefficient of thermal expansion (CTE) without any filler entrapment and a robust bonding joint. A commercial diglycidyl ether of a bisphenol A and F mixture resin and 3-glycidyloxypropyl trimethoxysilane were synthesized at 250 °C for 2 h. An anhydride (hardener) and an imidazole (catalyst) were used as the NCA curing system. The CTE of the silane-modified NCA was 29.1 ppm/ °C, which was lower than that of a neat epoxy NCA (42.6 ppm/ °C), and was the result of uniform silica dispersion in the NCA matrix. The shear strength of the TC bonded joint was also improved from 31.8 MPa to 46.5 MPa (1.45 times higher) after the epoxy silane modification due to the improved wettability of the epoxy resin. Void formation in the cured NCA layer and silica filler entrapment at the Cu/Sn interface were also suppressed. Thus, this epoxy silane modification produced a robust and thermally reliable NCA material for fine-pitch interconnections.

Solder anisotropic conductive films (ACFs) consist of conductive solder particles, polymer resin, and flux activator. The flux activator removes solder oxide of solder particles by generated acid for the solder wetting during a thermocompression bonding process. In this article, eutectic Sn52In solder (Tm = 118°) particles were used as the conductive solder particle in the solder ACFs to reduce