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The effects of the parasitic gate capacitance and gate resistance (Rg) on the radiofrequency (RF) performance are investigated in LG = 0.15 μm GaN high‐electron‐mobility transistors with T‐gate head size ranging from 0.83 to 1.08 μm. When the device characteristics are compared, the difference in DC characteristics is negligible. The RF performance in terms of the current‐gain cut‐off frequency (fT) and maximum oscillation frequency (fmax) substantially depend on the T‐gate head size. For clarifying the T‐gate head size dependence, small‐signal modeling is conducted to extract the parasitic gate capacitance and Rg. When the T‐gate head size is reduced from 1.08 to 0.83 μm, Rg increases by 82%, while fT and fmax improve by 27% and 26%, respectively, because the parasitic gate–source and gate–drain capacitances reduce by 19% and 43%, respectively. Therefore, minimizing the parasitic gate capacitance is more effective that reducing Rg in our transistor design and fabrication, leading to improved RF performance when reducing the T‐gate head size. [ABSTRACT FROM AUTHOR]

The effects of the parasitic gate capacitance and gate resistance (Rg) on the radiofrequency (RF) performance are investigated in LG = 0.15 μm GaN high-electron-mobility transistors with T-gate head size ranging from 0.83 to 1.08 μm. When the device characteristics are compared, the difference in DC characteristics is negligible. The RF performance in terms of the current-gain cut-off frequency (fT) and maximum oscillation frequency (fmax) sub-stantially depend on the T-gate head size. For clarifying the T-gate head size dependence, small-signal modeling is conducted to extract the parasitic gate capacitance and Rg. When the T-gate head size is reduced from 1.08 to 0.83 μm, Rg increases by 82%, while fT and fmax improve by 27% and 26%, respectively, because the parasitic gate–source and gate–drain capacitances reduce by 19% and 43%, respectively. Therefore, minimizing the parasitic gate capacitance is more effective that reducing Rg in our transistor design and fabrication, leading to improved RF performance when reducing the T-gate head size.

In this paper, we report DC and RF analysis of a T‐gate AlN/β‐Ga2O3 high electron mobility transistors (HEMTs) by optimizing the gate‐drain distance (LGD) and two T‐gate dimensions given by the—head‐length (LHL) and the foot‐length (LFL). A two‐dimensional (2‐D) physics‐based device simulator attuned with experimental results is used to perform the analysis. The AlN/β‐Ga2O3 HEMT achieves a high two‐dimensional electron gas (2DEG) density of ~3 × 1013 cm−2, which is attributed to large spontaneous as well as piezoelectric polarization components of the 10 nm AlN thick barrier layer. 2DEG density is also numerically validated using widely used polarization model for III nitrides. It is demonstrated that a highly scaled, both lateral and vertical, device with optimized T‐gate dimensions achieves higher blocking voltage (VBR), low on‐resistance (RON), higher cut‐off frequency (fT) and higher maximum oscillation frequency (fMAX), simultaneously. Consequently, AlN/β‐Ga2O3 HEMT achieves a low specific‐on resistance (RON,sp) of 0.1 mΩ cm2 and an off‐state breakdown voltage of 904 V, which corresponds to the record power figure‐of‐merit (PFoM) of ~8172 MW/cm2. Furthermore, fT of 73 GHz and fMAX of 142 GHz are estimated. These results—low power conduction loss along with higher blocking voltage, and superior RF parameters show the potential of the analyzed device T‐gate AlN/β‐Ga2O3 HEMT for high‐power switching and RF applications. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive investigation into the DC analog and AC microwave performance of a state-of-the-art T-gate double barrier AlGaN/AlInGaN/GaN MOSHEMT (Metal Oxide Semiconductor High Electron Mobility Transistor) implemented on a 4H-SiC substrate. The study involves meticulous numerical simulations and an extensive comparison with a single barrier design, utilizing the TCAD-Silvaco software. The observed disparity in performance can be attributed to the utilization of double barrier technology, which enhances electron confinement and current density by augmenting the polarization-induced charge during high-frequency operations. Remarkably, when compared to the single barrier design, the double barrier MOSHEMT exhibits a notable 15% increase in drain current, a 5% increase in transconductance, and an elevated breakdown voltage (VBR) of 140 V in E-mode operation. Furthermore, the radio frequency analysis of the double barrier device showcases exceptional performance, setting new records with a maximum oscillation frequency (fmax) of 1.148 THz and a gain cutoff frequency (ft) of 891 GHz. These impressive results obtained through deck-simulation affirm the immense potential of the proposed double barrier AlGaN/AlInGaN/GaN MOSHEMT for future applications in high-power and terahertz frequency domains.

The influence of double deck T-gate on LG = 0.2 μm AlN/GaN/AlGaN HEMT is analysed in this paper. The T-gate supported with Silicon Nitride provides a tremendous mechanical reliability. It drops off the crest electric-field at gate edges and postponing the breakdown voltage of a device. A 0.2-μm double deck T-gate HEMT on Silicon Carbide substrate offer fMAX of 107 Giga Hertz, fT of 60 Giga Hertz and the breakdown voltage of 136 Volts. Furthermore, it produces the maximum-transconductance and drain-current of 0.187 Siemens/mm and 0.41 Ampere/mm respectively. In addition, the lateral electric-field noticed at gate-edge shows 2.1 × 106 Volts/cm. Besides, the double deck T-gate AlN/GaN HEMT achieves a 45% increment in breakdown voltage compared to traditional GaN-HEMT device. Moreover, it reveals a remarkable Johnson figure-of-merit of 7.9 Tera Hertz Volt. Therefore, the double deck T-gate on AlN/GaN/AlGaN HEMT is the superlative device for 60 GHz V-band satellite application. [ABSTRACT FROM AUTHOR]

To increase the radio-frequency (RF) performance of AlGaN/GaN-based fin-type high electron mobility transistors (HEMTs), a novel T-gate process was developed and applied to fabricate a device with high RF performance. In a single lithography process, the applied T-gate process shows a technique for forming a T-gate using the reactivity difference of several photoresists. The fabricated device has a steep fin width (Wfin) of 130 nm, a fin height (Hfin) of 250 nm, and a gate length (LG) of 190 nm. The device exhibits a low leakage current (Ioff) of 6.6 × 10-10 A/mm and a high Ion/Ioff current ratio of 4.7 × 108. Moreover, the fabricated device achieved a high cut-off frequency (fT) of 9.7 GHz and a very high maximum oscillation frequency (fmax) of 27.8 GHz. The fmax value of the proposed device is 138% higher than that of GaN-based fin-type HEMTs without T-gate.

In a high electron mobility transistor (HEMT), the density of the two-dimensional electron gas (2DEG) channel is modulated by the application of a bias to a Schottky metal gate. These devices are depletion mode (D-mode), which means that a negative bias must be applied to the gate to deplete the electron channel and turn. The most challenging aspect in the present research activity on based-GaN devices is the development of a reliable way to achieve an enhancement-mode (E-mode) HEMT. Enhancement-mode GaN HEMTs would offer a simplified circuitry by eliminating the negative power supply. In this work, the aim is to investigate the different techniques which can influence the threshold voltage and shift it to a positive value. A novel E-mode metal-insulator-semiconductor (MIS) AlInN/GaN HEMT with an Au-T-gate has been investigated. The impacts of window-recess and deep-recess have been discussed, it was found that for dp=28 nm and wn=1.8 µm the threshold voltage achieves 0.7 V and the transconductance (Gm) peak value of 523 mS at Vgs=3.5 V. The drain current characteristic has been demonstrated. [ABSTRACT FROM AUTHOR]

A unique approach for fabricating poly-Si thin-film transistors (TFTs) with self-aligned T-shaped gate (T-gate) structure is reported. A counter-doped poly-Si process comprises an in-situ doped ${n}^{+}$ poly-Si deposition followed by a subsequentshallow implantation of BF $_{{2}}^{+}$. Both high etching isotropy in ${n}^{+}$ poly-Si and high etching selectivity between ${n}^{+}$ poly-Si and B-doped poly-Si in a Cl2-based plasma process are the key enablers for the fabrication of our T-gate structures. Thanks to good control in the shape and deformation of our T-gate structure, sidewall air-gap spacers in combination with self-aligned Ni silicided gate and source/drain were established. High-performance sub-micron poly-Si TFTs are evidenced by superior transfer characteristics measured on TFTs with effective gate length of $0.15~\mu \text{m}$. The unique T-gate structure provides an effective way for possible production of poly-Si radio-frequency TFTs viable for emerging new applications. [ABSTRACT FROM AUTHOR]

A 55-nm T-gate high-electron-mobility transistor was fabricated with a quaternary barrier AlGa(In)N/AlN/GaN heterostructure grown on a highly resistive Si substrate. The device shows a maximum current density of 1.25 A/mm, a peak extrinsic dc transconductance of 420 mS/mm, and the cutoff frequencies fT/f\text {max} of 145/220 GHz, which gives a record high value of ( fT\cdot f\text {max}{)}^{1/2} = 178 GHz among the reported GaN-on-Si ratio frequency devices. The Al-rich quaternary barrier featured an incorporation of little indium, which yet significantly improved the crystalline quality, resulting in a record low gate leakage below 10−5 A/mm and a high I \mathrm{\scriptscriptstyle ON}/I \mathrm{\scriptscriptstyle OFF} ratio of 1.78\times 10^5 . [ABSTRACT FROM AUTHOR]

The impact of the stem height of T-gate electrodes on the parasitic gate delay time in InGaAs high electron mobility transistors (HEMTs) is studied. Since T-gates with higher stem height make the parasitic gate capacitance smaller, the higher stem height is expected to minimize the parasitic gate delay. However, a systematic study using the devices with different stem height of T-gates reveals that the parasitic gate delay time decreases with the parasitic gate capacitance only at a drain voltage around the knee voltage and it becomes less sensitive to the parasitic capacitance by the T-gate when the device is operated in the deep saturation region at high drain bias voltage. This result suggests a design strategy for T-gate electrodes so that the tradeoff between the gate resistance and gate capacitance must be considered seriously in the devices for low-voltage applications, while one has more flexibility to use the T-gate electrode with a large head in the devices for high-voltage applications. [ABSTRACT FROM AUTHOR]

The effects of fringing capacitances on the high-frequency performance of T-gate GaN high-electron mobility transistors (HEMTs) are investigated. Delay time components have been analyzed for gate-recessed InAlN/GaN HEMTs with a total gate length of 40 nm and fT/f\max of 225/250 GHz. It is found that the gate extrinsic capacitance contributes significantly to the parasitic delay—approximately 50% of the total delay in these highly scaled devices. The gate extrinsic capacitance comprises two components: 1) parallel plate capacitances between the T-gate and the surrounding electrodes and 2) the fringing capacitance between the gate stem and the access regions. Detailed study of the gate electrostatics reveals that the later, the fringing capacitance between the T-gate stem and the device access region, ultimately determines the lower limit of the extrinsic capacitance Cext; this minimum Cext can be realized experimentally using a large gate stem height (>200~nm) and employing low-k passivation dielectric. Since the corresponding parasitic delay can be expressed as Cext/gm,{\rm int}, this paper also highlights the importance of maximizing gm,int in ultrascaled HEMTs by adopting strategies to enhance carrier velocity. [ABSTRACT FROM AUTHOR]

In this paper, a generalized analysis of recessed double-gate high-electron-mobility transistor for different gate geometries (T-gate, IL-gate, \Gamma-gate, etc.) to realize higher breakdown is carried out. The effect of gate geometries on breakdown voltage is studied through potential and electric field profile. The drain current, transconductance, intrinsic gain, capacitances, and RF performances are also studied. The analysis shows that the incorporation of these geometries not only leads to higher breakdown but also enhances the transcapacitance of the devices, which affect the device RF performance. [ABSTRACT FROM PUBLISHER]

Abstract: The operation at frequencies above 100GHz of electronic devices like transistors has been achieved both by using high electron mobility III–V semiconductor materials or heterostructures and by implementing fabrication techniques which strongly reduce parasitic capacitances between the device terminals, without increasing series resistances. The technology has been applied on different GaN high electron mobility transistor epiwafers, and the devices performances analyzed under their DC and RF characteristics, outlining that further semiconductor material optimization is mandatory to fully benefit the sub ¼ micron Gate length for very high frequency operation advantage. [Copyright &y& Elsevier]

The physics, technology, and modeling of complementary asymmetric MOSFETs are reviewed and illustrated with statistically representative silicon data from a recent manufacturing implementation, in which the transistors for the secondary power supply voltage are offered in asymmetric and symmetric constructions. The in-depth analysis of the device physics of asymmetric transistors provides new insights into their physical operation and into the operation of transistors using halo implants in general. The variability, matching, and noise implications of using halo implants are also analyzed, concluding that both asymmetric and symmetric devices need to be offered for uncompromised circuit design. The challenges associated with the compact modeling the asymmetric transistors are also reviewed and illustrated. The preferred manufacturing implementation uses retrograde wells with no dopant fillers at the surface, while avoiding the drain-to-source punch-through by source-side-only halo implants. In addition to the known switching speed and maximum voltage gain advantages of the asymmetric transistors, this particular device architecture offers superior hot-carrier reliability and transistor design flexibility. The availability of retrograde wells enables construction of high-reliability complementary extended-drain MOSFETs for a third higher power supply voltage. [ABSTRACT FROM PUBLISHER]

A new e-beam lithography method using stepping exposure was proposed to obtain a floating Y-gate for high electron mobility transistor (HEMT) application. The resist thickness shows good linearity with the exposure dose. An AlGaN/GaN HEMT device with 120 nm gate length was fabricated by this method. The device shows improved breakdown and frequency performance (fmax∙BV increased by 55%) compared to the traditional T-gate device. [Display omitted] • The stepping litho method shows a good linearity with exposure dose. • The Y-gate shows about 23° of dip angle. • The Y-gate improves the f t /f max and the BV of device at the same time. • The f max ∙BV of Y-gate device is improved 55% compared with T-gate device. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents two separate methods for the fabrication of 10nm footprint T-gates using a two-step gate process. We examine the limits of lithographic and pattern transfer processes using the exposure of ZEP520A resist by electron beam lithography, suitable development processes and subsequent pattern transfer by reactive ion etching of a silicon nitride layer on III–V substrates. In a second process, the dimensions of a larger initial feature are reduced using the deposition and etching of conformal silicon nitride. Both processes have yielded metallised gates with a footprint as small as 10nm and are suitable for incorporation into a HEMT process flow. [Copyright &y& Elsevier]

Abstract: In order to achieve superior RF performance, short gate length is required for the compound semiconductor field effect transistors, but the limitation in lithography for submicrometer gate lengths leads to the formation of various metal–insulator geometries like T-gate [Sandeep R. Bahl, Jesus A. del Alamo, Physics of breakdown in InAlAs/ n+-InGaAs heterostructure field-effect transistors, IEEE Trans. Electron Devices 41 (12) (1994) 2268–2275]. These geometries are the combination of various Metal-Semiconductor (MS)/Metal–Air-Semiconductor (MAS) contacts. Moreover, field plates [S. Karmalkar, M.S. Shur, G. Simin, M. Asif Khan, Field-plate engineering for HFETs, IEEE Trans. Electron Devices 52 (2005) 2534–2540] are also being fabricated these days, mainly at the drain end (-gate) having Metal–Insulator-Semiconductor (MIS) instead of MAS contact with the intention of increasing the breakdown voltage of the device. To realize the effect of upper gate electrode in the T-gate structure and field plates, an analytical model has been proposed in the present article by dividing the whole structure into MS/MIS contact regions, applying current continuity among them and solving iteratively. The model proposed for Metal–Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) [R. Gupta, S.K. Aggarwal, M. Gupta, R.S. Gupta, Analytical model for metal insulator semiconductor high electron mobility transistor (MISHEMT) for its high frequency and high power applications, J. Semicond. Technol. Sci. 6 (3) (2006) 189–198], is equally applicable to High Electron Mobility Transistors (HEMT) and has been used to formulate this model. In this paper, various structures and geometries have been compared to anticipate the need of T-gate modeling. The effect of MIS contacts has been implemented as parasitic resistance and capacitance and has also been studied to control the middle conventional gate as in dual gate technology by applying separate voltages across it. The results obtained using the proposed analytical scheme has been compared with simulated and experimental results, to prove the validity of our model. [Copyright &y& Elsevier]

GaAs-based metamorphic HEMTs (MHEMT) consist of GaAs substrates and InP-based epitaxial structure, and have the advantages of both lnP HEMT's excellent performances and GaAs-based HEMT's mature processes. GaAs-based MHEMT5 were applied to millimeter-wave low-noise, high-power applications and systems. The current gain cut-off frequency (f[subT]) and the maximum oscillation frequency (f[submax]) are important performance parameter of GaAs-based MHEMTs, and they are limited by the gate-length mainly. Electron beam lithography is one of the lithography technologies which can be used to realize the deep submicron gate-length. The 200 nm gate-length GaAs-based MHEMTs have been fabricated by electron beam lithography. In order to reduce the parasite gate capacitance and gate resistance, a trilayer resist structure was used to pattern the T-gate resist profile. Excellent DC, high frequency and power performances have been obtained. F[subT] and f[submax] are 105 GHz, 70 GHz respectively. The research is very helpful to obtain higher performance GaAs-based MHEMTs. [ABSTRACT FROM AUTHOR]

Abstract: In this paper analytical modeling for a novel three region gate dielectric engineered AlGaN/GaN Metal Insulator Semiconductor heterostructure field effect transistor (MISHFET) device architecture is presented which shows high transconductance and enhanced cut-off frequency at quarter micron gate lengths. Using a three region analysis along the horizontal direction in the gate dielectric region the expressions for transconductance and cut-off frequency of the device are obtained. It has been observed that using these gate dielectric schemes, improvements on device performance are observed over conventional MISHFET structures. Relative comparison of T and Γ-gate shaped structures is done with uniform gate dielectric profile and enhancement in microwave performance is observed. The proposed model is capable of modeling electrical characteristics like drain current, output conductance and threshold voltage of various other existent structures like uniform gate dielectric MISHFETs, HFETs and T-gate HFETs. The present model is based on closed form expression and does not involve any fitting parameter. The results obtained are compared with experimental data and show excellent agreement, thereby proving the validity of the model. [Copyright &y& Elsevier]

Abstract: This paper reports a new method for the fabrication of sub-25nm T-gates for high electron mobility transistors (HEMTs). For robust fabrication, it may be advantageous to employ a two-step process where the gate foot and head can be separately defined. The new process uses ZEP520A electron beam resist as a mask for SF6-based anisotropic reactive ion etching of ICP-deposited silicon nitride to define the gate foot. The gate head structure, defined in PMMA/LOR/UVIII, is then lithographically aligned to the gate foot. All electron beam lithography was performed using a Vistec VB6 UHR EWF tool. The design flexibility, mechanical stability, gate resistance and plasma-induced damage of this new method and its suitability for integration in a HEMT process flow are evaluated in this paper. This work has led to the high-yield fabrication of robust 22nm T-gates. [Copyright &y& Elsevier]

Recent advances in electron beam lithography have made possible the fabrication of pseudomorphic high electron mobility transistors (PHEMTs) with gate length well in the nanometer regime. This gate processes mostly require thin dielectric support layers in order to prevent collapse of gate head due to poor mechanical reliability in the narrow gate foot. However, this layer is a major cause for parasitic capacitance. In this paper, we have demonstrated the fabrication of a 70 nm foot print of the T-shaped gate by using a positive resist ZEP520/P(MMA-MAA)/PMMA trilayer by double exposure method without a thin dielectric supporting layer on the substrate. [Copyright &y& Elsevier]

This paper describes the use of a unique combination of an environmentally stable chemically amplified photoresist (UV113, Shipley) and a copolymer of methyl styrene and chloromethyl acrylate P(MS/CMA) resist (ZEP520, Zeon), without any additional intermediate layers, in the fabrication of high-resolution T-gates and Γ-gates. The two resists used are innocuous to each other during the designed process flow, providing flexibility, high resolution, greater throughput and ease of use. [Copyright &y& Elsevier]

This paper reports a simple route to fabricating T-gate like structures with footprint of 40 nm using a copper electroplating process and a single electron beam lithography step without the need for lift-off. To our knowledge, these are the smallest such structures demonstrated using this approach which could also be implemented straightforwardly using conventional stepper or nanoimprint lithography for low cost, high volume silicon compatible manufacture. [ABSTRACT FROM AUTHOR]

The impact of graded Al 0. 05 Ga 0. 95 N sub-channel over the DC characteristics of AlGaN/GaN/AlInN Metal Oxide Semiconductor-High Electron Mobility Transistor (MOS-HEMT) has been investigated here. By placing a field plate over the gate region and forming a T-gated structure, the breakdown characteristics are examined using Sentaurus Technology Computer-Aided Design (TCAD) simulation tool. An analytical study is carried out into the evaluation of various device parameters like drain current, transconductance and threshold voltage. RF parameters like cut-off frequency and gain has also been examined. Various physical models such as hydrodynamic, thermodynamic, piezoelectric polarization, impact ionization models are considered. HfO 2 as an oxide layer directly influences the charge confinement near the Two-Dimensional Electron Gas (2DEG), thereby causing a positive shift in the threshold voltage of the device. T-gated formation of the gate helped in enhancing the breakdown voltage of the device to nearly 750 V. A maximum current drive of 1.79 A/mm mm was obtained for the proposed device, nearly 24% improvement from the conventional Composite-channel (CC) HEMT. The current outcomes and the produced frequency characteristics determines the linearity enhancement occurred in the device, caused due to the graded AlGaN sub-channel below the GaN channel layer. The trade-off between specific on-resistance and breakdown voltage is well preserved by employing a T-gated structure with low normal gate length. The outcomes prove the device to be a prime contender for high power switching as well as large signal applications. • The impact of graded AlGaN sub-channel over the DC characteristics of AlGaN/GaN/AlInN MOS-HEMT has been investigated here. • HfO 2 dielectric directly influences the charge confinement near 2DEG, causing a positive shift in the threshold voltage. • T-gated formation of the gate helped in enhancing the breakdown voltage of the device to nearly 750 V. • A 24% enhancement in current drive is observed when the device is brought in comparison with a conventional CC HEMT. [ABSTRACT FROM AUTHOR]

Depletion-mode quaternary barrier \In0.13\Al0.83\break \Ga0.04\N high-electron-mobility transistors (HEMTs) with regrown ohmic contacts and T-gates on a SiC substrate have been fabricated. Devices with 40-nm-long footprints show a maximum output current density of 1.8 A/mm, an extrinsic dc transconductance of 770 mS/mm, and cutoff frequencies fT/f\max of 230/300 GHz at the same bias, which give a record-high value of \surd fT \cdot f\max = \263\ \GHz among all reported InAl(Ga)N barrier HEMTs. The device speed shows good scalability with gate length despite the onset of short-channel effects due to the lack of a back barrier. An effective electron velocity of \1.36 \times \10^7\ \cm/s, which is comparable with that in the state-of-the-art deeply scaled AlN/GaN HEMTs, has been extracted from the gate-length dependence of fT for gate lengths from 100 to 40 nm. [ABSTRACT FROM PUBLISHER]

High performance 150-nm gate-length metamorphic AlInAs/GaInAs high electron mobility transistors (mHEMTs) with very good device performance have been successfully fabricated. A T-shaped gate is fabricated by using a combined technique of optical and e-beam photolithography, which is beneficial to decreasing parasitic capacitance and parasitic resistance of the gate. The ohmic contact resistance R is as low as 0.03 Ω·mm when using a novel ohmic contact metal system (Ni/Ge/Ti/Au). The devices exhibit excellent DC and RF performance. A peak extrinsic transconductance of 775 mS/mm and a maximum drain current density of 720 mA/mm are achieved. The unity current gain cut-off frequency ( f) and the maximum oscillation frequency ( f) are 188.4 and 250 GHz, respectively. [ABSTRACT FROM AUTHOR]

Abstract: In this paper we present design, fabrication and characterization of Schottky terahertz diodes. The diode is based on a Ti/n-GaAs junction with very low junction capacitance. T-gate technology, based on trilayer of electronic resists and electron-beam lithography, and air-bridge technique have been used to obtain Schottky diodes with cutoff frequency in the THz range. The device fabrication process is fully planar and suitable for integration in monolithic arrays for active spectroscopic imaging. [Copyright &y& Elsevier]

A new body-tied (BT) (I-gate) silicon-on-insulator transistor with comparable fT and f\max as those of floating-body transistors and comparable analog performance as those of T-gate BT transistors is demonstrated. The structure is fabricated without process modifications by selectively blocking silicide formation and source/drain implant in a foundry technology. [ABSTRACT FROM AUTHOR]

A V-band push-push GaN monolithic microwave integrated circuit voltage controlled oscillator (VCO) has been realized based on a 0.2 mum T-gate AlGaN/GaN high electron mobility transistor technology with an fT ~ 65 GHz. The GaN VCO delivered an output power of +11 dBm at 53 GHz with an estimated phase noise of -97 dBc/Hz at 1 MHz offset based on on-wafer measurement. To the best of our knowledge, this is the highest frequency VCO ever reported for GaN technology with a high output power at V-band, without using any buffer amplifier. This work demonstrates the potential of applying GaN technology to millimeter wave band, high power, and low phase noise frequency sources applications. [ABSTRACT FROM PUBLISHER]

This letter presents the results of an enhancement mode metamorphic high-electron-mobility transistor device on a GaAs substrate with a 70% indium composition channel. A 35-nm gate length device exhibits a 490-GHz current gain cutoff frequency (fT), a transconductance (g,~) of 2 S/mm, a threshold voltage (V~h) of 0.11 V (enhancement mode) and a low on- resistance of 0.37 Il . mm. These attributes make the device well- suited for millimeter-wave circuit applications. [ABSTRACT FROM AUTHOR]