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A reaction system is a modeling framework for investigating the functioning of the living cell, focused on capturing cause−effect relationships in biochemical environments. Biochemical processes in this framework are seen to interact with each other by producing the ingredients enabling and/or inhibiting other reactions. They can also be influenced by the environment seen as a systematic driver of the processes through the ingredients brought into the cellular environment. In this paper, the first attempt is made to implement reaction systems in the hardware. We first show a tight relation between reaction systems and synchronous digital circuits, generally used for digital electronics design. We describe the algorithms allowing us to translate one model to the other one, while keeping the same behavior and similar size. We also develop a compiler translating a reaction systems description into hardware circuit description using field-programming gate arrays (FPGA) technology, leading to high performance, hardware-based simulations of reaction systems. This work also opens a novel interesting perspective of analyzing the behavior of biological systems using established industrial tools from electronic circuits design.

A reaction system is a modeling framework for investigating the functioning of the living cell, focused on capturing cause-effect relationships in biochemical environments. Biochemical processes in this framework are seen to interact with each other by producing the ingredients enabling and/or inhibiting other reactions. They can also be influenced by the environment seen as a systematic driver of the processes through the ingredients brought into the cellular environment. In this paper, the first attempt is made to implement reaction systems in the hardware. We first show a tight relation between reaction systems and synchronous digital circuits, generally used for digital electronics design. We describe the algorithms allowing us to translate one model to the other one, while keeping the same behavior and similar size. We also develop a compiler translating a reaction systems description into hardware circuit description using field-programming gate arrays (FPGA) technology, leading to high performance, hardware-based simulations of reaction systems. This work also opens a novel interesting perspective of analyzing the behavior of biological systems using established industrial tools from electronic circuits design.

Functional programming techniques have been used to describe synchronous digital circuits since the early 1980s. Here we survey the systems and formal underpinnings that constitute this tradition. We situate these techniques with respect to other formal methods for hardware design and discuss the work yet to be done. [ABSTRACT FROM AUTHOR]

Reaction system (RS) belongs to a type of qualitative computing model inspired by biochemical reactions taking place inside biological cells. It concerns more the interactions and causality among reactions rather than concrete concentrations of chemical entities. Many biochemical processes and models can be represented in the form of reaction systems so that complex relations and ultimate products of a variety of reactions can be revealed qualitatively. The reaction system works in parallel mode. Software simulation of this kind of model may suffer from the penalty of inefficient parallelism for the limited performance of CPU/GPU, especially for the simulation of large-scale models. Considering potential applications of reaction systems in disease diagnoses and in drug developments, hardware implementation of reaction systems provides a better way to accelerate computations involved. In this paper, an FPGA implementation method of a reaction system called RSFIM is proposed. Two small-scale models, i.e., the reaction system of intermediate filaments self-assembly and heat shock response, are implemented on FPGA, achieving a computing speed of 2 × 10 8 steps per second. For large-scale models, the ErbB reaction system is implemented, obtaining a speedup of 7.649 × 10 4 compared with its highest performance GPU simulation so far. The reaction system binary counter, which is a quantitative model, is also implemented by the Boolean explanation of the qualitative character of the reaction system. FPGA implementation of reaction systems opens a novel research line to speed up the simulations of reaction systems and other biological models in the perspective of parallel digital circuits. [ABSTRACT FROM AUTHOR]

Timing errors that are caused by the timing violations of sensitized circuit paths, have emerged as an important threat to the reliability of synchronous digital circuits. To protect circuits from these timing errors, designers typically use a conservative timing margin, which leads to operational inefficiency. Existing adaptive approaches reduce such conservative margins by predicting the timing errors in advance and adjusting the timing margin adaptively. However, these error prediction approaches overlook the impact of input workload (i.e., operands) on path sensitization, thereby resulting in a loss of accuracy. The diversity of input operands leads to complex path sensitization behaviors, making them hard to represent in timing error modeling. In this paper, we propose CLIM, a cross-level workload-aware timing error prediction model for functional units (FUs). CLIM predicts whether there are timing errors in FU at two levels: bit-level and value-level. At the bit level or value level, CLIM predicts each output bit or entire output value as one of two classes: $\lbrace$ timing correct, timing erroneous$\rbrace$ as a function of input workload and clock period, respectively. We apply supervised learning methods to construct CLIM , by using input operands, computation history and circuit toggling as input features, as well as outputs’ timing classes as labels. These training data are collected from gate-level simulations (GLS) of post place-and-route designs in TSMC 45nm process. We evaluate CLIM prediction accuracy for various FUs and compare it with baseline models. On average, CLIM  exhibits 95 percent prediction accuracy at value-level, 97 percent at bit-level, and executes at a rate 173X faster than GLS. We utilize CLIM to analyze the value-level and bit-level reliability of FUs under random and real-world application workloads. At value-level, CLIM -based reliability estimation is within 2.8 percent deviation on average of detailed GLS ground truth. At bit-level, we introduce the concept of bit-level reliability specification of error-tolerant applications and compare this with the CLIM-based bit-level reliability estimation. By comparison, CLIM will classify the application quality into two classes: $\lbrace$ acceptable, non-acceptable$\rbrace$ . On average, 97 percent application quality classification is consistent with GLS ground truth. [ABSTRACT FROM AUTHOR]

This paper describes a circuit called dynamic and applicative measurement of single events in logic (DAMSEL), which can individually measure the impact of single event upsets and single-event transients (SETs) in realistic, synchronous digital circuits. Heavy-ion and pulsed laser test results are presented. Both a simple digital and an analog simulation methodology are demonstrated to provide similar cross sections to those observed during the tests. Overall, the DAMSEL structure has many advantages over current circuits used for measuring SETs, including the ease with which test results can be extrapolated to real designs. [ABSTRACT FROM PUBLISHER]

This article addresses the growing need in resource-constrained edge computing scenarios for energy-efficient convolutional neural network (CNN) accelerators on mobile Field-Programmable Gate Array (FPGA) systems. In particular, we concentrate on register transfer level (RTL) design flow optimization to improve programming speed and power efficiency. We present a re-configurable accelerator design optimized for CNN-based object-detection applications, especially suitable for mobile FPGA platforms like the Xilinx PYNQ-Z2. By not only optimizing the MAC module using Enhanced clock gating (ECG), the accelerator can also use low-power techniques such as Local explicit clock gating (LECG) and Local explicit clock enable (LECE) in memory modules to efficiently minimize data access and memory utilization. The evaluation using ResNet-20 trained on the CIFAR-10 dataset demonstrated significant improvements in power efficiency consumption (up to 22%) and performance. The findings highlight the importance of using different optimization techniques across multiple hardware modules to achieve better results in real-world applications. [ABSTRACT FROM AUTHOR]

Brain-inspired computing, drawing inspiration from the fundamental structure and information-processing mechanisms of the human brain, has gained significant momentum in recent years. It has emerged as a research paradigm centered on brain–computer dual-driven and multi-network integration. One noteworthy instance of this paradigm is the hybrid neural network (HNN), which integrates computer-science-oriented artificial neural networks (ANNs) with neuroscience-oriented spiking neural networks (SNNs). HNNs exhibit distinct advantages in various intelligent tasks, including perception, cognition and learning. This paper presents a comprehensive review of HNNs with an emphasis on their origin, concepts, biological perspective, construction framework and supporting systems. Furthermore, insights and suggestions for potential research directions are provided aiming to propel the advancement of the HNN paradigm. [ABSTRACT FROM AUTHOR]

Keyword spotting is an important part of modern speech recognition pipelines. Typical contemporary keyword-spotting systems are based on Mel-Frequency Cepstral Coefficient (MFCC) audio features, which are relatively complex to compute. Considering the always-on nature of many keyword-spotting systems, it is prudent to optimize this part of the detection pipeline. We explore the simplifications of the MFCC audio features and derive a simplified version that can be more easily used in embedded applications. Additionally, we implement a hardware generator that generates an appropriate hardware pipeline for the simplified audio feature extraction. Using Chisel4ml framework, we integrate hardware generators into Python-based Keras framework, which facilitates the training process of the machine learning models using our simplified audio features. [ABSTRACT FROM AUTHOR]

The clock is one of the most critical signals in any synchronous system. As CMOS technology has scaled, supply voltages have dropped chip power consumption has increased and the effects of jitter due to clock frequency increase have become critical and jitter budget has become tighter. This article describes design and development of low-cost mixed-signal programmable jitter generator with high resolution. The digital technique is used for coarse-grain and an analogue technique for fine-grain clock phase shifting. Its structure allows injection of various random and deterministic jitter components in a controllable and programmable fashion. Each jitter component can be switched on or off. The jitter generator can be used in jitter tolerance test and jitter transfer function measurement of high-speed synchronous digital circuits. At operating system clock frequency of 220 MHz, a jitter with 4 ps resolution can be injected. [ABSTRACT FROM AUTHOR]