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Hybrid switched-capacitor converters (HSCCs) have gained attention due to their promising efficiency and power density compared to traditional inductor- or capacitor-based converters. However, with the recent development of various HSCC topologies, it has become increasingly challenging to choose the most suitable one for a particular application. To address this challenge, this paper proposes a benchmarking framework that enables direct comparison of direct HSCC topologies based on various performance metrics such as passives volume and bandwidth. The proposed approach, which compares all topologies at the same efficiency and output voltage ripple, provides guidelines for topology selection and optimization, ultimately contributing to wider industrial adoption and exploration of new topologies. Downloadable open-access code is also provided to recreate presented results and expand to other topologies not discussed in the paper.

The aim of this work is the design of a current control by means of state feedback, based on linear matrix inequalities (LMI), and it is applied in a DC-DC coupled inductors Buck-Boost modular converter, which has been widely used in distributed generation systems with renewable energy sources. This method considers constraints on the location of poles defined in the complex plane called d-stability. The closed-loop control system is implemented in Matlab® Simulink and validated under different test scenarios, where better dynamic performance is obtained, its operating range is extended, with shorter settling times and a better time-response, in contrast with the classical PI control technique. [ABSTRACT FROM AUTHOR]

Abstract This study proposes a comprehensive analysis of a novel non‐isolated step‐up converter with continuous input current and common ground. The proposed topology provides high voltage gain besides insignificant voltage and current stress across switches and diodes. Consequently, using switches and diodes with low current and voltage withstanding is achievable, leading to high converter efficiency and cost reduction. The voltage and current stress besides steady‐state and efficiency analysis are surveyed. Moreover, the converter's non‐ideal voltage gain analysis employing different components is discussed and compared with recently suggested converters. Additionally, the component losses, efficiency, normalized voltage, and current stresses of the studied converters are collected in tables to simplify the comparison between different topologies. Finally, a 100 W prototype converter is implemented to confirm theoretical performance, and the results are investigated in detail.

This study proposes a comprehensive analysis of a novel non‐isolated step‐up converter with continuous input current and common ground. The proposed topology provides high voltage gain besides insignificant voltage and current stress across switches and diodes. Consequently, using switches and diodes with low current and voltage withstanding is achievable, leading to high converter efficiency and cost reduction. The voltage and current stress besides steady‐state and efficiency analysis are surveyed. Moreover, the converter's non‐ideal voltage gain analysis employing different components is discussed and compared with recently suggested converters. Additionally, the component losses, efficiency, normalized voltage, and current stresses of the studied converters are collected in tables to simplify the comparison between different topologies. Finally, a 100 W prototype converter is implemented to confirm theoretical performance, and the results are investigated in detail. [ABSTRACT FROM AUTHOR]

This article proposes a novel control for the multiple-input, single-inductor, multiple-output dc–dc converters. It is digitally and discretely implemented, which can have an outstanding performance in low-power applications so that at the power of 10 mW, it has an efficiency of 92.5%. Conventionally, in this power range, an attempt is made to take advantage of an analog design that is flexible. Thus, a fully programmable (software designed) converter with digital design using a microcontroller is in great demand. This converter design basis is to deploy the microcontroller's central processing unit (CPU) as little as possible. Also, it only turns on the CPU when necessary to be employed in low-power, portable systems, e.g., energy-harvesting technologies. Therefore, construction costs are significantly reduced. Depending on the energy level of the inputs, they can simultaneously be utilized to charge the outputs. This article uses stability analysis, time-multiplexing control method, and variable-frequency pulsewidth modulation in the proposed control design. Each output can be charged with different frequencies according to its load, and the maximum switching frequency is equal to 10 kHz. Also, the proposed technique for zero-current switching has been digitally implemented; it can be utilized to determine the optimal value of the inductor discharge duty cycle based on the inductor's left-side voltage. Comparative simulations and experimental results reveal the superiority and practicality of the proposed approach. [ABSTRACT FROM AUTHOR]

This brief provides a detailed loop gain and stability analysis of hybrid power amplifier supply modulators. Design considerations, including the relations between the voltage and current loops, the rationale of current loop compensation to ensure stability and improve bandwidth, and the impacts of current loop on the overall system stability and efficiency, are studied with combined system loop gain modeled mathematically. The theoretical analysis is proven by simulation results. Based on the study, a hybrid supply modulator has been designed and fabricated in 65-nm CMOS. In measurements, stable voltage and current closed-loop operations have been verified, with a peak efficiency of 85% when tracking a 20-MHz LTE envelope. [ABSTRACT FROM AUTHOR]

This paper presents a discrete time simulation procedure of switched mode power supply (SWPS) power stages using Euler's forward method for numerical integration. Usually, the simulation of SMPS power stages is carried out in PSPICE alike circuit simulators, but sometimes this is inconvenient and slow. The proposed simulation method may be used for educational purposes, whenever a quick and easy illustration of the SMPSs is desired. Furthermore, it can be deployed in the development of digital control algorithm, as the method may be implemented in logic simulators (event driven or delta time simulators). This discrete time modeling procedure can be implemented in any number crunching environment (Matlab, Octave, NumPy, etc.), in a logic (event-driven) simulator or in a simple spreadsheet. The procedure consists in (i) writing the ordinary differential equations (ODEs) of the modelled power stage, (ii) solving the ODE using numerical methods. Several power stage models were developed and simulated: (i) an ideal buck-boost was simulated in MATLAB, (ii) a boost converter simulated in a spreadsheet and (iii) an ideal synchronous buck converter was described in a hardware description language, VHDL. The numerical error between discrete time and PSCIPE simulation results are negligible. [ABSTRACT FROM AUTHOR]

This brief provides a brief tutorial on designing a high efficiency envelope-tracking supply modulator with recent techniques. Design challenges for 5G communication applications are given. Detailed techniques covering topology derivation, multi-level and fast-speed switching converter design considerations, voltage step-up and –down function implementations, linear amplifier bandwidth improvements and measurement setup are discussed, providing design guidelines and considerations. [ABSTRACT FROM AUTHOR]

This article presents a novel control strategy for a dual active bridge series resonant converter. The strategy seeks to ensure the stability of the converter over its entire dynamic range while enhances the transient response. Both properties allow the use of the converter in new applications, where fast dynamics are required, surpassing the performance of existing feedback loops. Starting from the generalized averaged model of the converter, we propose a nonlinear control strategy by means of Lyapunov's stability theory. After that, we derive a series of modifications in order to implement the strategy in a microcontroller or a DSP, including a sensorless method to tackle the lack of measurements of certain variables and an adaptive control law to deal with uncertain parameters in the model. The strategy is evaluated in simulations and experiments, employing a commercial converter, and comparing the results with other control policies. [ABSTRACT FROM AUTHOR]

Series-connected insulated gate bipolar transistors (IGBTs) are vastly adopted in high-voltage/power converters. It has been shown in prior researches that shaping the switching element transient voltage to an “S”-shape profile decreases EMI considerably. This article proposes a series-stacked IGBT switch (SSIS) with pulse shaping capability. According to this feature, the voltage of the SSIS has a Gaussian profile in the rising time interval. The method works based on the specific delayed operation of the series-connected IGBTs. In this approach, all IGBTs are turned on/off as fast as possible. Hence, the EMI reduction is not obtained at the expense of the switching power loss increment. Moreover, the power loss relevant to the delayed operation of the IGBTs transfers to the main dc bus. Thus, the overall efficiency is not affected by the proposed approach. In order to validate the proposed approach, PSPICE simulations as well as the experimental results are provided. [ABSTRACT FROM AUTHOR]

A wireless power transfer (WPT) system in domino structure is a high-order system with a number of state variables. Thus, the controller design for the power electronic converters has been very challenging. With the aid of phasor transformation, a simple representation of the system could be derived. In this article, the procedure of creating a dynamic model for a WPT system in domino structure is introduced. The model allows the estimation of receiver-side operating conditions from the transmitter. Using the phasor transformation technique, the varying phasors of the resonant voltages and currents in the WPT system are taken as state variables, rather than their rapidly changing real-time values. Compared to traditional analytical methods, the lower computational cost is significantly benefited from the system order reduction. The dynamic model is validated by experimental measurement results. The results show good accuracy of input and output voltage and current prediction. The dynamic model provides a deep insight into the system behavior. The dynamic model could play an important role in the future development of control algorithms to further advance the performance of the WPT system. [ABSTRACT FROM AUTHOR]

In this article, a novel single-switch, high step-up dc–dc converter based on three-winding coupled inductor and voltage multiplier circuit (VMC) is proposed. And on this basis, pump capacitor unit (PCU) is integrated to achieve a very high voltage gain. The converter makes full use of the advantages of three-winding coupled inductor, skillfully combines it with the VMC, and integrates the PCU that can be used in superposition to further improve the voltage gain. The voltage stress of the switch is reduced by using a passive clamping circuit to recycle the leakage energy of the coupled inductor. The operating principle and steady-state analysis of the presented converter in continuous conduction mode are introduced in detail. Moreover, the comparative analysis shows that under the same conditions, the proposed converter has higher voltage gain and lower voltage stress than others. Several advantages include high voltage gain, low voltage stress, low turns ratio of coupled inductor, and high conversion efficiency, make the proposed converter very suitable for new energy generation applications, such as photovoltaic systems. Finally, the feasibility of the proposed converter and the correctness of theoretical analysis are verified by a 500-W prototype at 50 kHz switching frequency. [ABSTRACT FROM AUTHOR]

High voltage generation, is one of the main applications of the Cockcroft-Walton voltage multiplier (CWVM), however recently this structure is investigated to be used for high step-up DC-DC applications. This paper discusses dynamic behaviour and small-signal modelling of a CWVM based DC-DC converter and investigates how switching strategy can affect the dynamic performance of the converter. This study firstly presents, a new switching method, the steady-state relations are derived and compared to the conventional switching strategy, which shows that the proposed method equilibrates the voltage and current stress of the switches and decreases the current ripple of the input inductor. Then, the converter is dynamically modelled and analyzed using the pole-zero map. The analysis shows that the proposed switching strategy improves the dynamic behaviour of the converter. The effect of the passive elements on dynamic performance is also discussed. Experimental results are presented for a 160 W prototype to validate the evaluated performance and the dynamic analysis.

Summary: Switching DC/DC converters are closed loop systems requiring controllers to stabilize and optimize their performance. A practical method for designing these controllers through pole/zero placement adjustment is the K‐factor method. This method can easily be implemented using RC op‐amp circuits given a target crossover frequency and phase margin. Here, we extend this method to the fractional‐order domain and present detailed analytical formulae to calculate all component values in two types of op‐amp‐based compensators. Mathematical analysis, circuit simulation, and experimental results all correlate very well. [ABSTRACT FROM AUTHOR]

Switching regulators improve power efficiency and reduce cost of electronic devices. Continued advances in the performance of components have outpaced the models used for their analysis and design. Physical limits of the parts and their arrangement introduce nonideal parasitic effects that can no longer be ignored. This article introduces an extensible frequency domain model of buck regulators that can capture parasitic effects of arbitrary complexity. Such models are derived for both continuous and discontinuous conduction modes of peak current mode controllers. The proposed models are shown to be accurate when compared to other methods, while having lower computational cost. Numerical optimization is applied to design systems using the increased complexity models. Cost functions are developed, and shown to produce improved designs when compared to existing published examples. Experimental measurement finds the models accurately predict the performance of implemented designs. Additional parasitic elements are added to the model, showing improved fit to measured results, demonstrating the extensibility and accuracy possible. [ABSTRACT FROM AUTHOR]

The method for modeling switching converters plays a key role in real-time simulators. Associate discrete circuit (ADC) modeling technique is a commonly used method for modeling the switching converter. However, the optimal selection of the ADC-based switch model parameters has great importance in the accuracy of the real-time simulator. In this paper, the design of a real-time simulator for a switching power converter has been done, in which a novel method for detecting optimum values of the switch model parameters has been expressed. Particle swarm optimization (PSO) algorithm is used to find these optimum values using state-space analysis of the modeled circuit in the z-domain. The modified nodal analysis (MNA) method solves the real-time model at each simulation time-step. Case studies are a single-phase 5-level Cascaded H-Bridge (CHB), three-phase 9-level CHB inverter, and a Transmission line. Field-programmable gate array (FPGA) has been used as a platform for implementing the real-time simulator. Experimental result of the real-time simulator of the 5-level CHB inverter on a SPARTAN-6 FPGA and its comparison with the result of a prototype of a 5-level CHB inverter confirms not only the performance of the real-time simulator, but also the effectiveness of the proposed method for confirming the real-time simulator accuracy. [ABSTRACT FROM AUTHOR]

This article proposes a supply modulator (SM) that uses high switching frequency gallium-nitride (GaN) devices to achieve a four-phase fast step-down converter for the fast-tracking ability of the envelope tracking (ET). The ET signal is reshaped to generate an average power tracking (APT)-based signal to control the size of GaN switches to further increase light-load efficiency due to reduced switching loss. Moreover, a high-bandwidth and low-loss linear amplifier (LA) is used to supply the power amplifier (PA) to sufficiently provide fast-tracking speed for 5th generation (5G) NR ET. At a power of 3.5 W for 5G mobile phones, the peak efficiency that is tested with NR −130 MHz in the ET mode is as high as 85.7% over a wide load range. [ABSTRACT FROM AUTHOR]

This article presents a dual-frequency (DF) dual-input–dual-output interface based on a reconfigurable switching converter for thermoelectric energy harvesting. The DF operation decouples the rate of energy extraction at the input stage from the rate of energy distribution at the output stage. The interface automatically makes transitions among two energy-harvesting modes and one energy-recycling mode according to the load condition. The low-frequency harvesting together with the high-frequency recycling allows the interface to maintain high efficiency across a broad range of load. A zero-current detection (ZCD) approach based on real-time calculation turns off the power switches instantaneously and accurately to prevent synchronization loss. The interface is fabricated with a 0.13-μm CMOS process. From the measurement results, the input voltage is regulated in the range from 30 to 500 mV with the aid of maximum power point tracking (MPPT) and the output voltage is regulated at 1.2 V. The peak energy harvesting efficiency is 86% with 250-mV input voltage. Higher than 80% efficiency is achieved with 80–500 mV input voltages. The peak energy recycling efficiency is 94% and the power consumption of control circuits is 0.6 μW. [ABSTRACT FROM AUTHOR]

Automotive auxiliary converter empowers the electronic system, the failure of which will affect the system performance. As a critical component in the feedback loop of the converter, real-time health monitoring for optocoupler is of great importance. The degraded optocoupler mainly shows a falling current transfer ratio (CTR). This article proposes an online proactive CTR monitoring method for optocoupler via voltage measurement of critical nodes. The monitored CTR can indicate the health condition of the optocoupler. First, the principle of a boost-LLC converter is analyzed in detail. Then, the influences of degraded CTR on the feedback loop are derived. An online proactive CTR monitoring scheme is introduced. The realization of voltage measurement, signal filtering, wireless communication, and time synchronization are in two independent embedded systems. CTR will be calculated in the local server and be stored in the local database. The proposed method can monitor CTR for both unaged and aged optocouplers. Effects of switching frequency and ambient temperature are also incorporated for online CTR monitoring. Experimental results validate the superiority of this online proactive monitoring method. The method could be extended and further evaluate the health condition of the overall automotive auxiliary converter. [ABSTRACT FROM AUTHOR]

This article presents a control linearization technique for a single-phase single-stage inverter with multiple modulation strategies. The power topology is based on an flying capacitor multi-level (FCML) inverter, and the control is based on the plant inversion. The proposed technique allows decoupling the control of the input current and the output voltage, which simplifies the control in two ways: first, the control of both variables is independent and second, the controllers are independent of the modulation applied, thanks to the plant inversion. This control is implemented in an field-programmable gate array. Since the converter operates at variable frequency, two different data acquisition alternatives are explored: sampling at variable frequency (once per switching cycle) or sampling at constant frequency (higher than the switching frequency).The proposed control is validated by simulation and experimental results with a 1-kVA prototype. [ABSTRACT FROM AUTHOR]

In this study, we propose a configurable multifunction device for the mode division multiplexing (MDM) optical networks. The device can simultaneously function as low- and high-order mode block filters and a mode exchanger by selectively tuning different working states. We fabricated the device using standard microfabrication technology and the experimental performance of the device adequately follows the simulated performance. Particularly, the device exhibits a measured mode extinction ratio of 22.20 dB and 19.46 dB as a low-order mode block filter at $1.550~\mu \text{m}$ wavelength. The proposed device has great potential for use in a fully flexible and advanced MDM optical system. [ABSTRACT FROM AUTHOR]

This article presents an experimental methodology to control the voltage generated from a switched reluctance generator (SRG) using fuzzy logic control. The generated voltage is controlled by varying the demagnetization angle (θoff), maintaining the magnetization angle (θon) fixed. The developed strategy operates on the upper switches of the asymmetric half-bridge converter. The converter topology is used in conjunction with an intermediate freewheeling stage between the steps of magnetization and demagnetization of the phases. The control algorithm was developed in a DSP/FPGA with high processing capacity using LabVIEW graphical platform. Results in open loop and closed loop are presented, subjecting the SRG to variable speeds and load application. For the purpose of performance comparison, a PI compensator has been implemented and tuned for this specific application and the results for both controllers are presented and discussed. For the open-loop tests, the SRG was subjected to variations in the rotor speed, namely, shaft speed varying sinusoidally and triangularly. In these tests, it was observed that the bus voltage suffered great variations. Load variations were also implemented in open loop and, once again, the bus voltage varied significantly. In laboratory tests in closed loop, the SRG was again subjected to variations in sinusoidal and triangular speed and still under load step. In all these experiments, comparisons of results were made between PI controllers and using fuzzy logic control. At the end, it was observed that the imposition of a control loop allowed the bus voltage to be maintained at the preestablished value. [ABSTRACT FROM AUTHOR]

Average small-signal model, known as a simple and powerful tool, is widely used to provide design guidance for switching converters. Due to the ignorance of high-frequency characteristics, conventional average small-signal model fails to reveal dynamics of switching converters with ripple-based control. Improved small-signal models for ripple-based controls, including peak and valley ripple-based controls, are proposed in this article, which can be accurate to half of the switching frequency. Specifically, as for peak or valley current control, the uniform gain representing sample-and-hold effect is derived and suitable for different averaging ways. With regard to V2 control, the improved small-signal model can predict subharmonic oscillation caused by duty cycle and reveal the influence of the equivalent series resistance of output capacitor. Moreover, by combining the improved small-signal models of ripple-based current-mode control and V2 control, small-signal model of V2C control can be analyzed. The relationship among these ripple-based control methods is revealed, and the stability analysis as well as the transient response is carried out. Finally, experimental results turn out to agree well with the theory analysis. [ABSTRACT FROM AUTHOR]

This article presents a fully integrated, high conversion ratio, three-level switched-capacitor (SC) power converter. The converter adopts a tri-mode operation in contrast to classic dual-mode operation in conventional SC converters. The unique circuit structure and operation create an inherent third power rail, which facilitates the use of low-voltage devices at high supply voltage for fast speed and low-silicon real estate. The tri-mode operation naturally matches a three-phase interleaving scheme for improved output voltage ripple and transient response. Implemented on a 0.35-μm BCD process, the design prototype accomplishes a conversion ratio greater than 4:1 and a maximum power delivery of 180 mW at 6-V input and a switching frequency of 93 MHz. With the efficient use of on-chip power switches and capacitors, it achieves a maximum power density of 125 mW/mm2. [ABSTRACT FROM AUTHOR]

The Class Φ2/EF2 amplifier is an attractive topology for high-voltage and high-frequency power conversion because of the high efficiency, reduced device voltage stress, simplicity of gate driving, and load-independent ZVS operation. Due to many degrees of freedom for tuning, previous studies can only solve the single-ended Φ2 circuit using numerical methods. This work focuses on improving the design and operating characteristics of a push–pull Φ2 amplifier with a T network connected between the switch nodes, or a PPT Φ2 amplifier. The PPT Φ2 amplifier has less circulating energy and achieves higher cutoff frequency ƒT than other Φ2/EF2 circuits. We, then, present a series-stacked input configuration to reduce the switch voltage stress and improve the efficiency and power density. A compact 6.78-MHz, 100-V, 300-W prototype converter is demonstrated that uses low-cost Si devices and achieves 96% peak total efficiency and maintains above 94.5% drain efficiency across a wide range of voltage and power. Together with the advances in wide-bandgap semiconductors and magnetic materials, the PPT Φ2 circuit opens more possibilities for the state-of-the-art performance of solid-state RF amplifiers in high-frequency, high-power applications, including wireless charging for electric vehicles, plasma RF drives, and nuclear magnetic resonance spectroscopy. [ABSTRACT FROM AUTHOR]

This article addresses the use of the Thevenin equivalent model in the case of switching circuits. An augmented Thevenin model is proposed, based on a well-established augmented equivalent approach for the analysis of periodically switched linear networks. It can profitably be used to provide a time-invariant equivalent description of a switching network and to investigate on the harmonics behavior at any of its ports even upon the varying of one of its internal parameters. This makes the article interesting for harmonic analysis purposes as, for instance, in the analysis and troubleshooting of electromagnetic interference or in the monitoring of a system behavior through the assessment and analysis of some of its spectral components. The model has also the advantage to be simple in its implementation. The feasibility and potentiality of the method are verified via simulations and comparisons with the results obtained by applying the augmented equivalent approach to the case of a dc–dc Buck converter. [ABSTRACT FROM AUTHOR]

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Multi-objective optimization of power converters is a time-consuming task, especially when multiple operating points and multiple converter topologies must be considered. As a result, various steps are often taken to simplify the design problem and restrict the size of the design space prior to going through an optimization procedure. While this saves time, it produces potentially sub-optimal designs, and existing approaches must tradeoff between running time and design optimality. This paper presents an optimization-oriented method for modeling power converters and their components as posynomial functions, allowing multi-objective optimization of converters to be formulated as a geometric program, a type of convex optimization problem. This allows the use of fast, powerful solvers that guarantee global optimality of solutions. The method is demonstrated using the example of low-power multi-level flying capacitor step-down converters. Results show that, using geometric programming, sets of globally Pareto-optimal designs of two-, three-, and four-level converters with respect to efficiency and power density, for one design space and one operating point, can be generated in as little as 25 s, on a mid- to upper range laptop computer. Thus, optimal designs for three different converter topologies for hundreds of different operating points and/or design spaces can be generated in several hours—less than the time required to globally optimize one converter topology at one operating point for one design space using currently prevalent methods. This paper also demonstrates how geometric programming can be used to quickly perform sensitivity and tradeoff analysis of optimal converter designs. [ABSTRACT FROM AUTHOR]

This article presents a new step-down hybrid converter topology that uses an input flying inductor and a switched-capacitor network to generate output voltages suitable for charging 1-cell (1S) or 2-cell (2S) batteries. The proposed topology relocates the inductor from the high-current output to the low-current input, while providing step-down conversion ratios that take advantage of the higher voltage settings of Universal Serial Bus Type-C (USB-C) power delivery (PD). Moreover, moving the inductor to the input allows the parasitic inductance of a USB cable to be utilized in place of a discrete inductor, that is, a smart-cable architecture, eliminating the need for on-board magnetics and reducing on-board power dissipation. The converter is implemented in 7.37 mm2 of a 130-nm BCD process and provides two outputs with ranges of 3–4.2 V and 6–8.4 V from a 9V input. With a 1 $\mu \text{H}$ discrete inductor, the prototype achieves peak powers of 12.2W and 31.9W and peak efficiencies of 94.3% and 97.4% for each output, respectively. The prototype is also demonstrated in a smart-cable architecture to limit on-board dissipation to 630 mW while delivering 7.2W at the first output or 350mW while delivering 14.4W at the second output. Simultaneous data and power transfer and electromagnetic interference (EMI) tests are provided to support the feasibility of integration into a smart-cable architecture. [ABSTRACT FROM AUTHOR]

A new concept for reducing the losses in a boost converter is described. With the help of an auxiliary switch and a resonant circuit, zero-voltage switching at turn-off and zero-current switching during turn-on are achieved. The modes of the circuit are shown in detail. The energy recovery of the turn-off is analyzed and the recovered energy is calculated; an optimized switching concept therefore is described. The influence of the parasitic capacity of the switch is discussed. Dimensioning hints for the converter and the design of the recuperation circuit are given. A bread-boarded design shows the functional efficiency of the concept.

The abrupt change in current or voltage caused by the rapid switching action of power semiconductor devices will generate high-frequency electromagnetic interference (EMI) and needs to be located as the primary interference sources in power electronics. This paper deals with interference suppression on the basis of the study of shaped switching transients in switching waveforms and closed-loop gate drive method for power MOSFETs. The characteristics of switching waveforms with arbitrary switching transients are investigated in both timeand frequency-domain. In addition, conditions of constructing a switching waveform with optimized switching transients are put forward. An optimized Gaussian switching waveform with infinite successive derivatives is proposed which provides the deepest decreasing rate in the interference source spectrum for a given switching time. Compared with a trapezoidal waveform with singleslope transients, the proposed switching waveform has better interference suppression at high frequencies. Meanwhile, a closed-loop gate control prototype with on-state resistance compensation is presented to shape the switching transients of power MOSFETs. The simulated and experimental results show that the proposed controller is successfully implemented to shape the drain-source voltage into an optimized Gaussian reference. Spectrum comparisons show that the EMI generation is effectively suppressed as expected.

This study presents a newly developed modular system for control of power electronic amplifiers in high-power, high-frequency power hardware in the loop experiments. The proposed design comprises computational nodes connected via multi-gigabit fibre-optic links. Nodes are modular and reconfigurable, allowing interfacing with a range of sensors and actuators, typically voltage and current sensors, and switching converters. The system has been designed for scalability to permit arbitrarily high power ratings and fidelity to be achieved through paralleling and interleaving of multiple power converter modules, targeting an ultimate sample and control rate of 1 MHz. Experimental validation is presented using a two-node configuration to facilitate a power electronic experiment operating at 120 V(rms) and 10 A(rms), with a fundamental frequency of 50 Hz and frequency content up to the 11th harmonic.

In this paper we present an approach for real-time simulation and Hardware-in-the-Loop (HIL) testing of Modular Multilevel Converters (MMCs) that rely on switching models while supporting system level analysis. Using the Latency Based Linear Multistep Compound (LB-LMC) approach, we achieved a 50 ns simulation time step for systems composed of several MMC converters and for converters of various complexity. To facilitate system level testing, we introduce the use of a serial communication-based (Aurora) interface for HIL testing of MMC converters and we analyzed the effect that communication latency has on the accuracy of the HIL test. The simulation and HIL results are validated against an MMC laboratory prototype.

LED lamps are both potential victims and sources of electromagnetic disturbances in the frequency range between 2 and 150 kHz (“supraharmonics”). Immunity tests for this frequency range are important due to possible performance degradation of light intensity with LED lamps. In this paper, the impact of supraharmonics (SHs) on light intensity from LED lamps has been analyzed. LED lamps have been exposed to SH test profiles based on IEC 61000-4-19. Three phenomena that impact light intensity metrics have been observed and explained by models: 1) earlier conduction/later blocking caused by SH voltage, 2) intermittent conduction depending on the SH impedance of the LED driver, and 3) reverse-recovery current of the diodes at higher frequency. It is observed that impact on the light intensity metrics shows up around the beginning and end of the conduction period. The results reveal that the profile of the SH voltage could cause deviations in the modulation depth and the average light intensity. The immunity of LED lamps against SHs shall be further studied and discussed by research groups and standard committees. [ABSTRACT FROM AUTHOR]

This study presents a newly developed modular system for control of power electronic amplifiers in high-power, high-frequency power hardware in the loop experiments. The proposed design comprises computational nodes connected via multi-gigabit fibre-optic links. Nodes are modular and reconfigurable, allowing interfacing with a range of sensors and actuators, typically voltage and current sensors, and switching converters. The system has been designed for scalability to permit arbitrarily high power ratings and fidelity to be achieved through paralleling and interleaving of multiple power converter modules, targeting an ultimate sample and control rate of 1 MHz. Experimental validation is presented using a two-node configuration to facilitate a power electronic experiment operating at 120 Vrms and 10 Arms, with a fundamental frequency of 50 Hz and frequency content up to the 11th harmonic. [ABSTRACT FROM AUTHOR]

Switching-linear hybrid envelope tracking (SLH ET) power supplies can achieve both high efficiency and high bandwidth. However, the switching frequency is often required to be far higher than or at least equal to the envelope bandwidth. With the modulation methods advance, the increasing envelope bandwidth may lead to a too high switching frequency to implement. This paper proposes an SLH ET power supply, consisting of a multilevel converter and a linear amplifier connected in series. Based on the multicell configuration of the multilevel converter, a pulse edge independent distribution method is proposed, which can break the control pulses for the multilevel converter into independent rising and falling edges, and rebuild them with new sequences. It can not only reduce the switching frequency to 1/n (n ∊ N) of the envelope bandwidth but also extend the pulsewidths to provide a more reliable and effective driving for high bandwidth applications. A prototype for 2 MHz sine-wave tracking, with 7–27-V output voltage and 90-W peak output power, is fabricated and tested. It is also verified by a 5- and a 10-MHz bandwidth communication envelope. The experimental results validate the proposed method. [ABSTRACT FROM AUTHOR]

The emulation of virtual resistance finds various applications in the power processing industry. This paper proposes a novel notion of adaptive sliding mode based loss free resistor (ASLFR). This is achieved by allowing the input power of the power-out power-in (POPI) system to vary, in order to accommodate the load demands. In this paper, the concept is illustrated for power-factor correction (PFC) applications. The ASLFR is used to achieve the dual purpose of harmonics-free rectification along with excellent system response under load and line transients. The scheme serves itself as an efficient single-stage PFC solution. A generic mathematical formulation of the scheme is presented, which can be used for different converters. Then on, a boost topology, operating in continuous conduction mode, is chosen to demonstrate theoretical developments and to showcase the effectiveness of the scheme. The robustness of the proposed controller to any line or load variation is established. A fast voltage recovery with almost no undershoot/overshoot is achieved at transients by using the proposed controller. Additionally, a qualitative analysis is provided to demonstrate the expediency of the proposed ASLFR. The theoretical claims are well supported by simulation as well as experimental results. [ABSTRACT FROM AUTHOR]

An instantaneous power consuming level shifter is presented in this brief to increase the dc converter efficiency. The level shifter is used in a high-side power switch driver to remove the external capacitor which is used in bootstrap technique. The level shifter consumes power only during the transition period. A delay cell is used to turn the level shifter off to reduce the power consumption period. An output voltage detector is added to turn the level shifter off even before the delay time. An asynchronous discontinuous conduction mode buck converter is designed to verify the performance of the level shifter. Simulation results show that the power consumption of the proposed level shifter decreased by 66%, while the converter efficiency increased by the maximum of 9% compared to results obtained for a conventional level shifter. The converter is fabricated using the TSMC 0.18- $\boldsymbol {\mu }\text{m}$ BCD process and it operates within an input range of 2–5 V when the current varies from 400 $\boldsymbol {\mu }\text{A}$ to 18 mA and delivers an output voltage of 1.8 V. [ABSTRACT FROM AUTHOR]

Resonant converters under zero current switching control strategy can exhibit coexistence of attractors, making it difficult the startup of the system from zero initial conditions. In this brief, the problem of multiple coexisting attractors in parallel resonant converters is addressed. Appropriate modifications of the switching decision with the aim of converting undesired attractors into virtual ones are proposed. A suitable control signal is generated from the state variables of the system and used to adjust the switching decision. Numerical simulations corroborate the proposed solutions and the simplest one was finally verified by measurements from a laboratory prototype. [ABSTRACT FROM AUTHOR]

Several researches have been done in literature to improve the resolution of pulse mode architectures used for controlling the DC–DC converters. Resolution can be measured as the number of bits used for representing the duty cycle control input [1]. Higher the resolution of control inputs more precisely the changes in output voltage with DC–DC converter can be addressed [2]. Traditional architectures implemented with counter and other delay line structure occupies large area and also has less throughput with an increase in number of control inputs. But the DC–DC converters used in portable and mobile based applications must be compact and consumes low power [3]. This proposed DPWM architecture uses Block RAM available in FPGA to store the binary bit patterns to derive variable duty cycle pulses [4]. The architecture is proposed for three different control inputs like four bit, three bit and two bit control inputs. This proposed architecture for a four bit control input can address 4096 bit patterns and has maximum operating clock frequency of 306.84 megahertz (MHz). [ABSTRACT FROM AUTHOR]

This paper presents a micro-watt level energy harvesting system for piezoelectric transducers with a wide input voltage range. Many such applications utilizing vibration energy harvesting have a widely varying input voltage and need an interface that can accommodate both low and high input voltages in order to harvest as much energy as possible. The proposed system consists of two rectifiers, both implemented as negative voltage converters followed by active-diodes, and three switched-capacitor DC-DC converters to either step-up or step-down and regulate to the target voltage. The system has been implemented in a 0.18 μm CMOS process and the chip measures 3 mm2. Measurements show a low voltage drop across the rectifiers and high peak power efficiency of the DC-DC converters (68.7-82.2%) with an input voltage range of 0.45-5.5 V for the complete system. Used standalone, the DC-DC converters support input voltages between 0.5 and 11 V while maintaining an output voltage of 1.8 V at an output power of 16.2 μW. The ratio of each converter is selectable to be either 1:2, 1:3, or 1:4. [ABSTRACT FROM AUTHOR]

Many autonomous sensor nodes use small photovoltaic (PV) panels oriented toward the direction that provides the highest energy yield in the worst case scenario. Since all those panels operate at similar irradiance and temperature conditions, they can be properly biased at the same bias point by using a single maximum power point tracker (MPPT). But in applications that involve several PV panels with dissimilar orientations, using an MPPT tailored to each panel would increase system cost. A better design option is to implement the MPPT with a single multiple-input converter shared through time-division multiplexing (TDM) control. However, existing TDM controls are usually based on pulsewidth modulation converters wherein the high switching frequency of transistors results in excessive power losses for low-power systems. Consequently, low-power MPPTs are instead usually based on pulse frequency modulation (PFM) converters. This paper proposes a novel TDM control method for MPPTs based on PFM converters. [ABSTRACT FROM AUTHOR]

Summary: This paper presents a 7.7‐mm2 on‐chip LED driver based on a DC/DC resonant hybrid‐switched capacitor converter operating in the MHz range with and without output capacitor. The converter operation allows continuously dimming the LED while keeping control on both peak and average current. Also, it features no flickering even in the absence of output capacitor and for light dimmed down to 10% of the nominal value. The capacitors and switches of the LED driver are integrated on a single IC die fabricated in a low‐cost 5 V 0.18‐μm bulk CMOS technology. This LED driver uses a small (0.7 mm2) inductor of 100 nH, which is 10 times smaller value than prior art integrated inductive LED drivers, still showing a competitive peak efficiency of 93% and achieving a power density of 0.26 W/mm2 (0.34 W/mm3). [ABSTRACT FROM AUTHOR]