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Conventional semiconductor-based integrated circuits are gradually approaching fundamental scaling limits. Many prospective solutions have recently emerged to supplement or replace both the technology on which basic devices are built and the architecture of data processing. Neuromorphic circuits are a promising approach to computing where techniques used by the brain to achieve high efficiency are exploited. Many existing neuromorphic circuits rely on unconventional and useful properties of novel technologies to better mimic the operation of the brain. One such technology is single flux quantum (SFQ) logic—a cryogenic superconductive technology in which the data are represented by quanta of magnetic flux (fluxons) produced and processed by Josephson junctions embedded within inductive loops. The movement of a fluxon within a circuit produces a quantized voltage pulse (SFQ pulse), resembling a neuronal spiking event. These circuits routinely operate at clock frequencies of tens to hundreds of gigahertz, making SFQ a natural technology for processing high frequency pulse trains. This work harnesses thermal stochasticity in superconducting synapses to emulate stochasticity in biological synapses in which the synapse probabilistically propagates or blocks incoming spikes. The authors also present neuronal, fan-in, and fan-out circuitry inspired by the literature that seamlessly cascade with the synapses for deep neural network construction. Synapse weights and neuron biases are set with bias current, and the authors propose multiple mechanisms for training the network and storing weights. The network primitives are successfully demonstrated in simulation in the context of a rate-coded multi-layer XOR neural network which achieves a wide classification margin. The proposed methodology is based solely on existing SFQ technology and does not employ unconventional superconductive devices or semiconductor transistors, making this proposed system an effective approach for scalable cryogenic neuromorphic computing.

Superconductor electronics (SCE) is competing to become a platform for efficient implementations of neuromorphic computing and deep learning algorithms (DLAs) with projects mostly concentrating on searching for gates that would better mimic behavior of real neurons. In contrast, we believe that most of the required components have already been demonstrated during the long history of SCE, whereas the missing part is how to organize these components to efficiently implement DLAs. We propose a family of logic/memory cells in which stored multi-bit data are encoded by quasi-analog currents or magnetic flux in superconductor loops while transmitted data are encoded as the rate of SFQ pulses. We designed, fabricated, and tested some of the basic cells to demonstrate a proof of concept, e.g., a unipolar and bipolar multipliers based on Josephson junction comparators. We coined the term bioSFQ to clearly connote close but distinguishable relations between the conventional SFQ electronics and its new neuromorphic paradigm. [ABSTRACT FROM AUTHOR]

Superconductor electronics fabrication technology developed at MIT Lincoln Laboratory enables the development of VLSI digital circuits with millions of Josephson junctions per square centimeter. However, conventional DC and multi-phase AC biasing techniques already encounter serious challenges for scaling circuits above several hundred thousand junctions. In this work, we propose a novel AC-based biasing scheme for RSFQ-type logic families requiring DC bias. The major step toward this scheme is a superconducting AC/DC rectifier which we introduced at ASC 2014. We proposed to connect the rectifiers to “payload cells” via superconducting inductors with large inductance in order to reduce parasitic effects of flux quantization. Recently, we discovered that this powering scheme works even better at a much lower value of the inductance, when it is just sufficient to hold only one or two flux quanta in the inductive loop between the converter and the payload. In this case, flux quantization in the loop becomes beneficial because the value of current fed into the payload is defined by the value of the coupling inductance. Therefore, our AC/SFQ converter powers the payload cell by single flux quanta rather than by DC current. Such mode of operation is extremely energy efficient because energy is used only to recover the flux quantum consumed by the cell during the logic operation. We present designs of AC/SFQ converters comprising an AC/DC rectifier and a current conditioning circuit which we termed an SFQ filter. We also present test results and demonstrate AC/SFQ powering a payload circuit using circuits fabricated in a new, 150-nm node of Lincoln Laboratory fabrication technology using self-shunted Nb/AlOx-Al/Nb Josephson junctions with 600 µA/µm2 critical current density and 200 nm minimum linewidth of inductors. [ABSTRACT FROM AUTHOR]

By modeling the propagation of a seed layer with various crystal orientations, this study explores the influence of process variations on grain formation with the help of a physics-based process simulator. Grain boundaries allow easy diffusion of foreign atoms through the lattice, which causes Al to move inside the Nb bottom electrode layer and more interestingly, O to penetrate through the Al layer during oxidation and create a barrier with non-uniform thickness. In addition to thickness variations, the grain structure exhibited by Nb and Al can cause significant suppression of supercurrent at the boundaries depending on the degree of lattice mismatch, impurity deposition, etc. This work details the process simulation of grain boundary formation and aims to provide geometrical models that may be used in the simulation of device performance to account for process-induced variations. [ABSTRACT FROM AUTHOR]

The adiabatic quantum-flux-parametron (AQFP) superconductor logic family has the potential to be the electronics groundwork for energy-efficient large-scale computing. To this end, we have been developing an AQFP top-down design flow, and our design efficiency has improved recently for combinational logic circuits. As a next step, we establish a methodology to synthesize sequential logic circuits which we previously did not consider. In this paper, we describe our sequential logic circuit model and how it can be used to map the sequential elements of an RTL (register transfer level) behavioral design. Next we discuss the structure of sequential circuits in more detail using a benchmark of N-bit counters. Lastly, we show some preliminary results of a synthesized 16 bit MIPS microprocessor. During this study, we also developed an architectural retiming methodology to reduce the number of synchronization buffers needed for microprocessor pipeline stage balancing. [ABSTRACT FROM AUTHOR]

Soft defects caused by flux quanta not captured by moats during superconductor integrated circuit cooldown are known to degrade circuit performance. However, haphazard or random moat placement does not necessarily improve circuit performance and may even degrade it. Under the IARPA SuperTools program we have both developed numerical simulation tools to extract simulation models of circuit structures in the presence of trapped fluxons and designed experiments to measure the probability of flux trapping in moats and the coupling of such trapped flux to circuit structures. Depending on moat structure, the coupling from a few moat-captured fluxons is shown to reduce the critical current for a SQUID by 20% or more, which justifies a thorough analysis. We present results for this very important aspect of magnetic rule checking and show how controlled flux trapping experiments in designated moats yield measurement results that fit simulated predictions very well. With the simulation tools validated, we show how flux trapping is incorporated into compact simulation models and we detail the extraction of magnetic coupling and the calculation of the compact models for both branch and loop-type simulations. We also show how phase-based simulation with the circuit simulator JoSIM allows arbitrary fluxon insertion in moats during transient circuit simulation and conclude with some recommended design rules for moat geometry, size, and placement. [ABSTRACT FROM AUTHOR]

We conducted the first successful demonstration of an adiabatic microprocessor based on unshunted Josephson junction (JJ) devices manufactured using a Nb/AlOx/Nb superconductor IC fabrication process. It is a hybrid of RISC and dataflow architectures operating on 4-b data words. We demonstrate register file R/W access, ALU execution, hardware stalling, and program branching performed at 100 kHz under the cryogenic temperature of 4.2 K. We also successfully demonstrated a high-speed breakout chip of the microprocessor execution units up to 2.5 GHz. We use a logic primitive called the adiabatic quantum-flux-parametron (AQFP), which has a switching energy of 1.4 zJ per JJ when driven by a four-phase 5-GHz sinusoidal ac-clock at 4.2 K. These demonstrations show that AQFP logic is capable of both processing and memory operations and that we have a path toward practical adiabatic computing operating at high-clock rates while dissipating very little energy. [ABSTRACT FROM AUTHOR]

Superconductor electronics combines passive and active superconducting components and sometimes normal resistors into functional circuits and systems that also include room-temperature electronics for amplification, power sources, necessary controls, etc., usually computer operated. Furthermore, complete systems include magnetic and electromagnetic shielding, cryogenic enclosures, and increasingly a cryocooler in self-contained units. Components or devices of low or high critical temperature superconductors include inductances (coils), passive transmission lines, resonators, antennae, filters, as well as active elements: Josephson junctions, Josephson oscillators, and superconducting quantum interference devices. Of multiple demonstrated applications, mostly but not only in science and metrology, currently most successful are voltage standards, astronomy detectors and large telescope cameras, instruments for material characterization, and magnetometers for geomagnetic prospecting. Major current efforts concentrate on energy-efficient high-end computing and quantum computing. The outcomes of these efforts are likely to be known in the course of the following decade. [ABSTRACT FROM AUTHOR]

Will quantum computation become an important milestone in human progress? Passionate advocates and equally passionate skeptics abound. IEEE already provides useful, neutral forums for state-of-the-art science and engineering knowledge as well as practical benchmarks for quantum computation evaluation. But could the organization do more? [ABSTRACT FROM AUTHOR]

We develop an ac-biased shift register introduced in our previous work (V. K. Semenov et al., IEEE Trans. Appl. Supercond., vol. 25, no. 3, 1301507, June 2015) into a benchmark circuit for evaluation of superconductor electronics fabrication technology. The developed testing technique allows for extracting margins of all individual cells in the shift register, which in turn makes it possible to estimate statistical distribution of Josephson junctions (JJs) in the circuit. We applied this approach to successfully test registers having 8-, 16-, 36-, and 202 thousand cells and, respectively, about 33-, 65-, 144-, and 809 thousand JJs. The circuits were fabricated at MIT Lincoln Laboratory, using a fully planarized process, 0.4-μm inductor linewidth and 1.33 × 106 cm−2 junction density. They are presently the largest operational superconducting SFQ circuits ever made. The developed technique distinguishes between “hard” defects (fabrication-related) and “soft” defects (measurement-related) and locates them in the circuit. The “soft” defects are specific to superconducting circuits and caused by magnetic flux trapping either inside the active cells or in the dedicated flux-trapping moats near the cells. The number and distribution of “soft” defects depend on the ambient magnetic field and vary with thermal cycling even if done in the same magnetic environment. [ABSTRACT FROM PUBLISHER]

Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90 ^\circ bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with 8 niobium layers, developed at MIT Lincoln Laboratory for very-large-scale superconducting integrated circuits. Excellent run-to-run reproducibility and inductance uniformity of better than 1% across 200-mm wafers have been found. It has been found that the inductance per unit length of stripline and microstrip line inductors continues to grow as the inductor linewidth is reduced deep into the submicron range to the widths comparable to the film thickness and magnetic field penetration depth. It is shown that the linewidth reduction does not lead to widening of the parameter spread due to diminishing sensitivity of the inductance to the linewidth and dielectric thickness. The experimental results were compared with numeric inductance extraction using commercial software and freeware, and a good agreement was found for 3-D inductance extractors. Methods of further miniaturization of circuit inductors for achieving circuit densities >10^6 Josephson junctions per \cm^2 are discussed. [ABSTRACT FROM PUBLISHER]

The correct operation and high performance of complex superconducting integrated circuits significantly depend on fabrication-process-induced variations of the Josephson junction critical current Ic. Such variations in Nb/Al/AlOx/Nb junctions were investigated and shown to be dependent on how the junction electrodes are connected to other layers in the integrated circuit, especially the ground plane and the Ti/Pd/Au contact pad. The observed enhancement of Ic and gap voltage over time for junctions with certain wiring connections suggests that the phenomenon is related to the diffusion over time of impurities between the junction electrode and the Ti/Pd/Au pad. Considering the strong affinity of both Nb and Ti to H, a model where H is the main impurity element involved in the diffusion-related phenomenon is presented. The results show that direct wiring to Ti is sufficient to observe Ic variations. The results also suggest that as fabricated, the interface between the junction counter-electrode and the AlOx barrier is already close to or at full H saturation, significantly depressing the Ic by up to 20%, compared to clean Nb junctions. [ABSTRACT FROM AUTHOR]

Abstract: The state-of-the-art Rapid Single Flux Quantum (RSFQ) circuits consists of Josephson junctions (JJ), inductances and bias current sources, whereat the inductances are practically used as functional elements. Even more, their value defines the functionality and therefore the conventional design process requires strict conditions for the wiring between JJs. The present design and optimization process does not take into account distributed microwave properties. This becomes an important issue for high-dense ultra fast applications above 100GHz, but also for circuits dedicated to control quantum electronics with reduced critical current density. We discuss different wiring configurations and analyze their properties. We present our theoretical and experimental results about the influence of the line impedance to the operation of RSFQ circuits. The impedance matching between the connecting microstrip-lines and the JJ is a key issue for the correct operation. We performed circuit simulations and collected experimental data of correct and incorrect operating circuits to derive a design criteria. The critical reflection coefficient is 0.35 and the particular design must use a smaller value to ensure pulse transfer and a larger value for storage of SFQ pulses, respectively. [Copyright &y& Elsevier]

Fabrication-induced variations in the critical currents of Josephson junctions significantly affect the performance and yield of complex superconducting integrated circuits. Electrical stress that may develop during plasma processing steps in the fabrication process was initially suggested as a possible cause of these variations. The effect on the Josephson and quasipartide tunneling properties of Nb/A1/A1OxNb junctions with ultrathin A1Ox, barriers by the application of dc electrical stress was investigated. Current ramps with increasing amplitude corresponding to voltages across the barrier up to ∼0.65 V were used to apply electrical stress. Junction conductance and current-voltage (I-V) characteristics were measured after each stress application at room temperature. As the stressing progresses, a dramatic increase in subgap conductance of the junctions, the appearance of subharmonic current steps, and a gradual increase in both the critical and the excess currents as well as a decrease in the normal-state resistance have been observed. A model is proposed wherein a progressively increasing number of defects and associated additional conduction channels (superconducting quantum point contacts (SQPC5)) are induced by the applied electric field in the tunnel barrier. The dependence of the stress effect on the polarity is also investigated and the results are presented. It is found that the magnitude of stress current needed for junction breakdown is unlikely to be supplied during plasma processing and as such, potential differences that can develop during plasma processing appear to be an unlikely cause of fabrication-induced, circuit pattern-dependent variations of Josephson junctions' critical currents in superconductor integrated circuits. [ABSTRACT FROM AUTHOR]

It is widely accepted that flux trapping is one of the most serious problems that could create an integration limit for superconductor integrated circuits. The ultimate goal of our project is to reduce the problem to a set of routine technical recommendations for SFQ circuit design. To achieve the goal, we review known theories and recommendations for the reduction of flux trapping. Another important part of the project is an experimental verification of our suggestions. In this paper, we describe our experimental technique, which allows measurements to be carried out in real environments, for example, in a closed-cycle refrigerator or transport Dewar. To illustrate the advantages of our technique we discuss in detail the measured flux trapping properties of one test circuit: a 16-bit shift register. We found that the flux trapping properties of apparently similar cells vary dramatically from cell to cell. In other words, the effects of microscopic fabrication imperfections could be as important as layout optimization. [ABSTRACT FROM AUTHOR]

Decimation filters are still the most complex and valuable superconductor digital circuits, so it is natural to use them to compare different design techniques. In the paper we discuss two new techniques. The first deals with the DC biasing scheme. For debugging purposes it is convenient to use separate power lines for different functional blocks. However, the lines occupy extra space, which could be unacceptable for a final design, when the decimation filters become part of larger circuits, for example, low-pass or band-pass ADCs. We will discuss an efficient rewiring technique that saves space during the connection of separate power lines after the circuit is debugged. The second technique is a selective use of micro-strip lines. Our solution contrasts with ‘extreme’ recommendations for micro-strip lines as a universal tool for inter cell connections. More specifically for each connection we select either Josephson transmission or micro-strip line connection to keep the occupied area as small as possible. This highly ‘custom’ design is possible due to parametric cell technique that dramatically accelerates the design procedure. In particular, we easily converted the circuit initially developed for 1 kA/cm2 standard HYPRES technology to the advanced technology with higher (4.5 kA/cm2) critical current density. The filter has 20 GHz and 40 GHz target sampling frequencies for lkA/cm2 and 4.5 kA/cm2 fabrication processes respectively. The circuits are fully operational at low frequency. [ABSTRACT FROM AUTHOR]

The HYPRES 3.0 μm Niobium (Nb) process has proven to be capable of realizing complex Low Temperature Superconductor (LTS) Rapid Single Flux Quantum (RSFQ) circuits. In such a mature fabrication process, the importance of the detection of random defects is crucial as they contribute to the majority of the defects occurring while processing the chips. The global low yield in SCE is due to the fact that little is known about the defects and fault mechanisms occurring in Nb technology. This is, however, of crucial importance in realizing the required complex systems with yields required for commercial production. For this purpose, a structural testing approach has been applied to the HYPRES Nb process. As a result, we have developed test structures for the detection of random defects in the process. Test chips were realized in the process and measurements were carried out. Test results on the processed chips leading to defect statistics in the HYPRES Nb Process are presented in this paper. [ABSTRACT FROM AUTHOR]