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High density phase change memory array requires both minimized critical dimension (CD) and maximized process window for the phase change material layer. High in-wafer uniformity of the nanoscale patterning of chalcogenides material is challenging given the optical proximity effect (OPE) in the lithography process and the micro-loading effect in the etching process. In this study, we demonstrate an approach to fabricate high density phase change material arrays with half-pitch down to around 70 nm by the co-optimization of lithography and plasma etching process. The focused-energy matrix was performed to improve the pattern process window of phase change material on a 12-inch wafer. A variety of patternings from an isolated line to a dense pitch line were investigated using immersion lithography system. The collapse of the edge line is observed due to the OPE induced shrinkage in linewidth, which is deteriorative as the patterning density increases. The sub-resolution assist feature (SRAF) was placed to increase the width of the lines at both edges of each patterning by taking advantage of the optical interference between the main features and the assistant features. The survival of the line at the edges is confirmed with around a 70 nm half-pitch feature in various arrays. A uniform etching profile across the pitch line pattern of phase change material was demonstrated in which the micro-loading effect and the plasma etching damage were significantly suppressed by co-optimizing the etching parameters. The results pave the way to achieve high density device arrays with improved uniformity and reliability for mass storage applications. [ABSTRACT FROM AUTHOR]

This paper presents the Step-by-Step Design of memory hierarchy for heterogeneously-integrated SCM/NAND flash storage. The heterogeneously-integrated storages utilize multiple types of non-volatile memories such as storage class memories (SCMs) and NAND flash memories. SCMs are further classified to memory-type and storage-type. NAND flash memories are also characterized by the number of stored bits per cell. These non-volatile memories show complex trade-off of various latency, power, capacity and cost. What's worse, in NAND flash, garbage collection seriously degrades the performance. Thus, the intelligent mix & match of these memories is required, depending on each workload. For various storage applications, this paper shows that optimal SCM/NAND flash hierarchies are determined by considering system performance, energy consumption, endurance, and cost for each workload. The recommended non-volatile memory combinations with SCMs and NAND flash memories are proposed for representative 7 storage application workloads with diverse characteristics. The proposed Step-by-Step Design is the useful solution for the heterogeneously-integrated storage with multiple types of non-volatile memories and for various applications. [ABSTRACT FROM AUTHOR]

Recent developments in storage class memory (SCM) such as PCM, MRAM, resistive RAM (RRAM), and spin-transfer torque (STT)-RAM have strengthened their leadership as storage media for memory-based file systems. Traditional Linux memory-based file systems such as Ramfs and Tmpfs utilize the Linux page cache as a file system. These file systems have unnecessary overheads when adopted for SCM file system. Therefore, we propose a new memory-based file system using Memory Zone Partitioning called ZonFS, by extending the Linux Ramfs. In particular, we define a storage zone for SCM, modify the Ramfs to allocate a file system page from SCM. ZonFS avoids running Linux VM kernel codes such as (i) inserting pages allocated from SCM into the LRU list for VM page replacement and (ii) checking dirty pages for write-back to disk. Our extensive evaluations indicate that ZonFS has up to 9.1 and 14.1% higher I/O throughputs than native Ramfs and Tmpfs. Moreover, we also analyze performance behavior of ZonFS under the non-uniform memory access architecture of SCMs on a 40 manycore machine with various configurations such as file sharing level and file stripping level. Our evaluations show that memory controller contention and inter-node link congestion significantly affect the file system's performance and scalability. [ABSTRACT FROM AUTHOR]

The cross-point architecture for memory arrays is widely considered as one of the most attractive solutions for storage and memory circuits thanks to simplicity, scalability, small cell size, and consequently high density and low cost. Cost-scalable vertical 3-D cross-point architectures, in particular, offer the opportunity to challenge Flash memory with comparable density and cost. To develop scalable cross-point arrays, however, select devices with sufficient ON–OFF ratio, current capability, and endurance must be available. This paper presents a select device technology based on volatile resistive switching with Cu and Ag top electrode and silicon oxide (SiOx) switching materials. The select device displays ultrahigh resistance window and good current capability exceeding 2 MAcm−2. Retention study shows a stochastic voltage-dependent ON–OFF transition time in the 10~\mu \texts –1 ms range, which needs to be further optimized for fast memory operation in storage class memory arrays. [ABSTRACT FROM PUBLISHER]

The ultimate challenge of filamentary oxide-based ReRAM devices for storage-class memory application is the control of oxygen vacancies. As a result of the specifications dictated by the performance-cost dependency, oxygen vacancies in the conductive filament are predominantly isolated. This paper tries to shed light on the properties and implications of isolated vacancies in conductive filaments of oxide-based ReRAM devices. The isolated defects are a consequence of the low power requirements and result in very unstable resistance states. To find viable engineering solutions, the physical origins of these unstable states need to be investigated. Some of the possible origins like isolated vacancies and the effect of excess charge in the switching layer are outlined in this paper. [ABSTRACT FROM AUTHOR]

NAND flash memory-based solid-state drives (SSDs) are increasingly being used in both consumer and enterprise storage markets, due to their superior performance over hard disk drives (HDDs) and continuous bit cost reductions. With multiple-level cell technology memory device is capable of trading off the performance and endurance with bit density. The more bits per cell there are, the longer latency and shorter lifetime. On the other hand, the performance of such SSDs is limited due to NAND flash access speed as well as the need of garbage collection. Recently, storage class memories (SCMs) like resistive RAM (ReRAM) and phase change RAM (PRAM) have been developed to fill the bandwidth gap between DRAM and NAND flash memory. SCMs are nonvolatile and byte addressable, which are much faster and durable than NAND flash. Therefore, with SCMs, the storage performance would be significantly improved. Hybrid SSDs are promising cost-efficient storage solutions. Various types of memories like single-level cell (SLC), multiple-level cell (MLC), triple-level cell (TLC) NAND flash memories, and SCMs create lots of opportunities for new system architectures and algorithms. In this paper, the architecture and algorithm design overview of three types of hybrid drives including MLC/TLC NAND flash hybrid, SCM/MLC NAND flash hybrid, and SCM/MLC/TLC NAND flash tri-hybrid are presented. From the evaluation results, hybrid drives demonstrate better performance, endurance, and power consumption, compared to the MLC NAND flash only SSD. Furthermore, the relationship between device reliability and performance of the SCM/NAND flash hybrid SSD has been understood at a system level. There is a tradeoff between acceptable bit error rate of SCM and NAND flash. In addition, the decoding latency of SCM affects the performance of hybrid SSD more than that of NAND flash. [ABSTRACT FROM PUBLISHER]

Resistive random access memory (RRAM) is regarded as one of the most promising emerging memory technologies for next-generation embedded, standalone nonvolatile memory (NVM), and storage class memory (SCM) due to its speed, density, cost, and scalability. Considerable progress has been made in recent years on the manufacturability of RRAM, with low-density RRAM products now in production and the path to higher density parts becoming clearer. This review updates the learning on the fundamental materials and process integration needed for high-volume manufacturing and summarizes very recent progress on array level performance improvement methodology using novel techniques, and circuit level contributions for different applications. The device performance, array integration, and device/circuit codesign for memory systems are discussed. Novel applications besides embedded memory and standalone memory are addressed, including hardware security, neuromorphic computing, and nonvolatile logic systems. [ABSTRACT FROM PUBLISHER]

Storage Class Memory (SCM) is emerging as a viable solution to lift DRAM's scalability limits, both in capacity and energy consumption. Indeed, SCM combines the economic characteristics, non-volatility, and density of traditional storage media with the low latency and byteaddressability of DRAM. In this paper we survey research works on how SCM can be leveraged in databases and explore different solutions ranging from using SCM as disk replacement, to single-level storage architectures, where SCM is used as universal memory (i.e., as memory and storage at the same time), together with the challenges that stem from these opportunities. Finally, we synthesize our findings into recommendations on how to exploit the full potential of SCMin next-generation database architectures. [ABSTRACT FROM AUTHOR]

Hybrid memory comprised of a big SCM and a little DRAM (BSLD) is widely studied to address the growing power consumption challenge of pure DRAM. However, the performance degradation, limited endurance and immature mass production of ultra-high-density SCM are still the painful points of BSLD. Here we propose a Retention-Aware Hybrid Main Memory (RAHMM) architecture with a big DRAM and a little SCM (BDLS) for the first time. DRAM is refreshed at a much longer interval by using SCM to store the small quantity of leaky tail bits in DRAM. A two-step search technology combined with outcome forecasting is put forward to get ultra-fast read access, as well as to diminish the power and performance overheads. A hidden buffer strategy (HBS) is proposed to optimize write performance and endurance hurt. The experimental results show 45 percent reduction of power consumption and 30 percent performance optimization, which are significantly improved compared to that of both serial and parallel BSLD with a counterpart capacity [ABSTRACT FROM AUTHOR]

In this letter, simple binary Ovonic threshold switching (OTS) material with outstanding selector device performance has been demonstrated. Even with its simple material composition and easy fabrication process, the selector device with the binary OTS material showed excellent selector performance such as high-OFF resistance (> 1 G \Omega at 0.1 V), low-ON resistance (< 1 k \Omega at 2.0 V), extremely sharp switching slope (< 1 mV/dec), fast operating speed ( \textt\mathrm {transition} <2 ns, \textt\mathrm {delay} <7 ns), high endurance (> 108 cycles of 150 ns pulse), high electrical stability (> 1 ks at 1.2 V), and high thermal stability (> 400 °C / 30 min). Furthermore, conduction mechanism of the OTS has been explained by Poole-Frenkel-based analytical modeling. [ABSTRACT FROM AUTHOR]

New storage class memory (SCM) technologies, such as phase change memory (PCM) and memristors, are not only byte-addressable like DRAM but also non-volatile like traditional hard disk drives. SCM modules can be placed side-by-side with DRAM on the memory bus, available to memory instructions issued by the CPU. This shift thus engenders a new “DRAM-SCM” storage architecture, which promises near-DRAM secondary storage access speed at several orders of magnitude faster than magnetic disk or flash memory. Utilizing SCM as a secondary storage device will have a profound impact on memory hierarchy design, requiring new architectural and operating system support. In this paper, we adopt PCM in the DRAM-SCM storage architecture and present BSS to provide file system-independent B lock device S upport for S torage class memory. To ensure backward compatibility and high performance, BSS provides a block device interface found in traditional hard disk drives and allows existing file systems to be built on top of itself without any modifications. BSS is designed to directly access the PCM through memory instructions and bypass traditional disk caches that are intended to reduce seek time. The DRAM-SCM architecture and BSS are prototyped in QEMU and the Linux kernel, respectively. Validation using benchmarks reveals that both work together well to exploit significant advantages of SCM. Compared to traditional hard disk drives, our approach boosts the write/read performance by up to 204x for large files and achieves comparable performance for small ones. [ABSTRACT FROM AUTHOR]

ICT has been all -- pervasive, fertilizing and empowering nearly all areas of our life, creating interaction and interdependence. The present paper examines some of the developments, starting with the economic and technologic state of the industry, the transition from mM to MtM and the impacts on individuals and society. Additionally, it renders tribute to the two anniversaries deserving special attention: 50 Years of „Moore's Law” and 25 years of public Internet. [ABSTRACT FROM AUTHOR]

Solid-state drives (SSDs), composed of NAND flash memories, are replacing hard disk drives (HDDs) rapidly. In addition, storage class memories (SCMs) bridge the bandwidth gap between DRAM and NAND flash, thus introducing SCM to SSD further improves the solid storage performance. Different from schemes that use SCM to store file system metadata or logical to physical mapping tables, two architectures 1) use SCM as a write-back non-volatile memory (NVM) based cache, 2) use SCM as a storage device are presented in this paper. Since SCM chip latency varies due to memory device and circuit design, three SSD data management algorithms are evaluated under five SCM chip design scenarios to provide useful design guidelines of SCM/NAND flash hybrid SSD. SCM interface and capacity requirement are also analyzed. From the experimental results, less than 10% of the SCM/NAND flash capacity ratio is enough for SCM chips with 500 ns read and 5 μs write latency to boost NAND flash-only SSD speed by over 10 times when workloads own high IO skew1. [ABSTRACT FROM PUBLISHER]

A novel error correction scheme, called reset-check-reverse-flag (RCRF), is proposed to improve the reliability of storage class memories (SCMs). RCRF divides the conventional Bose-Chaudhuri-Hocquenghem (BCH) code length into multiple subsections. One flag bit is added to each subsection to correct program errors. By reversing the flag bit and user data, at least one reset error in each subsection can be recovered. A 4 Mbit carbon nanotube (CNT) based nano-random access memory (NRAM) cell array is measured to verify this scheme. During 10^8 write cycles, it is demonstrated that RCRF reduces the program bit error rate (BER) by 50% and only requires 0.4% extra array area for the flag bits. Next, BCH ECC is applied after RCRF to correct the remaining errors. Compared with the conventional BCH ECC-only approach, the proposed combination of RCRF and BCH ECC reduces parity overhead by 35% and ECC decoding latency by 16%. Therefore, RCRF is especially suited for read-intensive types of data storage, such as video and audio. On the other hand, for high endurance applications, RCRF and BCH ECC is also effective to improve the cycling reliability of resistive memories, and 50 times endurance extension is demonstrated for a 50 nm AlxOy resistive RAM (ReRAM) test chip. [ABSTRACT FROM PUBLISHER]

In this article, we comprehensively review recent progress in the ReRAM cell technology for 3D integration focusing on a material/device level. First we briefly mention pioneering work on high-density crossbar ReRAM arrays which paved the way to 3D integration. We discuss the two main proposed 3D integration schemes-3D horizontally stacked ReRAM vs 3D Vertical ReRAM and their respective advantages and disadvantages. We follow with the detailed memory cell design on important work in both areas, utilizing either filamentary or interface-limited switching mechanisms. We also discuss our own contributions on HfO-based filamentary 3D Vertical ReRAM as well as TaO/TiO bilayer-based self-rectifying 3D Vertical ReRAM. Finally, we summarize the present status and provide an outlook for the nearterm future. [ABSTRACT FROM AUTHOR]

Storage class memory (SCM) has the potential to revolutionize the memory landscape by its non-volatile and byte-addressable properties. However, there is little published work about exploring its usage for modern virtualized cloud infrastructure. We propose SCM-vWrite, a novel architecture designed around SCM, to ease the performance interference of virtualized storage subsystem. Through a case study on a typical virtualized cloud system, we first describe why current writeback manners are not suitable for a virtualized environment, then design and implement SCM-vWrite to improve this problem. We also use typical benchmarks and realistic workloads to evaluate its performance. Compared with the traditional method on a conventional architecture, the experimental result shows that SCM-vWrite can coordinate the writeback flows more effectively among multiple co-located guest operating systems, achieving a better disk I/O performance without any loss of reliability. [ABSTRACT FROM AUTHOR]

Various emerging resistive memory technologies, such as phase change memory, have drawn attention in recent decades because they provide persistency, byte-addressability, low latency near that of DRAM, and high density.Storage-class memory(SCM) is the class of these memory technologies that have the best memory and storage properties. SCM can be accessed directly via load and store instructions because it is placed on a memory bus. In this paper, we introduce SCM in the context of emerging non-volatile memory technologies and review the efforts that have been made to utilize SCM in computer systems and exploit it for performance or reliability purposes. We also discuss the challenges and opportunities that accompany adopting SCM in computer systems. We focus more on issues of exploiting SCM because its potential for computer systems and applications is substantial, and accordingly, many more studies are expected. [ABSTRACT FROM PUBLISHER]

After decades of a cache, DRAM, and disk data storage hierarchy, new memory technologies are promising nonvolatility, high endurance, and fine-grained data access--all of which could, with some preparation, enable a new storage paradigm in server systems. [ABSTRACT FROM PUBLISHER]

Phase-change memory (PCM) is the best candidate for the storage device of next-generation mobile consumer electronics. PCM has the potential to replace NAND flash memory, due to its non-volatility, in-place programmability, and low power consumption. Even though the lifetime of PCM is longer than that of flash memory, wear leveling is still required to cope with the non-uniformity of storage workload or malicious attack. In this paper, a novel wear-leveling algorithm for PCM storage is proposed, where more physical pages are allocated to frequently updated logical pages, to balance the wear counts of PCM cells. In comparison with the previous techniques, the proposed algorithm improved the lifetime of PCM by at maximum 14 times and on average 8 times. [ABSTRACT FROM AUTHOR]

Modern computer systems have been built around the assumption that persistent storage is accessed via a slow, block-based interface. However, emerging nonvolatile memory technologies (sometimes referred to as storage class memory (SCM)), are poised to revolutionize storage systems. The SCM devices can be attached directly to the memory bus and offer fast, fine-grained access to persistent storage. In this article, we propose a new file system--SCMFS, which is specially designed for Storage Class Memory. SCMFS is implemented on the virtual address space and utilizes the existing memory management module of the operating system to help mange the file system space. As a result, we largely simplified the file system operations of SCMFS, which allowed us a better exploration of performance gain from SCM. We have implemented a prototype in Linux and evaluated its performance through multiple benchmarks. The experimental results show that SCMFS outperforms other memory resident file systems, tmpfs, ramfs and ext2 on ramdisk, and achieves about 70% of memory bandwidth for file read/write operations. [ABSTRACT FROM AUTHOR]

Recently, interest in incorporating Storage Class Memory (SCM), which blurs the distinction between memory and storage, into mainstream computing has been increasing rapidly. In this paper, we address the emerging questions regarding the use of SCM. Based on an embedded platform that employs FeRAM, a type of SCM, we present our findings. In summary, by introducing SCM, power efficiency improves while performance is degraded. We also show that such performance degradations may be removed with operating system level schemes that fully exploit the characteristics of SCM. Finally, we present permanent computing that supports lightweight system on/off capabilities by using SCM. [ABSTRACT FROM AUTHOR]

Phase change memory (PCM) has opportunities of various applications on the premise of its high performance operations, which are still to develop with innovations such as change of a memory material. In respects of high-speed and high-scalability memory characteristics, δ-phase Ge-doped SbTe (GeST) materials stand as highly promising candidates. An overview of the material and device characteristics of these materials is presented primarily based on our recent experimental and computational studies and with a particular regard to their Sb-to-Te ratio (STR) dependence. TEM images of the δ-phase GeST microstructures of varying STR and a highly scaled PCM cell with a δ-phase GeST of high STR. [ABSTRACT FROM AUTHOR]

We explore the possibility of deploying storage class memory (SCM) into the I/O path as a file system metadata store and examine what effects it has on the performance of portable computing systems. In this regard, we develop a new flash memory-based file system that stores all metadata in SCM, while storing all file data in flash memory. In so doing, we make two contributions in this work. First, we present a model that analyzes the amount of SCM that is needed for specific flash memory storage capacity. Second, we present quantitative experimental results that show how much performance gains are possible by exploiting SCM in terms of I/O performance, energy efficiency and lifetime of the underlying flash memory. Compared to YAFFS, a popular flash memory-based file system, we show that system performance is improved by a maximum of around 320, 260, and 180% in terms of I/O performance, energy efficiency and lifetime of the Flash memory, respectively, for the realistic workloads that we considered. [ABSTRACT FROM AUTHOR]