Search

Summary: This paper proposes a step‐down alternating current (AC)/direct current (DC) converter with current‐doubler rectification stage, therefore suitable for low‐voltage and high‐power applications. High power factor and low harmonic distortion can be achieved by simply applying sinusoidal pulse‐width modulation (SPWM) control. A laboratory prototype circuit rated at 2 kW, 180‐V output voltage is designed and built to verify the circuit feasibility. Experimental results confirm that the power factor is ubiquitously higher than 0.99 from 500 W to the full load. The total harmonic distortion at the full load is less than 5%, which meet the harmonic specifications of IEC 61000‐3‐2 and IEC 61000‐3‐12. [ABSTRACT FROM AUTHOR]

The conventional topological approach to eliminate the multiple-input DC voltage requirement in multilevel inverter configurations for synthesizing high-output voltage levels is to deploy split capacitor banks at the input terminal. This method stipulates a less expensive, light weight, and reduced size inverter system. However, the excessive demand for several capacitor banks and the complex voltage balancing strategy associated with this conceptual approach poses numerous limitations in their deployment. In view of these drawbacks, this study proposes a self-balanced, single-phase, nine-level switched-capacitor-based inverter topology consisting of a single-input DC voltage, an auxiliary circuit, and an H-bridge circuit unit. A commensurate single carrier-based sinusoidal pulse-width modulation scheme is developed for the proposed power circuit control, enabling the synthesis of a nine-level output voltage waveform whose amplitude is four times the input voltage value. Detailed power circuit operations and switching functions are adequately provided in the proposed topology. A comparison between the proposed inverter and its recent counterparts in terms of component count, cost involvement, and output voltage-boosting ability is duly carried out using Python data visualization. Results reveal that the proposed inverter competes well in these three criteria. For varying R–L load values, the inverter has the capability of high active and reactive power delivery. Its dynamic response for step changes in the modulation index under these power-mode operations is presented in this paper. For high active power-mode operation, efficiencies of 98.27% and 98.92% under light- and heavy-load conditions, respectively, are obtained on a 3-kW-rated inverter prototype. [ABSTRACT FROM AUTHOR]

The classical four-level nested neutral point-clamped (4L NNPC) inverter-leg is a hybrid of the flying-capacitor and diode-clamped 4L-inverter-leg configurations. Though uniform reduced voltage stress (1/3 of input voltage) on constituting switches is evident in the 4L NNPC inverter-leg, trails of the drawbacks of the diode-clamping concept still exist. With the significantly rated off-the-shelf IGBT switch modules (6.5 kV, 1200 A), chances of deployment of the newly evolved Four-Level Nested T-Type inverter (4L NTTI) in certain applications is high. Compared with the classical 4L NNPC inverter, 4L NTTI involves a smaller number of power switches and low conduction losses. However, in 4L NTTI, two of the six active switches have a blocking voltage rating of 2/3 of the input voltage. Considering this limiting topological feature in 4L NTTI, a six-switch inverter-leg for the four-level active neutral point-clamped (4L ANNPC) inverter is presented in this paper. In the proposed 4L ANNPC inverter-leg, only one switch has a voltage stress of 2/3 of the input voltage. This ameliorated voltage stress translates to low-cost and -loss inverter implementation. The operational characteristics and competitiveness of the 4L ANNPC inverter are analyzed in detail and demonstrated with a prototype.

In view of reducing the number of inverter legs that provide dual-phase, three-level output voltages (as may be needed in an uninterruptible power supply), and that also provide a wide range of output frequencies (as needed in an advanced motor drive system with wide speed ranges), a three-level, dual-phase inverter topology is presented in this paper. Its three-level attribute was based on the F-type inverter topological concept, and its dual-output feature was based on the common representation of the inverter-leg concept. The proposed inverter could deliver single- and three-phase voltages to corresponding one- and three-phase loads, in common or different frequency modes of operation. A boundary between these modes of operation was established for the proposed inverter. An additional possibility of either operation in the one-phase or the three-phase system was offered by the inverter configuration. A modified carrier-based sinusoidal pulse-width modulation scheme is presented for the control of the inverter topology. The performances of the dual-phase inverter are given in the simulation results and demonstrated with a hardware prototype. [ABSTRACT FROM AUTHOR]

Multiplicity of the triangular carrier signals is a criterion for the extension of sinusoidal pulse-width modulation, SPWM, to a number of output voltage levels per phase-leg in cascaded H-bridge (CHB) multilevel inverter (MLI). Considering medium and high voltage applications where appreciable number of output voltage levels from CHB MLI is needed, commensurate high number of carrier signals in either classical level- or phase-shifted SPWM scheme for this inverter is inevitable. High-quality output waveforms from CHB MLI system demands precise synchronization of these multi-carrier signals. Sampling issues, memory constraints and computational delays pose difficulties in achieving this synchronization for real-time digital implementation. This study presents a PWM template for CHB MLI. The developed control concept generates adequate modulation templates for CHB inverter wherein a sinusoidal modulating waveform is modified to fit in a single triangular carrier signal range. These templates can be used on CHB inverter of any level with no further control modification. Nearly even distribution of switching pulses, equal sharing of the overall real power among the constituting power switches and enhanced output voltage quality were achieved with the proposed modulation. For a 3-phase, 7-level CHB, simulation and experimental results, for an R-L load, were presented.

Given the recently available IGBT switch modules up to 6.5 kV, 1200 A rating, the prospect of the diode-free variant topology of the three-level neutral-point-clamped (3-level T-type, NPC) inverter in certain medium-voltage applications is bright due to its small part count and low conduction losses compared to the diode-clamped NPC inverter. However, within this voltage range, the input dc voltage rating of 50% of the switches per inverter phase-leg still poses limitations to the deployment of a 3-level T-type inverter. In view of these limitations, a reconfigured four-switch per phase-leg power circuit for a 3-level inverter (F-type) is presented in this article. The common node of the bidirectional switch in the T-type inverter is explored to have only one power switch rated at input dc voltage and three switches rated at half the input dc voltage per inverter leg. This reduced voltage stress has inverter cost and loss implications. The performances and competitiveness of the three-level F-type inverter are analyzed in detail and demonstrated with a hardware prototype. Results reveal that it has the potentials of being considered a real alternative to 3-level T-type inverters for certain low- and medium-voltage applications. [ABSTRACT FROM AUTHOR]

In view of reducing the number of inverter legs that provide dual-phase, three-level output voltages (as may be needed in an uninterruptible power supply), and that also provide a wide range of output frequencies (as needed in an advanced motor drive system with wide speed ranges), a three-level, dual-phase inverter topology is presented in this paper. Its three-level attribute was based on the F-type inverter topological concept, and its dual-output feature was based on the common representation of the inverter-leg concept. The proposed inverter could deliver single- and three-phase voltages to corresponding one- and three-phase loads, in common or different frequency modes of operation. A boundary between these modes of operation was established for the proposed inverter. An additional possibility of either operation in the one-phase or the three-phase system was offered by the inverter configuration. A modified carrier-based sinusoidal pulse-width modulation scheme is presented for the control of the inverter topology. The performances of the dual-phase inverter are given in the simulation results and demonstrated with a hardware prototype.

This article presents a carrier-based pulse-width modulation (PWM) template for a 5-level, H bridge-based cascaded multilevel inverter (MLI). The developed control concept generates adequate modulation template for this inverter topology wherein a sinusoidal modulating waveform is modified to fit in a single triangular carrier signal range. With this modulation approach, classical multiplicity and synchronization of the triangular carrier signals criterion for the extension of sinusoidal pulse-width modulation, SPWM, to several cascaded 5-level, H-bridge-based MLI topology are removed. The proposed template can be used on the inverter configuration of any level with no further control modification. Nearly even distribution of switching pulses and equalized individual cascaded cell output power were achieved with the proposed modulation scheme. Three 5-level, H-bridge-based MLI units were cascaded for 1-phase, 13-level inverter operation; simulation and experimental results are adequately presented.

Supraharmonic is an inevitable power quality issue, with the rapid development of power electronic technologies, receiving more and more attention. Firstly, this study analyses the supraharmonic emission mechanism of voltage source converter (VSC) based on sinusoidal pulse‐width modulation. The mathematical analysis shows that the supraharmonics emitted by grid‐connected VSC mainly distribute near the integer multiple of its switching frequency, and grid‐connected VSCs are essentially supraharmonic voltage sources. Then, this study proposes the supraharmonic equivalent circuit model of multiple VSCs grid‐connected system, by modelling grid‐connected VSCs as supraharmonic voltage sources and connecting them in parallel with the LCL filters. Based on the proposed model, considering the primary and secondary emissions, a method is proposed to evaluate the supraharmonic current emission of one VSC and the total supraharmonic current emission flowing into the grid. Finally, simulation and field measurements show that the proposed method can effectively evaluate the supraharmonic emission levels of multiple VSCs grid‐connected systems. [ABSTRACT FROM AUTHOR]

This paper discusses the difference between the three fundamental types of multilevel inverter (MLI) topologies, which are the neutral-point-clamped, the flying capacitors and the cascaded H-bridges. The sinusoidal pulse width modulation technique was used to simulate the output voltages and currents of the MLI inverters. The total harmonic distortion (THD) was estimated for each topology and each voltage level. Moreover, the simulation results indicate that the cascaded structure exhibited a lower THD value even when increasing the number of the output voltage. Furthermore, a new key parameter was defined as cost efficiency factor and used to compare the three topologies. Evaluation results of this factor indicate that the cascaded structure was the most advantages as it reduces stress effect on the inverter switches by eliminating the power diodes and capacitors. [ABSTRACT FROM AUTHOR]

This paper presents a novel digital sinusoidal pulse-width modulation (SPWM) technique based on immediate calculation of duty cycle count (DCC) values of pulses with high speed Harvard architecture based RISC controllers. The DCC values are calculated with the multiplication of an instant modulation index count (MIC) and a preloaded sine count value (SCV) table in the program memory of the controller. The proposed technique overcomes the drawbacks of overhead time in digital carrier-reference based technique and large memory requirement in look-up table technique. The proposed technique is effective where frequent change of modulation index (MI) of SPWM is essential like grid-connected inverter applications. The effectiveness of the proposed technique is verified with both Proteus VSM based simulation and dsPIC based experiment. [ABSTRACT FROM AUTHOR]

The causes of the appearance of dc components in the output voltage of voltage-source inverters controlled by the method of pulse-width modulation (PWM) are shown. Two different variants to compensate for the causes of appearance of the dc component for a sinusoidal PWM and one variant for a vector PWM are suggested. [ABSTRACT FROM AUTHOR]

This paper presents an all-digital concept for sinusoidal pulse-width modulation (SPWM) generation that uses modern arithmetic algorithms to impose a sinusoidal variation of the switching pulses that control the power transistors of a single-phase inverter, thus improving the linear characteristics of the inverter output signal. The developed modulation strategy is given a mathematical description, which can then be modelled and synthesised on field programmable gate arrays (FPGAs). The only existing harmonics present within the spectrum of the final signal are the multiple of the switching frequency. The order of these harmonics is so high (switching frequency related with output frequency sidebands), that a filter can easily be designed to reject these frequencies. The ability to accurately control the output characteristics of the inverter within 1% and also maintain less than 1% harmonic distortion, demonstrates the feasibility of the digital synthesiser. [ABSTRACT FROM AUTHOR]