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Memristor is an electronic device, which corresponds to a switch translating memory data (synapse) into resistance values. Scientists made a switch with a combination of titanium dioxide (Tio2) and oxygen deficient TiO2 to create a metal-insulator transition mechanism to make a device with nonlinear conductive states Ron and Roff. This work presents the memory storing capability of memristor by utilizing an equivalent experimental setup of steel balls array. An experiment exhibits an identical memristive mechanism of memristor device where the nonlinear conductive states along an array of steel balls describes an exact mechanism of memristor's functionality. Via utilizing an identical setup, we depict electric and magnetic field compatibility at memristor's pinched (on & off) regions. It shows that how memristor stores synaptic information by means of resistance values at its pinched (on & off) conducting regions. The aim of this effort is to provide technical support to conceive a memristor as a resistive memory storage device, which changes its resistance values with respect to applied voltage (multiple synaptic weights). [ABSTRACT FROM AUTHOR]

Highly flexible, nonvolatile resistive switching-based memory devices with a hierarchical thin-film architecture were fabricated using a low-temperature, cost-efficient solution processing technique. The device structure consists of an ITO-coated flexible PET substrate as the bottom electrode and a PMMA-embedded reduced-graphene/ZnO nanoparticle (NP) (rGO/ZnO NP) heterostructure as the flexible active layer. Besides, a PMMA-embedded graphene oxide (GO/PMMA)-based device was also fabricated as a reference. The operating voltage of this device is limited within ±2 V, whereas the ON/OFF current ratio is ∼106, which is ∼103 times higher than the reference device. The device also exhibited excellent endurance and retention characteristics, with no significant degradation for more than 50 cycles. Besides, the retention time of this device is ∼104 s, which is several times more than that of the reference device. These electrical performance enhancements were attributed to the multifunctionality introduced by the rGO/ZnO NP heterostructures, which combine the excellent conductivity of rGO nanosheets with charge trapping and transport properties and high electron mobility of ZnO nanostructures. A model based on the energy band of the components of this composite material has been proposed for a better understanding of this mechanism. Flexibility studies exhibited stable device performance for an extreme bending radius of 6 mm. The resistance of the device in ON and OFF states did not show any significant change even after 1000 bending cycles, thus establishing the device as an excellent memory candidate for flexible electronic applications such as flexible displays and sensors, wearable devices, implantable medical devices, and portable diagnostic devices. [ABSTRACT FROM AUTHOR]

Nonvolatile memory devices play a pivotal role within sensor systems, serving as integral components that significantly enhance the efficiency, reliability, and overall performance of these advanced technologies. In this paper, we present a nonvolatile oxide-based resistive memory device employing a chemical displacement technique (CDT) for copper thin film as the metal electrode. The utilization of CDT-Cu offers several distinct advantages, including costeffectiveness, high selectivity, and the ability to operate at lower temperatures. Notably, the CDT-Cu film exhibits a rough surface, which proves advantageous for facilitating the formation of filament pathways in the electrochemical metallization (ECM)-type resistive random-access memory (ReRAM) device. We systematically investigated the surface roughness of CDT-Cu samples, varying chemical displacement time, to shed light on the influence of the Cu electrode on the electrical performance of the resistive memory devices. The findings indicate that devices subjected to shorter CDT times, which yields rougher surfaces, demonstrate lower operation electric fields and enhanced reliability. This is attributed to the reduced voltage requirements, effectively mitigating the impact of Joule heating during device operation. [ABSTRACT FROM AUTHOR]

In recent years, resistive memories have emerged as a pivotal advancement in the realm of electronics, offering numerous advantages in terms of energy efficiency, scalability, and non-volatility [1]. Characterized by their unique resistive switching behavior, these memories are well-suited for a variety of applications, ranging from high-density data storage to neuromorphic computing [2]. Their potential is further enhanced by their compatibility with advanced semiconductor processes, enabling seamless integration into modern electronic circuits [3]. A particularly promising avenue for resistive memory lies in its integration at the Back-End-of-Line (BEOL) stage of semiconductor manufacturing [4]. BEOL integration involves processes that occur after the fabrication of the transistors, primarily focusing on creating interconnections that electrically link these transistors. Integrating resistive memories at this stage can lead to compact, efficient, and high-performance architectures, pivotal for in-memory computing applications where data storage and processing are co-located [5]. This paper studies three ways to integrate TiOx-based resistive memory into passive crossbar array structures, using chemical mechanical polishing (CMP) processes, focusing on identifying the optimal integration techniques.

Atomic layer deposition (ALD) is widely utilized in the modern microelectronic industry due to its capability of depositing thin films with exceptional conformality and uniformity. The first Russian ALD system Izofaz TM 200-01 has already been successfully employed in the deposition of various materials, particularly high-k dielectrics such as aluminum oxide. This study presents the computer modeling-based investigation of the ALD process for hafnia and zirconia oxide films using the aforementioned ALD system. The growth per cycle was determined to be 1.1 Å/cycle, while the within-wafer nonuniformity was measured to be 1.2% or lower. These results are consistent with previously reported results and, more importantly, with experimental results also collected in this work, and demonstrate a high level of quality. Additionally, the electrical and physical properties of hafnia oxide films, including their potential application in ReRAM-like structures, were investigated. The storage elements based on hafnia oxide exhibited stable performance over 3 million switching cycles. Consequently, the Izofaz TM 200-01 ALD system has been proven effective in the deposition of thin films composed of hafnia and zirconia oxides. [ABSTRACT FROM AUTHOR]

Atomic layer deposition (ALD) is widely utilized in the modern microelectronic industry due to its capability of depositing thin films with exceptional conformality and uniformity. The first Russian ALD system Izofaz TM 200-01 has already been successfully employed in the deposition of various materials, particularly high-k dielectrics such as aluminum oxide. This study presents the computer modeling-based investigation of the ALD process for hafnia and zirconia oxide films using the aforementioned ALD system. The growth per cycle was determined to be 1.1 Å/cycle, while the within-wafer nonuniformity was measured to be 1.2% or lower. These results are consistent with previously reported results and, more importantly, with experimental results also collected in this work, and demonstrate a high level of quality. Additionally, the electrical and physical properties of hafnia oxide films, including their potential application in ReRAM-like structures, were investigated. The storage elements based on hafnia oxide exhibited stable performance over 3 million switching cycles. Consequently, the Izofaz TM 200-01 ALD system has been proven effective in the deposition of thin films composed of hafnia and zirconia oxides. [ABSTRACT FROM AUTHOR]

Memristors are recognized as crucial devices for future nonvolatile memory and artificial intelligence. Due to their typical neuron-synapse-like metal–insulator–metal(MIM) sandwich structure, they are widely used to simulate biological synapses and have great potential in advancing biological synapse simulation. However, the high switch voltage and inferior stability of the memristor restrict the broader application to the emulation of the biological synapse. In this study, we report a vertically structured memristor based on few-layer MoS 2 . The device shows a lower switching voltage below 0.6 V, with a high ON/OFF current ratio of 10 4 , good stability of more than 180 cycles, and a long retention time exceeding 3 × 10 3 s. In addition, the device has successfully simulated various biological synaptic functions, including potential/depression propagation, paired-pulse facilitation (PPF), and long-term potentiation/long-term depression (LTP/LTD) modulation. These results have significant implications for the design of a two-dimensional transition-metal dichalcogenides composite material memristor that aim to mimic biological synapses, representing promising avenues for the development of advanced neuromorphic computing systems. [ABSTRACT FROM AUTHOR]

By doping a dielectric layer material and improving the device's structure, the electrical characteristics of a memristor can be effectively adjusted, and its application field can be expanded. In this study, graphene quantum dots are embedded in the dielectric layer to improve the performance of a starch-based memristor, and the PMMA layer is introduced into the upper and lower interfaces of the dielectric layer. The experimental results show that the switching current ratio of the Al/starch: GQDs/ITO device was 102 times higher than that of the Al/starch/ITO device. However, the switching current ratio of the Al/starch: GQDs/ITO device was further increased, and the set voltage was reduced (−0.75 V) after the introduction of the PMMA layer. The introduction of GQDs and PMMA layers can regulate the formation process of conductive filaments in the device and significantly improve the electrical performance of the memristor. [ABSTRACT FROM AUTHOR]

The rapid development of artificial intelligence has significantly accelerated computational calculation and enlarged the demands in information storage. Therefore, high‐performance memory devices based on new architectures and functionalities, such as resistive memory, transistor memory, and phase change memory, along with their applications in neuromorphic computing and artificial synapse have arisen extensive interest among researchers. In order to improve the memory performance, block copolymer electrets with diversified self‐assembled structures have been extensively developed, and their structure–performance properties have been investigated. Therefore, in this focused review, a variety of block copolymers combining incompatible polymers, such as hydrophilic/hydrophobic, polar/nonpolar, and conjugated/insulating polymers, are introduced in this focused review. The design concepts and recent advances of block copolymers in nonvolatile memory and artificial synapses were addressed. With these divergent structure designs, block copolymers are regarded as potential candidates to provide high performance in memory device applications. This review sheds light on the great potential and importance of block copolymers for optoelectronic device applications. [ABSTRACT FROM AUTHOR]

Recent advances in developing beyond von Neumann architectures have moved the memristive devices to the forefront as one of the key enablers to realizing memristive computing-in-memory (mCIM) structures, which shows a great promise to boost the energy-efficiency and the performance of artificial intelligence (AI) chips. In this study, by considering the interactions between devices, circuits, and systems in the mCIM design, we propose several cross-layer design techniques, including (1) the BL-SL interactive forming protection (BSIFP) circuit that can reduce the voltage drop on the selected transistor, suppress the current overshoot by 65.96%, and improve the bit-cell density by more than 10.19%, (2) the clamping transistor trimming scheme (CTTS) to prevent the multiply-and-accumulate (MAC) signal margin degradation from chip-to-chip resistance variations, and (3) dynamic input-parallelism and output-precision (DIPOP) that can reduce the energy cost by 22.92% in a typical inference task with negligible accuracy loss. The results demonstrate the significant role of the cross-layer-interactive approach and provide a preliminary guideline for highly-efficient mCIM design. [ABSTRACT FROM AUTHOR]

The resistive switching layer of CeO2-x-TiO2 film was prepared on the FTO substrate by the sol-gel method and spin coating technique, and the Al/CeO2-x-TiO2/FTO resistive switching device was fabricated by depositing thin Al top electrode on the surface of the CeO2-x-TiO2 film. The crystal phase composition and crystal structure of CeO2-x-TiO2 thin films were characterized by XRD and XPS. The results show that the resistive switching layer is mainly composed of TiO2 and CeO2-x. Compared with Al/CeO2/FTO devices, the electrical performance of Al/CeO2-x-TiO2/FTO device is improved. I-V test shows that Al/CeO2-x-TiO2/FTO device has bipolar resistance variation characteristics without forming process. The resistive behavior with different CeO2-x-TiO2 thicknesses was carried out. The results show that the low resistance state of Al/CeO2-x-TiO2/FTO device shows ohmic conduction mechanism under different CeO2-x-TiO2 film thicknesses. As the thickness of CeO2-x-TiO2 increases, the essential change of resistance mechanism occurs in high resistance state. The resistance mechanism of the device changes from oxygen vacancy conductive filament mechanism to charge trapping/releasing mechanism by defect controlled. It was found that the AlOxlayer at the Al/CeO2-x-TiO2 interface is critical to the transformation of resistance mechanism, and the thickness of AlOx layer changes the device from "digital type" to "analog type".

Resistive-switching-based memory devices meet most of the requirements for use in next-generation information and communication technology applications, including standalone memory devices, neuromorphic hardware, and embedded sensing devices with on-chip storage, due to their low cost, excellent memory retention, compatibility with 3D integration, in-memory computing capabilities, and ease of fabrication. Electrochemical synthesis is the most widespread technique for the fabrication of state-of-the-art memory devices. The present review article summarizes the electrochemical approaches that have been proposed for the fabrication of switching, memristor, and memristive devices for memory storage, neuromorphic computing, and sensing applications, highlighting their various advantages and performance metrics. We also present the challenges and future research directions for this field in the concluding section. [ABSTRACT FROM AUTHOR]

Resistive memories are outstanding electron devices that have displayed a large potential in a plethora of applications such as nonvolatile data storage, neuromorphic computing, hardware cryptography, etc. Their fabrication control and performance have been notably improved in the last few years to cope with the requirements of massive industrial production. However, the most important hurdle to progress in their development is the so‐called cycle‐to‐cycle variability, which is inherently rooted in the resistive switching mechanism behind the operational principle of these devices. In order to achieve the whole picture, variability must be assessed from different viewpoints going from the experimental characterization to the adequation of modeling and simulation techniques. Herein, special emphasis is put on the modeling part because the accurate representation of the phenomenon is critical for circuit designers. In this respect, a number of approaches are used to the date: stochastic, behavioral, mesoscopic..., each of them covering particular aspects of the electron and ion transport mechanisms occurring within the switching material. These subjects are dealt with in this review, with the aim of presenting the most recent advancements in the treatment of variability in resistive memories. [ABSTRACT FROM AUTHOR]

Matrix-based computing is ubiquitous in an increasing number of present-day machine learning applications such as neural networks, regression, and 5G communications. Conventional systems based on von-Neumann architecture are limited by the energy and latency bottleneck induced by the physical separation of the processing and memory units. In-memory computing (IMC) is a novel paradigm where computation is performed directly within the memory, thus eliminating the need for constant data transfer. IMC has shown exceptional throughput and energy efficiency when coupled with crosspoint arrays of resistive memory devices in open-loop matrix-vector-multiplication and closed-loop inverse-matrix-vector multiplication (IMVM) accelerators. However, each application results in a different circuit topology, thus complicating the development of reconfigurable, general-purpose IMC systems. In this article, we present a generalized closed-loop IMVM circuit capable of performing any linear matrix operation by proper memory remapping. We derive closed-form equations for the ideal input-output transfer functions, static error, and dynamic behavior, introducing a novel continuous-time analytical model allowing for orders-of-magnitude simulation speedup with respect to SPICE-based solvers. The proposed circuit represents an ideal candidate for general-purpose accelerators of machine learning.

Organic–inorganic or inorganic metal halide materials have emerged as a promising candidate for a resistive switching material owing to their ability to achieve low operating voltage, high on–off ratio, and multi‐level switching. However, the high switching variation, limited endurance, and poor reproducibility of the device hinder practical use of the memristors. In this study, a universal approach to address the issues using a van der Waals metal contact (vdWC) is reported. By transferring the pre‐deposited metal contact onto the active layers, an intact junction between the metal halide and contact layer is formed without unintended damage to the active layer caused by a conventional physical deposition process of the metal contacts. Compared with the thermally evaporated metal contact (EVC), the vdWC does not degrade the optoelectronic quality of the underlying layer to enable memristors with reduced switching variation, significantly enhanced endurance, and reproducibility relative to those based on the EVC. By adopting various metal halide active layers, versatile utility of the vdWC is demonstrated. Thus, this vdWC approach can be a useful platform technology for the development of high‐performance and reliable memristors for future computing. [ABSTRACT FROM AUTHOR]

In this study, the dielectric layer of the xanthan gum resistive memory is treated by air plasma. Compared with the untreated original device, when the device is treated with plasma for 30 s, the activation energy is reduced from 0.17 to 0.13 eV, which helps to control the randomness of the path of trap hopping conduction. Thus, the average set voltage is reduced from 1.05 to 0.54 V, which makes the filament grow more easily. The fluctuation of I HRS decreased from 88.88% to 49.56%. This means that the uniformity and stability of the device can be effectively improved by the plasma treatment. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Materials Engineering / Cailiao Gongcheng is the property of Journal of Materials Engineering Editorial Office and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The ability of resistive memory (ReRAM) to naturally conduct vector–matrix multiplication (VMM), which is the primary operation carried out during the training and inference of neural networks, has caught the interest of researchers. The memristor crossbar is one of the desirable architectures to perform VMM because it offers various benefits over other memory technologies, including in-memory computing, low power, and high density. Direct downloading and chip-on-the-loop approaches are typically used to train ReRAM-based neural networks. In these methods, all weight computations are carried out by a host machine, and the computed weights are downloaded in the crossbar. It has been seen that the network does not deliver the same precision as promised by the host system once the weights have been downloaded. This is because crossbars contain a significant number of faulty memristors and suffer from cell resistance variations because of immature manufacturing technologies. As a result, a cell may not be able to take the exact weight values that the host system generates, and may lead to incorrect inferences. Existing techniques for fault-tolerant mapping either involve network retraining or employ a graph-matching strategy that comes with hardware, power, and latency overheads. In this paper, we propose a mapping method to tolerate the effect of defective memristors. In order to lessen the impact of faulty memristors, the mapping is done in a way that allows network weights to cover up faulty memristors. Further, this work prioritizes the different faults based on the frequency of occurrence. The mapping efficiency is found to increase significantly with low power, area and latency overheads in the proposed approach. Experimental analyses show considerable improvement as compared to state-of-the-art works.

Resistive memories are outstanding electron devices that have displayed a large potential in a plethora of applications such as nonvolatile data storage, neuromorphic computing, hardware cryptography, etc. Their fabrication control and performance have been notably improved in the last few years to cope with the requirements of massive industrial production. However, the most important hurdle to progress in their development is the so‐called cycle‐to‐cycle variability, which is inherently rooted in the resistive switching mechanism behind the operational principle of these devices. In order to achieve the whole picture, variability must be assessed from different viewpoints going from the experimental characterization to the adequation of modeling and simulation techniques. Herein, special emphasis is put on the modeling part because the accurate representation of the phenomenon is critical for circuit designers. In this respect, a number of approaches are used to the date: stochastic, behavioral, mesoscopic..., each of them covering particular aspects of the electron and ion transport mechanisms occurring within the switching material. These subjects are dealt with in this review, with the aim of presenting the most recent advancements in the treatment of variability in resistive memories.

Memristors are recognized as crucial devices for future nonvolatile memory and artificial intelligence. Due to their typical neuron-synapse-like metal–insulator–metal(MIM) sandwich structure, they are widely used to simulate biological synapses and have great potential in advancing biological synapse simulation. However, the high switch voltage and inferior stability of the memristor restrict the broader application to the emulation of the biological synapse. In this study, we report a vertically structured memristor based on few-layer MoS2. The device shows a lower switching voltage below 0.6 V, with a high ON/OFF current ratio of 104, good stability of more than 180 cycles, and a long retention time exceeding 3 × 103 s. In addition, the device has successfully simulated various biological synaptic functions, including potential/depression propagation, paired-pulse facilitation (PPF), and long-term potentiation/long-term depression (LTP/LTD) modulation. These results have significant implications for the design of a two-dimensional transition-metal dichalcogenides composite material memristor that aim to mimic biological synapses, representing promising avenues for the development of advanced neuromorphic computing systems.

By doping a dielectric layer material and improving the device’s structure, the electrical characteristics of a memristor can be effectively adjusted, and its application field can be expanded. In this study, graphene quantum dots are embedded in the dielectric layer to improve the performance of a starch-based memristor, and the PMMA layer is introduced into the upper and lower interfaces of the dielectric layer. The experimental results show that the switching current ratio of the Al/starch: GQDs/ITO device was 102 times higher than that of the Al/starch/ITO device. However, the switching current ratio of the Al/starch: GQDs/ITO device was further increased, and the set voltage was reduced (−0.75 V) after the introduction of the PMMA layer. The introduction of GQDs and PMMA layers can regulate the formation process of conductive filaments in the device and significantly improve the electrical performance of the memristor.

Transition metal doped Zinc oxide (ZnO) thin films with wide band gap semiconducting nature have diverse range of applications including, gas sensors, optical and optoelectronic devices, electronics and spintronics spintronic devices etc. In the present study, Manganese (Mn)‐doped ZnO thin films deposited on glass substrates using RF‐magnetron sputtering have been investigated for their optical and electrical behavior aiming at resistive random access memory applications. To study the influence of Mn doping and correlation between the structural and the physical properties of the films, the samples were characterized by X‐ray Diffraction (XRD), Raman spectroscopy, Field Emission Scanning Electron Microscopy (FESEM), Energy Dispersive X‐ray Spectroscopy (EDS), UV‐VIS spectrophotometry and X‐ray photoelectron spectroscopy (XPS). The films are found to be crystalline and a decrease in lattice parameter from 2.6049 Å to 2.5845 Å, an increase in optical band gap from 3.27 eV to 3.35 eV and a decrease in Urbach energy from 0.222 eV to 0.171 eV, is observed with increase in Mn‐concentration. The electrical performance of the film with highest Mn‐content is found to be more suitable for resistive memory applications. Tailoring the electrical behavior of the film by incorporating Mn as dopant is an important approach to find suitable material combination for novel memory devices. [ABSTRACT FROM AUTHOR]

New ambipolar polyimides containing pendant electron-acceptor groups of the thioxanthenone series are shown to have a high thermal stability (up to 400 °C), a good film-forming ability, and a band gap 3.15 < Eg < 3.42 eV (T = 295 K). By spin-coating of polyimide solutions onto p++-Si(100) silicon plates, model resistive memory devices of the metal–dielectric–metal type with an average polymer layer thickness of ~40 nm and aluminum counter electrodes are made and tested. The devices demonstrate non-volatile memory of the WORM type. [ABSTRACT FROM AUTHOR]

Herein, a comprehensive investigation into the optical, local chemical state, and electrical properties of the less explored magnesium oxide (MgO) are presented for resistive switching data storage applications in reference to the well‐documented hafnium oxide (HfO2). The observed local chemical state from X‐ray photoelectron spectroscopy (XPS) analysis yields a nonlattice oxygen peak in O 1s spectra, indicating the resistive switching potential of polycrystalline MgO analogous to the amorphous HfO2 as‐deposited thin films. The optical investigation through UV–visible spectroscopic and photoluminescence examination reveals the high transmissivity of HfO2 (84–98%) and MgO (86–88%) thin films in visible and near‐infrared domains, with a high bandgap of 5.6 and 4.2 eV, respectively, implying the possibility of two distinct stable states essential for resistive switching phenomena. Additionally, the electrical characterization manifests bipolar switching phenomena in HfO2 and MgO metal–oxide–metal stacks with SET transitions at 0.6 and 0.5 V, followed by RESET transitions at −0.6 and −0.5 V, respectively. Both oxides in respective stacks exhibit dominant Ohmic conduction in high‐resistive and low‐resistive regions during positive and negative bias. These observations propose MgO as a preferable resistive switching material for nonvolatile data storage applications, showing similar properties of widely studied HfO2. [ABSTRACT FROM AUTHOR]

In this study, we demonstrate multimemory functions of anAg/SiOx/n+-Si device, including nonvolatile (NV) write-once-read-many-times (WORM), NV bipolar, NV unipolar, and volatile resistive switching (RS) characteristics. The SiOx layer is grown using a dry oxidation process. Different RS features are obtained by modulating the compliance current during device operation. The resistance switch from the OFF to ON state, corresponding to a set process, is observed in the positive voltage region, which indicates that the Ag cations are responsible for the RS process. When the Ag/SiOx/n+-Si memory switches to the ON state, an Ag conductive bridge (CB) in the SiOx layer is indeed observed under transmission electron microscopy (TEM) examination. A CB-based model is used to explain the different RS behaviors of the Ag/SiOx/n+-Si resistive memory. [ABSTRACT FROM AUTHOR]

Organic-resistance random access memory has high application potential in the field of next-generation green nonvolatile memory. Because of their biocompatibility and environmental friendliness, natural biomaterials are suitable for the fabrication of biodegradable and physically transient resistive switching memory devices. A flexible memory device with physically transient properties was fabricated with silver ions and egg albumen composites as active layers, which exhibited characteristics of write-once-read-many-times (WORM), and the incorporation of silver ions improved the ON/OFF current ratio of the device. The device can not only complete the logical operations of "AND gate" and "OR gate", but its active layer film can also be dissolved in deionized water, indicating that it has the characteristics of physical transients. This biocompatible memory device is a strong candidate for a memory element for the construction of transient electronic systems. [ABSTRACT FROM AUTHOR]

In this letter, a high-performance dual-function device fabricated using one single SiO2 resistive switching layer is demonstrated. The SiO2 layer is sandwiched between Ag and n+-Si to form an Ag/SiO2/n+-Si dual-function device with memory and selector features. As a memory device, it shows a high memory window of 107, and can continually operate over 104 cycles. Nonvolatility and stability are examined using a retention and a stress test for 104 s. Measurement at 85°C is performed to further confirm the reliability of the memory feature. As a selector, the device shows an extremely low leakage current of 0.1 pA, a high selectivity of 106, and a low turn-on energy consumption of 0.93 pJ. Moreover, it has steep turn-on and turn-off switching slopes of 1.7 mV/decade and 0.7 mV/decade. The reliability of the selector feature is confirmed by pulse operations and a stress test. [ABSTRACT FROM AUTHOR]

Write-once-read-many (WORM) memory effect is reported in the 19.68 Tex, 80:20 ratio polyethylene terephthalate (PET)-metal fiber spun electroconductive yarn. The yarn sample displayed a typical WORM memory behavior having electrical bistability with an OFF/ ON resistance ratio up to $10^{{9}}$ and a long retention period. As the polyester fibers transform from amorphous (resistive state) to semicrystalline (conductive state) upon the application of bias voltage, the charge conduction changes from electronic to ionic, above the glass transition temperature. Furthermore, ${I}-{V}$ curves were fit to explain the charge carrier transport mechanisms in the WORM behavior. Additionally, upon intentional mechanical perturbation, the sample could reset to its native high-resistive state (the phenomenon is termed as Reset WORM or ReWORM), ready for another WORM storage cycle. [ABSTRACT FROM AUTHOR]

The authors apply the concept of continual learning to modeling conductive‐filament growth in resistive‐switching materials (RSM). The approach permits computation of compliance current without knowing the geometries of conductive filaments and switching behaviors. This avoids the need to retrain the entire dataset when additional compliance currents are considered and is thus ideal for resistive switching (RS) thin films, doped layers, and other material systems. Computation of compliance current is consistent with experimental data for a wide range of parameters and learning tasks and demonstrates switching behavior not captured by traditional models. Lesion calculations elucidate the brain‐inspired‐modification‐facilitated increase in compliance‐current‐computation‐accuracy. A state‐of‐the‐art performance on challenging compliance‐current learning tasks without storing data is achieved ("brain inspired replay (BIR) – gating based on internal context (Gat)" method, ≈89%; above a benchmark of ≈50% for synaptic‐intelligence (SI)/elastic‐weight‐consolidation (EWC) methods), and it provides a novel model for computing compliance current based on replay of the brain. This intuitive approach combined with a simple solver tool, allows researchers with little computation experience to perform realistic and accurate modeling. [ABSTRACT FROM AUTHOR]

Resistive-switching-based memory devices meet most of the requirements for use in next-generation information and communication technology applications, including standalone memory devices, neuromorphic hardware, and embedded sensing devices with on-chip storage, due to their low cost, excellent memory retention, compatibility with 3D integration, in-memory computing capabilities, and ease of fabrication. Electrochemical synthesis is the most widespread technique for the fabrication of state-of-the-art memory devices. The present review article summarizes the electrochemical approaches that have been proposed for the fabrication of switching, memristor, and memristive devices for memory storage, neuromorphic computing, and sensing applications, highlighting their various advantages and performance metrics. We also present the challenges and future research directions for this field in the concluding section.

As information technology is moving toward the era of big data, the traditional Von-Neumann architecture shows limitations in performance. The field of computing has already struggled with the latency and bandwidth required to access memory ("the memory wall") and energy dissipation ("the power wall"). These challenging issues, such as "the memory bottleneck," call for significant research investments to develop a new architecture for the next generation of computing systems. Brain-inspired computing is a new computing architecture providing a method of high energy efficiency and high real-time performance for artificial intelligence computing. Brain-inspired neural network system is based on neuron and synapse. The memristive device has been proposed as an artificial synapse for creating neuromorphic computer applications. In this study, post-silicon nano-electronic device and its application in brain-inspired chips are surveyed. First, we introduce the development of neural networks and review the current typical brain-inspired chips, including brain-inspired chips dominated by analog circuit and brain-inspired chips of the full-digital circuit, leading to the design of brain-inspired chips based on post-silicon nano-electronic device. Then, through the analysis of N kinds of post-silicon nano-electronic devices, the research progress of constructing brain-inspired chips using post-silicon nano-electronic device is expounded. Lastly, the future of building brain-inspired chips based on post-silicon nano-electronic device has been prospected. [ABSTRACT FROM AUTHOR]

Copyright of Frontiers of Information Technology & Electronic Engineering is the property of Springer Nature and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Matrix computation is ubiquitous in modern scientific and engineering fields. Due to the high computational complexity in conventional digital computers, matrix computation represents a heavy workload in many data-intensive applications, e.g., machine learning, scientific computing, and wireless communications. For fast, efficient matrix computations, analog computing with resistive memory arrays has been proven to be a promising solution. In this Tutorial, we present analog matrix computing (AMC) circuits based on crosspoint resistive memory arrays. AMC circuits are able to carry out basic matrix computations, including matrix multiplication, matrix inversion, pseudoinverse and eigenvector computation, all with one single operation. We describe the main design principles of the AMC circuits, such as local/global or negative/positive feedback configurations, with/without external inputs. Mapping strategies for matrices containing negative values will be presented. The underlying requirements for circuit stability will be described via the transfer function analysis, which also defines time complexity of the circuits towards steady-state results. Lastly, typical applications, challenges, and future trends of AMC circuits will be discussed. [ABSTRACT FROM AUTHOR]

An aluminum oxynitride (AlOx:N) resistive memory with a large ON/OFF ratio of 106 at a low read voltage of 0.5 V is proposed. The AlOx:N resistive switching (RS) layer is fabricated using a two-stage thermal oxynitridation process of an evaporated Al film. The Al/AlOx: N/n+-Si device shows write-once–read-many-times (WORM) characteristics and the writing operation is voltage-polarity-independent. The resistance states can be repeatably read $10^{4}\times $ and the data retention time is over 104 s. A high read-disturb immunity is also observed for over 104 s. Data retention and read-disturb characteristics measured at 85 °C predict a ten-year lifetime of the device. The carrier transport and the RS mechanisms are studied and illustrated. [ABSTRACT FROM AUTHOR]

Memristors are one of the fastest developing electronic devices in the field of data storage and brain inspired neural computing. As a two terminal device, memristors are numerously utilized as resistive random access memories (RRAM) and energy efficient artificial synapses. Herein, the fabrication of perovskite‐type rubidium lead chloride quantum dots (RPCQDs) is reported as a functional layer in a memristive system. The device, Al/RPCQDs/indium doped tin oxide (ITO), exhibits a cycling‐induced decrease in SET voltage, where Al and ITO work as a top and bottom electrode respectively. However, time dependent self‐recovery to the pristine state is observed in the Al/RPCQDs/ITO device. In contrast, the self‐rejuvenation is suppressed when a buffer capped conducting polymer (BCCP) is incorporated on the ITO layer to make a Al/RPCQDs/BCCP/ITO structure. This customized device structure successfully retains the reproducible bipolar switching behavior without severe deviation in operating voltages, which helps in studying reliable memristive properties. In addition, the Al/RPCQDs/BCCP/ITO memristive device also demonstrates some essential synaptic functions such as pair‐pulse facilitation, long‐term potentiation, and long‐term depression. [ABSTRACT FROM AUTHOR]

Current large-scale implementations of deep learning and data mining require thousands of processors, massive amounts of off-chip memory, and consume gigajoules of energy. New memory technologies, such as nanoscale two-terminal resistive switching memory devices, offer a compact, scalable, and low-power alternative that permits on-chip colocated processing and memory in fine-grain distributed parallel architecture. Here, we report the first use of resistive memory devices for implementing and training a restricted Boltzmann machine (RBM), a generative probabilistic graphical model as a key component for unsupervised learning in deep networks. We experimentally demonstrate a 45-synapse RBM realized with 90 resistive phase change memory (PCM) elements trained with a bioinspired variant of the contrastive divergence algorithm, implementing Hebbian and anti-Hebbian weight updates. The resistive PCM devices show a twofold to tenfold reduction in error rate in a missing pixel pattern completion task trained over 30 epochs, compared with untrained case. Measured programming energy consumption is 6.1 nJ per epoch with the PCM devices, a factor of 150 times lower than the conventional processor-memory systems. We analyze and discuss the dependence of learning performance on cycle-to-cycle variations and number of gradual levels in the PCM analog memory devices.

Memristor devices fabricated using the chalcogenide Ge2Te3 phase change thin films in a metal-insulator-metal structure are characterized using thermal and electrical stimuli in this study. Once the thermal and electrical stimuli are applied, cross-sectional transmission electron microscopy (TEM) and X-ray energy-dispersive spectroscopy (XEDS) analyses are performed to determine structural and compositional changes in the devices. Electrical measurements on these devices showed a need for increasing compliance current between cycles to initiate switching from low resistance state (LRS) to high resistance state (HRS). The measured resistance in HRS also exhibited a steady decrease with increase in the compliance current. High resolution TEM studies on devices in HRS showed the presence of residual crystalline phase at the top-electrode/dielectric interface, which may explain the observed dependence on compliance current. XEDS study revealed diffusion related processes at dielectric-electrode interface characterized, by the separation of Ge2Te3 into Ge-and Te- enriched interfacial layers. This was also accompanied by spikes in O level at these regions. Furthermore, in-situ heating experiments on as-grown thin films revealed a deleterious effect of Ti adhesive layer, wherein the in-diffusion of Ti leads to further degradation of the dielectric layer. This experimental physics-based study shows that the large HRS/LRS ratio below the current compliance limit of 1mA and the ability to control the HRS and LRS by varying the compliance current are attractive for memristor and neuromorphic computing applications. [ABSTRACT FROM AUTHOR]

Abstract With the rapid development of data‐driven human interaction, advanced data‐storage technologies with lower power consumption, larger storage capacity, faster switching speed, and higher integration density have become the goals of future memory electronics. Nevertheless, the physical limitations of conventional Si‐based binary storage systems lag far behind the ultrahigh‐density requirements of post‐Moore information storage. In this regard, the pursuit of alternatives and/or supplements to the existing storage technology has come to the forefront. Recently, organic‐based resistive memory materials have emerged as promising candidates for next‐generation information storage applications, which provide new possibilities of realizing high‐performance organic electronics. Herein, the memory device structure, switching types, mechanisms, and recent advances in organic resistive memory materials are reviewed. In particular, their potential of fulfilling multilevel storage is summarized. Besides, the present challenges and future prospects confronted by organic resistive memory materials and devices are discussed.

Memristor devices fabricated using the chalcogenide Ge2Te3 phase change thin films in a metal-insulator-metal structure are characterized using thermal and electrical stimuli in this study. Once the thermal and electrical stimuli are applied, cross-sectional transmission electron microscopy (TEM) and X-ray energy-dispersive spectroscopy (XEDS) analyses are performed to determine structural and compositional changes in the devices. Electrical measurements on these devices showed a need for increasing compliance current between cycles to initiate switching from low resistance state (LRS) to high resistance state (HRS). The measured resistance in HRS also exhibited a steady decrease with increase in the compliance current. High resolution TEM studies on devices in HRS showed the presence of residual crystalline phase at the top-electrode/dielectric interface, which may explain the observed dependence on compliance current. XEDS study revealed diffusion related processes at dielectric-electrode interface characterized, by the separation of Ge2Te3 into Ge- and Te- enriched interfacial layers. This was also accompanied by spikes in O level at these regions. Furthermore, in-situ heating experiments on as-grown thin films revealed a deleterious effect of Ti adhesive layer, wherein the in-diffusion of Ti leads to further degradation of the dielectric layer. This experimental physics-based study shows that the large HRS/LRS ratio below the current compliance limit of 1 mA and the ability to control the HRS and LRS by varying the compliance current are attractive for memristor and neuromorphic computing applications.

Recent progress in novel non-volatile memory-based synaptic device technologies and their feasibility for matrix-vector multiplication (MVM) has ignited active research on implementing analog neural network training accelerators with resistive crosspoint arrays. While significant performance boost as well as area- and power-efficiency is theoretically predicted, the realization of such analog accelerators is largely limited by non-ideal switching characteristics of crosspoint elements. One of the most performance-limiting non-idealities is the conductance update asymmetry which is known to distort the actual weight change values away from the calculation by error back-propagation and, therefore, significantly deteriorates the neural network training performance. To address this issue by an algorithmic remedy, Tiki-Taka algorithm was proposed and shown to be effective for neural network training with asymmetric devices. However, a systematic analysis to reveal the required asymmetry specification to guarantee the neural network performance has been unexplored. Here, we quantitatively analyze the impact of update asymmetry on the neural network training performance when trained with Tiki-Taka algorithm by exploring the space of asymmetry and hyper-parameters and measuring the classification accuracy. We discover that the update asymmetry level of the auxiliary array affects the way the optimizer takes the importance of previous gradients, whereas that of main array affects the frequency of accepting those gradients. We propose a novel calibration method to find the optimal operating point in terms of device and network parameters. By searching over the hyper-parameter space of Tiki-Taka algorithm using interpolation and Gaussian filtering, we find the optimal hyper-parameters efficiently and reveal the optimal range of asymmetry, namely the asymmetry specification. Finally, we show that the analysis and calibration method be applicable to spiking neural networks. [ABSTRACT FROM AUTHOR]

Abstract Memristors are a new type of circuit element with a resistance that is tunable to discrete levels by a voltage/current and sustainable after removal of power, allowing for low‐power computation and multilevel information storage. Many organic‐inorganic lead perovskites are reported to demonstrate memristive behavior, but few have been considered for use as a multilevel memory; also, their potential application has been hindered by the toxicity of lead ions. In this article, lead‐free perovskite MASnBr3 was utilized in memristors for quaternary information storage. Indium tin oxide (ITO)/MASnBr3/Au memristors were fabricated and showed reliable memristive switching with well‐separated ON/OFF states of a maxima resistance ratio of 102 to 103. More importantly, four resistive states can be distinguished and repeatedly written/read/erased with a retention time of 104 seconds and an endurance of 104 pulses. By investigating the current‐electrode area relationship, Br distribution in the ON/OFF states by in situ Raman and scanning electron microscopy, and temperature‐dependent current decay, the memristive behavior was explicitly attributed to the forming/breaking of conductive filaments caused by the migration of Br− under an electric field. In addition, poly(ethylene terephthalate)‐ITO/MASnBr3/Au devices were found to retain their multiresistance state behavior after being bent for 1000 times, thus demonstrating good device flexibility. Our results will inspire more lead‐free perovskite work for multilevel information storage, as well as other memristor‐based electronics.

There is a growing gap between data explosion speed and the improvement of graph processing systems on conventional architectures. The main reason lies in the large overhead of random access and data movement, as well as the unbalanced and unordered communication cost. The emerging metal-oxide resistive random access memory (ReRAM) has great potential to solve these in the context of processing-inmemory (PIM) technology. However, the unbalanced and irregular communication under different graph organizations is not well addressed. In this paper, we present a PIM graph traversal accelerator using ReRAM with a lower communication cost named ReGra. ReGra optimizes the graph organization and communication efficiency in graph traversal. Benefiting from high density and efficient access of ReRAM, graphs are organized compactly and partitioned into processing cubes by the proposed Interval-Block Hash Balance (IBHB) method to balance graph distribution. Moreover, remote cube updates in graph traversal are converged into batched messages and transferred in a concentrated period via the custom circular round communication phase. This eliminates irregular and unpredictable inter-cube communication and overlaps partial computation and communication. Comparative experiments with previous work like Tesseract and RPBFS show that ReGra achieves better performance and yields a speedup of up to 2.2×. Besides the communication cost is reduced by up to 76%. It also achieves an average reduction in energy consumption of 70%.

Recent progress in novel non-volatile memory-based synaptic device technologies and their feasibility for matrix-vector multiplication (MVM) has ignited active research on implementing analog neural network training accelerators with resistive crosspoint arrays. While significant performance boost as well as area- and power-efficiency is theoretically predicted, the realization of such analog accelerators is largely limited by non-ideal switching characteristics of crosspoint elements. One of the most performance-limiting non-idealities is the conductance update asymmetry which is known to distort the actual weight change values away from the calculation by error back-propagation and, therefore, significantly deteriorates the neural network training performance. To address this issue by an algorithmic remedy, Tiki-Taka algorithm was proposed and shown to be effective for neural network training with asymmetric devices. However, a systematic analysis to reveal the required asymmetry specification to guarantee the neural network performance has been unexplored. Here, we quantitatively analyze the impact of update asymmetry on the neural network training performance when trained with Tiki-Taka algorithm by exploring the space of asymmetry and hyper-parameters and measuring the classification accuracy. We discover that the update asymmetry level of the auxiliary array affects the way the optimizer takes the importance of previous gradients, whereas that of main array affects the frequency of accepting those gradients. We propose a novel calibration method to find the optimal operating point in terms of device and network parameters. By searching over the hyper-parameter space of Tiki-Taka algorithm using interpolation and Gaussian filtering, we find the optimal hyper-parameters efficiently and reveal the optimal range of asymmetry, namely the asymmetry specification. Finally, we show that the analysis and calibration method be applicable to spiking neural networks.