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Battery-less active implantable devices are of interest because they offer longer life span and eliminate costly battery replacement surgical interventions. This is possible as a result of advances in inductive power transfer and development of power management circuits to maximize the overall power transfer and provide various voltage levels for multi-functional implantable devices. Rehabilitation therapy using optical stimulation of genetically modified peripheral neurons requires high current loads. Standard rectification topologies are inefficient and have associated voltage drops unsuited for miniaturized implants. This paper presents an integrated power management unit (PMU) for an optical-electrical stimulator to be used in the treatment of motor neurone disease. It includes a power-efficient regulating rectifier with a novel body biased high-speed comparator providing 3.3 V for the operation of the stimulator, a 3-stage latch-up charge pump with 12 V output for the input stage of the optical-electrical stimulator, and 1.8 V for digital control logic. The chip was fabricated in a $0.18 ~\mu \text{m}$ CMOS process. Measured results show that for a regulated output of 3.3 V delivering 30.3 mW power, the peak power conversion efficiency is 84.2% at 6.78 MHz inductive link tunable frequency reducing to 70.3% at 13.56 MHz. The charge pump with on chip capacitors has 90.9% measured voltage conversion efficiency.

This paper presents a 125 KHz, single-stage, dual-output wireless power receiver with pulse skip modulation (PSM). Multi-output receivers are proposed to supply different modules in one system. Conventional multi-output receivers contain a rectifier and a multi-output regulator, which degrade the power conversion efficiency (PCE) due to interstage loss of the rectifier and the regulator. Additionally, existing single-inductor multi-output (SIMO) receivers exhibit a cross-regulation phenomenon because of the sharing inductor, which decreases the stability of the output voltages, and the use of an inductor in SIMO receivers increases the cost of the circuit. The proposed receiver in this article realizes rectification and regulation in only one stage, which eliminates interstage loss; this improves the power conversion efficiency of the system and realizes dual-output voltages with only four power transistors without an inductor, which reduces the chip area and minimizes cost. There is no cross-regulation in this dual-output architecture because the dual-output voltages are charged by different phases of the input signal. PSM modulation was adopted to regulate output voltages for higher efficiency. The proposed single-stage, dual-output regulating rectifier delivers a maximum power of 47 mW, and the dual-output voltages are 1.8 V and 2 V. This receiver is designed by a 0.18 μm complementary metal-oxide-semiconductor (CMOS) process and realizes a peak efficiency of 86% when the output power ranges from 15 mW to 47 mW. [ABSTRACT FROM AUTHOR]

This article presents a 6.78-MHz wireless power transfer system with a structure-reconfigurable power amplifier (SR-PA) and a 0X/1X regulating rectifier. The proposed 0X/1X regulating rectifier with local-loop control achieves voltage rectification and regulation without dc–dc converter usage to improve the receiver efficiency. To further enhance the system efficiency, the proposed SR-PA with global-loop power control adjusts its power-stage structure to realize adaptive power delivery. The transmitter and receiver chips were fabricated in a 0.25- $\mu \text{m}$ CMOS process using 5-V devices, and the resulting system was able to regulate an output voltage of 5 V. The measurement results demonstrated an 11.2% improvement in system efficiency for a light load and a 2.7 times increase in available output power compared with the same system without transmission power control. A measured peak receiver efficiency of 92.9% and a total system efficiency of 71.5% were also demonstrated. [ABSTRACT FROM AUTHOR]

This paper presents a reconfigurable, dual-output, regulating rectifier featuring pulse width modulation (PWM) and dual-mode pulse frequency modulation (PFM) control schemes for single-stage ac-to-dc conversion to provide two independently regulated supply voltages (each in 1.5–3 V) from an input ac voltage. The dual-mode PFM controllers feature event-driven regulation as well as frequency division. The former incorporates stable, fast, digital feedback loops to adaptively adjust the driving frequency of four power transistors, MP1∼4, based on the desired output power level to perform voltage regulation and deliver fast, transient, load currents. The latter sets the driving frequency of MP1∼4 to a user-defined fraction (1/1 ∼ 1/32) of the input frequency (1–10 MHz). The PWM controllers incorporate stable, analog, feedback loops to accurately adjust the conduction duration of MP1∼4 for voltage regulation and can be combined with PFM frequency division for an extended operation dynamic range. Fabricated in 0.18 μm 1P/6M CMOS, the regulating rectifier features power conversion efficiency (PCE) of >83.8% at 2 and 5 MHz, with the first output channel delivering ∼1 mW from VDD of 1.5 V and the second output channel delivering variable power from VDDH of 2.5 V to a load in the range of 0.1 to 1 kΩ. Peak PCE values of 90.75% (2 MHz, 100 Ω) and 90.7% (5 MHz, 200 Ω) are also measured. The regulating rectifier is suitable for the emerging modality of capacitive wireless power transfer to biomedical implants. [ABSTRACT FROM AUTHOR]

A miniaturized, fully integrated wireless power receiver system-on-chip with embedded 16-channel electrode array and data transceiver for electrocortical neural recording and stimulation is presented. An H-tree power and signal distribution network throughout the SoC maintains high quality factor up to 11 in the on-chip receiver coil at 144 MHz resonant frequency while rejecting RF interference in sensitive neural interface circuits owing to its perpendicular and equidistant geometry. A multi-mode buck-boost resonant regulating rectifier (B $^2$ R $^3$) offers greater than 11-dB input dynamic range in RF reception and less than 1 mV overshoot in transient load regulation. At 10 mm link distance, the 9 mm $^2$ neural interface SoC fabricated in a 180 nm silicon-on-insulator (SOI) process attains an overall wireless power transmission system efficiency (WSE) of 3.4% in driving a 160  $\mu$ W load yielding a WSE figure-of-merit of 131, while maintaining signal integrity in analog recording and wireless data transmission that comprise the on-chip load. [ABSTRACT FROM AUTHOR]

This paper presents a fully integrated resonant regulating rectifier (IR3) with an on-chip coil used to wirelessly power mm-sized implants. By combining rectification and regulation in a single stage, and controlling this stage via a hybrid pulse-width modulation and pulse-frequency modulation (PFM) feedback scheme, the IR3 avoids efficiency-limiting cascaded losses while enabling tight voltage regulation with low dropout and ripple. The IR3 is implemented in 0.078 mm2 of active area in 180-nm Silicon oxide insulator (SOI) CMOS, and achieves a 1.87% $\Delta V_{{{\textrm{DD}}}}/V_{{{\textrm{DD}}}}$ power supply regulation ratio with a 1-nF decoupling capacitor despite a tenfold load current variation from 8 to 80 $\mu {{\text{A}}}$ . A 0.8-V $V_{{{\textrm{DD}}}}$ is maintained at a 8- ${{\text{k}}}\Omega $ load for 144-MHz RF inputs ranging from 0.98 to 1.5 V. At 1-V regulation, the voltage conversion efficiency is greater than 92% with less than 5.2- ${{\text{m}}}V_{{{\textrm{pp}}}}$ ripple, while the power conversion efficiency is 54%. The measured overall wireless power transfer system efficiency, from the primary coil to $V_{{{\textrm{DD}}}}$ output of the IR3, is 2% at 160- $\mu {{\text{W}}}$ load, and reaches 5% at 700 $\mu {{\text{W}}}$ . [ABSTRACT FROM AUTHOR]