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Abstract A CMOS baseband‐active‐feedback receiver frontend with passive voltage‐commutating mixers is proposed. The active feedback baseband enables in‐band signal amplification and out‐of‐band blocker interference suppression by constructing the RF bandpass filter and BB lowpass filter, simultaneously. The voltage‐commutating mixers embedded in current mirrors significantly reduce the power requirement for the LO generator. The stacked n/pMOS structure is commonly adopted to further improve power efficiency. The receiver frontend is designed in a standard 65 nm CMOS process. Simulation results display an NF of 3.4 dB and a maximum gain of 32 dB from 1 to 5 GHz LO frequency range. The obtained in‐band and out‐of‐band IIP3 are −12 dBm and 9 dBm, respectively. The receiver frontend core only consumes 22 mW at 1 GHz LO frequency and occupies the area of 645 × 543 μm2, which is suitable for the low‐power application of handheld terminals.

A CMOS baseband‐active‐feedback receiver frontend with passive voltage‐commutating mixers is proposed. The active feedback baseband enables in‐band signal amplification and out‐of‐band blocker interference suppression by constructing the RF bandpass filter and BB lowpass filter, simultaneously. The voltage‐commutating mixers embedded in current mirrors significantly reduce the power requirement for the LO generator. The stacked n/pMOS structure is commonly adopted to further improve power efficiency. The receiver frontend is designed in a standard 65 nm CMOS process. Simulation results display an NF of 3.4 dB and a maximum gain of 32 dB from 1 to 5 GHz LO frequency range. The obtained in‐band and out‐of‐band IIP3 are −12 dBm and 9 dBm, respectively. The receiver frontend core only consumes 22 mW at 1 GHz LO frequency and occupies the area of 645 × 543 μm2, which is suitable for the low‐power application of handheld terminals. [ABSTRACT FROM AUTHOR]

Deep submicron CMOS technology proves to be suitable for transceiver design at mmwave band frequencies. At the same time, it has been a challenging task to obtain high performance at mmwave frequencies. In this paper, a 28 GHz low-IF receiver frontend with improved performance by incorporating a proposed linear Gm-C low-pass filter (LPF) is presented using 40 nm CMOS technology targeting for 5G wireless system. A mathematical expression for the linearity of the proposed filter is derived and compared with the basic filter model. The improved linearity (IIP3 of − 7. 1 8 dBm) of the proposed filter results in the enhancement of linearity and hence the Figure of Merit (FOM) of the receiver with the proposed filter. The receiver attains a conversion gain of 34.6 dB, a noise figure of 3.1 dB and IIP3 of − 2 1. 7 dBm. The total current drawn by the receiver is 27.3 mA at a 1.2 V power supply. The overall FOM of the receiver with the proposed filter is improved to 0.30 whereas the FOM of the receiver with the basic filter model is 0.13. The area of the receiver is 7 7 0 ∗ 3 8 0 μ m 2 whereas the proposed filter occupies 2 7. 7 ∗ 2 1. 9 μ m 2 . [ABSTRACT FROM AUTHOR]

The paper describes the Advanced Multi-Engine Platform (AMP™) – Topcon's patent pending technique, which is capable to improve RTK performance, based on the idea of running several RTK engines in parallel. The performance of AMP™ is dependent on Topcon receiver board, where it has been implemented, and the best results are achieved with B210 board. The main specifics of B210 is that it has two RF front-ends and a single digital section. Such an architecture allows for calculating heading and tilt within a single receiver board, and providing better RTK performance due to synergy of attitude determination and RTK solutions from two antennas, calculated within a single digital section. The paper describes specifics of B210 board along with mathematical aspects of AMP™ and its logic. The test results demonstrate noticeable improvements in RTK performance for B210 receiver board with AMP™, compared with the classical single-engine RTK approach. [ABSTRACT FROM AUTHOR]

This paper presents experimental CMOS RF frontends suitable for ultra-low-power and ultra-low-voltage operations. In order to achieve the desirable gain and linearity of the receiver chain at a reduced supply voltage, the current-reused bias technique and the multiple-gated transistors are employed. As for the transmitter frontend, a low-voltage double-balanced mixer is utilized to maximize the conversion gain. In addition, a differential-to-single-ended circuit is also included to increase the saturated output power. Using a standard 0.18-\mum CMOS process, the proposed circuits are realized for 5-GHz RF applications with a supply voltage of 0.6 V. The fabricated receiver frontend demonstrates a conversion gain of 14.5 dB and an IIP3 of - 16 dBm with a power consumption of 2.1 mW, while the conversion gain and the output 1-dB compression of the transmitter frontend are 12.9 dB and -4.1 dBm, respectively, provided a dc power of 6 mW. [ABSTRACT FROM PUBLISHER]

In this letter, a fully integrated receiver frontend which is composed of a low-noise amplifier and a down-conversion mixer is presented for multiband applications. Different from conventional concurrent or switched-type architectures, the proposed circuit uses varactors for the frequency tuning. In addition, broadband techniques are also employed to maximize the operating frequency range and to enhance the circuit performance. Using a standard 0.18 mum CMOS technology, a 3-5 GHz receiver frontend is implemented for demonstration. With a LO power of 3 dBm and an IF frequency of 10 MHz, the circuit exhibits a conversion gain of 22.2 plusmn2.4 dB while the IIP3 and noise figure are better than -6 dBm and 17 dB, respectively, within the entire frequency range. Operated at a supply voltage of 2 V, the receiver consumes a dc power of 16 mW. [ABSTRACT FROM PUBLISHER]