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Wireless secret key generation has emerged as a promising technique for Internet of Things (IoT) systems to establish shared encryption keys between the server and legitimate mobile user. This paper focuses on the use of multi-domain joint information to achieve a high key generation rate (KGR) and the implementation of a reliable, low-complexity secret key generation mechanism for distributed antenna systems (DAS) with orthogonal-frequency division multiplexing (OFDM). We present a space-time-frequency channel state information (CSI)-based key generation scheme based on a two-step approach of adaptive link selection and stepwise decorrelation algorithms. The performance is evaluated in terms of KGR, key disagreement rate (KDR), randomness, and computational complexity by using both a standardized channel model and real-world measurements. Numerical results show that our proposed low-complexity algorithms effectively utilize the space-time-frequency CSI to multiply the KGR in both indoor and outdoor environments. Through adaptive link selection in DAS, the KDR is maintained within a correctable range, thereby ensuring the validity of generated keys in dynamic environments. Further applying stepwise decorrelation reduces the computational complexity by more than half while satisfying all eight key generation randomness tests in the NIST test suite.

The implementation of true random number generators is of vital importance to preserve the reliability of cryptographic systems. The lack of entropy can compromise their integrity, affecting the security of the entire chain of applications. Ensuring the effectiveness of a random number generator can be understood as reducing the risk of information loss due to possible attacks by third parties. This paper presents a novel approach for a true random number generator based on a Ring Oscillator-Physical Unclonable Function. Since the principle of operation of physical unclonable functions is based on the physical properties of each device, they can be used for security applications such as device identification, counterfeit prevention, and increase the robustness of cryptographic functions. In addition, increasing the versatility of the design to use them as a source of entropy, they can also fulfill tasks such as generation of initialization vectors or nonces and keys for symmetric cryptography. The system incorporates multiple operating configurations, which allows a complete analysis of its performance to adapt it to different application scenarios. The randomness and correct operation of the proposed design have been evaluated online, by incorporating it into a hybrid HW/SW embedded system able to run the official test suite published by the National Institute of Standards and Technology without any need for post-processing. The architecture has been designed for Xilinx Zynq-700 family devices and implemented on the Pynq-Z2 development board., SPIRS Project with Grant Agreement No. 952622 under the EU H2020 research and innovation program, ARES Project PID2020-116664RB-100 funded by MCIN/AEI/10.13039/501100011033 and the EU NextGenerationEU/PRTR., M.C.M.R. holds a Postdoc fellowship from the Andalusia Government with support from PO FSE of EU.

This study presents a pure digital scalable mixed entropy separation structure for the physical unclonable function (PUF) and true random number generator (TRNG), which is implemented on Xilinx field-programmable gate arrays (FPGAs). The mixed entropy separation structure in this study is to solve the problems of unstable output in the existing PUF structure and the poor scalability of the TRNG and PUF design. The proposed design has the following innovations: 1) concept of sensitive entropy and the corresponding processing method are proposed for the first time; 2) design does not need to modify the internal design of the entropy source, and it is suitable for most entropy source arrays; and 3) adjustable PUF bit width and TRNG throughput enhance the scalability of the architecture under different requirements. The structure is simulated and validated on two Xilinx FPGAs and tested under nominal working conditions. The results show that the 512-bit PUF entropy source after treatment is 92.7% more stable than the 1024-bit entropy source before treatment, the random number after treatment passes all types of randomness tests, and the minimum entropy is more than 0.8. Under various conditions within the ranges of 0 °C–80 °C and 0.8–1.2 V, the TRNG output remains stable after treatment; the maximum intra-Hamming distance of the treated PUF is 5.1028%, and the average intra-Hamming distance is 2.7065%.

To properly respond to ever-growing threats to information security, there is a pressing need for more effective encryption techniques. This paper offers an innovative block-based encryption technique that combines effective random manipulations of a block’s symbols with tricky substitution techniques. Furthermore, the proposed technique offers a block diffusion method in which minor variations to the block’s symbols will magnify and then propagate to the entire block, largely affecting every individual symbol in the block. Experiments with the prototype implementation showed that the output of the proposed encryption technique passed effective randomness tests (NIST and ENT batteries) with a success rate greater than 94%. The simulations of the block diffusion technique showed that it has a high avalanche effect, which greatly boosts the security of the resulting ciphertext.

The rapid rise of Internet of Technology (IoT) applications in the twenty-first century is characterized by the frequent transmission of sensitive multimedia data. Such transmissions are vulnerable to security threats, putting the data at risk. Handling security aspects becomes especially important when dealing with sensitive data exchanges. It should be emphasized, however, that sensor devices are resource constrained, limiting the use of standard ciphers at the device level. Because CA are easy to implement in hardware, give a huge key space, and can generate extremely random sequences computationally faster, they can be utilized to create lightweight ciphers for data confidentiality. In this paper, a color image cipher based on 3-D von Neumann CA is proposed for IoT applications. It has succeeded in achieving significantly faster execution speeds, lower energy consumption, and a bigger key space than previous methods. The cipher images also exhibit a consistently distributed histogram and correlation coefficient map, high information entropy values, and passed the NIST and DIEHARD randomness tests. Furthermore, the LICCA’s efficacy against cyber-attacks has been demonstrated by numerous standard cryptanalysis attacks and other critical studies. Its suitability for IoT applications has been verified by experimental results.

A stream cipher generates long keystream to be XORed with plaintext to produce ciphertext. A stream cipher is said to be secure if the keystream that it produces is consistently random. One of the ways by which we can analyze stream ciphers is by testing randomness of the keystream. The statistical tests mainly try to find if any output keystream leaks any information about the secret key or the cipher’s internal state and also check the randomness of the keystream. We have applied these tests to different keystreams generated by ZUC, Espresso and Grain v1 stream ciphers to check for any weaknesses. We have also proposed four new statistical tests to analyze the internal state when the hamming weight of key and IV used is very high or low. Out of these four tests, Grain v1 fails the last test i.e. internal state correlation using high hamming weight IV.

This paper proposed a chaotic system of N-level logistic cascaded homogenization mapping (N-LLCHM). The cascade structure of multiple one-dimensional logistic mappings results in an exponential increase in the number of fixed points in the mapping, which greatly increases the initial error divergence of the system during the iteration process, and ultimately increases the complexity of the system to generate time series. In the experiment, the homogenization adjustment function of the mapping is derived according to the maximum entropy theorem. The homogenization adjustment function and the N-level logistic cascade structure are cascaded again to construct a complete dynamics system. The analyses of indicators such as information entropy, Lyapunov exponent, spectral entropy and NIST SP800-22 randomness test reveal that the mapping generates a chaotic time series with good aperiodic and uniform distribution characteristics under the condition that N is greater than or equal to 4. Then, N-LLCHM is used as the core of pseudo-random number generator, and the color image encryption algorithm is constructed by using three steps of pixel bidirectional cross-coding, position scrambling and pixel diffusion as the main system. According to the evaluation of histogram, correlation, information entropy and anti-differential attack test, it is verified that this algorithm has better encryption effect and higher security than the present image encryption algorithms.

The concept of black-and-white visual cryptography with two truly random shares, previously applied to color images, was improved by mixing the contents of the segments of each coding image and by randomly changing a specified number of black pixels into color ones. This was done in such a way that the changes of the contents of the decoded image were as small as possible. These modifications made the numbers of color pixels in the shares close to balanced, which potentially made it possible for the shares to be truly random. The true randomness was understood as that the data pass the suitably designed randomness tests. The randomness of the shares was tested with the NIST randomness tests. Part of the tests passed successfully, while some failed. The target of coding a color image in truly random shares was approached, but not yet reached. In visual cryptography, the decoding with the unarmed human eye is of primary importance, but besides this, simple numerical processing of the decoded image makes it possible to greatly improve the quality of the reconstructed image, so that it becomes close to that of the dithered original image.

The design of cryptographically secure pseudorandom number generator (CSPRNG) producing unpredictable pseudorandom sequences robustly and credibly has been a nontrivial task. Almost all the chaos-based CSPRNG design approaches invariably depend only on statistical analysis. Such schemes designed to be secure are being proven to be predictable and insecure day by day. This paper proposes a design and instantiation approach to chaos-based CSPRNG using proven generic constructions of modern cryptography. The proposed design approach with proper instantiation of such generic constructions eventually results in providing best of both worlds that is the provable security guarantees of modern cryptography and passing of necessary statistical tests as that of chaos-based schemes. Also, we introduce a new coupled map lattice based on logistic-sine map for the construction of CSPRNG. The proposed pseudorandom number generator is proven using rigorous security analysis as that of modern cryptography and tested using the standard statistical testing suites. It is observed that the generated sequences pass all stringent statistical tests such as NIST, Dieharder, ENT, and TestU01 randomness test suites.

In cryptosystems, the generation of random keys is crucial. The random number generator is required to have a sufficiently fast generation speed to ensure the size of the keyspace. At the same time, the randomness of the key is an important indicator to ensure the security of the encryption system. The chaotic random number generator has been widely used in cryptosystems due to the uncertainty, non-repeatability, and unpredictability of chaotic systems. However, chaotic systems, especially high-dimensional chaotic systems, have slow calculation speed and long iteration time. This caused a conflict between the number of random keys and the speed of generation. In this paper, we introduce the Least Squares Generative Adversarial Networks(LSGAN)into random number generation. Using LSGAN’s powerful learning ability, a novel learning random number generator is constructed. Six chaotic systems with different structures and different dimensions are used as training sets to realize the rapid and efficient generation of random numbers. Experimental results prove that the encryption key generated by this scheme can pass all randomness tests of the National Institute of Standards and Technology (NIST). Hence, our result shows that LSGAN has the potential to improve the quality of the random number generators. Finally, the results are successfully applied to the image encryption scheme based on selective scrambling and overlay diffusion, and good results are achieved.

This work investigates the effectiveness of wavelet packets in dynamic secret key generation (DSKG) for physical layer security (PLS). Preprocessing channel coefficients before quantization is highly essential in DSKG, as noisy measurements on direct quantization produces distinct keys at the transmitter and receiver. Secret keys generated will be having high key disagreement. The performance of different wavelets namely, Daubechies, Symlet and Coiflet, of orders 3 and 5, are studied using Spearman correlation coefficient, bit disagreement rate and NIST randomness tests. NIST tests are evaluated for different bit sequence lengths and as an outcome of the experiment, the best performing wavelet is identified. Further, the proposed work is compared with an existing scheme. It is inferred that, along with maintaining higher correlation coefficient, wavelet packet based DSKG scheme ensures an enhancement in PLS.

We report an ReRAM-based pseudo-true random number generator (RNG) which can significantly improve the security feature of e-ReRAM chips at a very low cost. Combining the true randomness from stochastic behavior of ReRAM and the high output speed from a modified linear feedback shift register (LFSR), the proposed architecture can provide ultrahigh throughput random sequence following system clocks from several Mbit/sec to tens of Gbit/sec. The highly reliable, unpredictable, and unrepeatable ReRAM-based pseudo-true RNG circuit can pass NIST SP800-22 randomness tests at a high score. It is suitable for secure IoT and 5G applications.

Although the intrinsic variability in nanoelectronic devices has been a major obstacle and has prevented mass production, this natural stochasticity can be an asset in hardware security applications. Herein, we demonstrate a true random number generator (TRNG) based on stochastic carrier trapping/detrapping processes in randomly distributed carbon nanotube networks. The bitstreams collected from the TRNG passed all the National Institute of Standards and Technology randomness tests without post-processing. The random bit generated in this study is sufficient for encryption applications, particularly those related to the Internet of Things and edge computing, which require significantly lower power consumption.

In this paper, a Modular Fractional Chaotic Sine Map (MFC-SM) has been introduced to achieve high Lyapunov exponent values and completely chaotic behavior of the bifurcation diagram for high level security. The proposed MFC-SM is compared with the conventional non MFC-SM and it has an excellent chaotic analysis. In addition, the randomness test results indicate that the proposed MFC-SM shows better performance and satisfy all randomness tests. Due to the excellent chaotic properties and good randomization results for the proposed MFC-SM, it is used to be cooperated with the biometric digital identity to achieve dynamic chaotic biometric digital identity. Also, for real time image encryption, both Discrete Wavelet Transform (DWT)partial image encryption and Isomorphic Elliptic Curve (IEC)key exchange are used. In addition, the biometric digital identity is extracted from the user fingerprint image as fingerprint minutia data incorporated with the proposed MFC-SM and hence, a new Dynamic Fractional Chaotic Biometric Digital IdentityIEC (DFC-BID-IEC) has been introduced. Dynamic Fractional Chaotic Key Generator (DFC-KG) is used to control the key schedule for all encryption and decryption processing. The encryption process consists of the confusion and diffusion steps. In the confusion step, the 2D Arnold Cat Map (ACM) is used with secret parameters taken from DFC-KG. Also, the diffusion step is based on the dynamic chaotic self-invertible secret key matrix which can be generated from the proposed MFC-SM. The IEC key exchange secret parameters are generated based on Elliptic Curve Diffie?Hellman(ECDH) key exchange and the isomorphism parametre. Statistical analysis, differential analysis and key sensitivity tests are performed to estimate the security strengths of the proposed DFC-BID-IEC system. The experimental results show that the proposed algorithm is robust against common signal processing attacks and provides a high security level and high speed for image encryption application.

Present era is marked by exponential growth in transfer of multimedia data through internet. Most of the Internet-of-Things(IoT) applications send images to cloud storages through internet. However, in sensitive applications such as healthcare, defense, etc., these images should be encrypted before transmission through insecure public channels to gateway fog nodes. Conventional encryption algorithms cannot be used there due to the resource constraint characters of IoT devices. Here, Cellular Automata (CA) based encryption algorithms can be used because of their inherent simplicity in implementation in hardware, without affecting the capability of generating highly random sequences. In this paper, a lightweight, robust and secure image encryption technique has been proposed using 2-D Von-Neumann Cellular Automata (VCA), called IEVCA, which is lossless, correlation immune and has all the essential properties of a good image cipher. Additionally, the proposed technique passes all the randomness tests of DIEHARD and NIST statistical test suites. Moreover, several security and performance analyses of the IEVCA proved its efficiency and resistance against security attacks. Experimental results of the IEVCA show its better performance when compared to the existing encryption techniques.

The article is dedicated to systematization of scientific positions about the static testing of sequences, widely used in cryptographic systems of information protection for the production of key and additional information (random numbers, vectors of initialization, etc.). Existing approaches to testing pseudorandom sequences, their advantages and disadvantages are considered. It is revealed that for sequences of length up to 100 bits there are not enough existing statistical packets. Perspective direction of research – static testing of sequences using n- dimensional statistics is considered. The joint distributions of 2-chains and 3-chains of a fixed type of random (0, 1) -sequences allow for statistical analysis of local sections of this sequence. Examples, tables, diagrams that can be used to test for randomness of the location of zeros and ones in the bit section are 16 lengths. The paper proposes a methodology for testing pseudorandom sequences, an explicit form of the joint distribution of 2- and 3-chains numbers of various options of random bit sequence of a given small length is obtained. As a result of the implementation of this technique, an information system will be created that will allow analyzing the pseudorandom sequence of a small length and choosing a quality pseudorandom sequence for use in a particular subject area.

This paper presents a novel, real time, high speed and robust chaos-based pseudo random number generator (PRNG) design using the structures of artificial neural network (ANN)-based 2D chaotic oscillator and ring oscillator. In this study, four different robust PRNGs have been implemented using four different approaches (TS-55, Elliott-93, Elliott-2, Cordic-LUT) of TanSig activation functions (TSAF) that have been used in the design of ANN-based 2D chaotic oscillators. The designs have been coded in VHDL using IEEE-754-1985 number standard. The PRNGs have been synthesized for Virtex-6 FPGA chip using Xilinx ISE Design Tools. After Place&Route operation, FPGA chip statistics and maximum operating frequencies have been presented. The maximum operating frequencies of the proposed PRNGs range between 184 and 241 MHz. The 1 Mbit of bit streams generated by PRNGs have been subjected to NIST-800-22 randomness tests. Among 4 different proposed PRNGs, the proposed PRNGs that designed using the Elliott-93 and Cordic-LUT approaches have successfully passed all NIST-800-22 tests and have a bit production rate of 241 Mbps. The proposed secure hybrid chaos-based PRNG structures were compared with similar studies conducted in the literature in recent years. According to the results, the proposed FPGA-based secure new chaotic PRNG structures are useful in cryptographic applications.

Sensitive information used online has resulted in the emergence of many security systems to be protected by secret keys. One of these security systems is the so-called secret sharing, in which certain key portions are distributed to allow sharing access by a specified number of participants. The sharing system requires that several users enter their shares, at the same time, to rebuild the main target key (TK) to access sensitive data within the system. Normally, the number of shares is limited by the number of zeros within TK as of our focus on the recent counting-based secret sharing strategy. If the number of participants is more than TK zeros, the complete system cannot work needing to reconsider regenerating TK again. In this work, we improved the original system of counting-based secret sharing to accommodate more participants via longer trustworthy TK selection. We proposed several possible models to enlarge the number of participants for applicable share’s keys generated from TK. The trustworthy security randomness of the new shares and adjusted target keys were all measured to select the best choice based on standard reliability randomness test. The study experimented the proposal on typical simulations applied on different target keys applicable sizes. The results presented that the final target key TK created as having the highest ratio of randomness to be preferred choice proven secure and reliable to protect information within the system.

This article proposes a physical unclonable function (PUF) based on the contact formation probability. The contact here is the interconnect layer between the metal and the silicon in a chip. As the contact is designed smaller than the size given in the design rule, the contact formation becomes stochastic in a certain range of contact hole sizes and can be a random source for the PUF. Consequently, once the contact state is determined to be either open or short, its connectivity does not change over time under noisy environmental conditions, such as temperature, supply voltage, humidity variations, and so on. The reliability of the proposed contact PUF is verified through seven reliability tests defined by the Joint Electron Device Engineering Council (JEDEC) standards. No bit errors occur in any of the 366 chips tested. The bitcell is designed using a digital standard cell structure and scattered throughout the chip embedded in other logic gates. This makes it difficult to find the bitcell position. The proposed contact PUF is fabricated using 0.13- $\mu \text{m}$ CMOS technology. It achieves 49.99% uniqueness and 0.99973 entropy and passes all applicable randomness tests given by the National Institute of Standards and Technology (NIST) SP 800-22.

The secret sharing scheme is a data security tool to provide safe reliability and robustness for multi-user authentication systems. This work focus on expanding counting-based secret sharing technique to generate more shares for more handlers’ services considering security as well as simple and fast computation. The research considers resolving some originally published imperfections in the share’s generation phase proposing new smart expansion models validated to be optimized practical and efficient. We proposed seven possible models to expand the number of participants for applicable share’s keys generated from the target key. The smart security randomness of the shares and target keys adjusted were all analyzed to select the best choice based on consistency randomness test. The study further used standard simulations applied on two different applicable multimedia target keys sizes of 16-bits and 64-bits showing attractive remarks pointing for further research improvements to continue. The improved smart system has been analyzed according to distortion security and capacity parameters showing attractive contributions.

This paper presents a novel simple 4-D dissipative autonomous hyperchaotic system with a saddle-point index-2 equilibrium point. The dynamics of the new system consists of nine terms with two nonlinear terms. Thus, the proposed system is one of the simplest 4-D hyperchaotic systems. The new system also shows multistability behavior for some range of its parameters. Bifurcation diagrams, Lyapunov spectrum, Kaplan-Yorke dimension, and phase plots are used to analyze the complex dynamical behavior of the system. The discrete-time equivalent of the presented hyperchaotic system is made by using the Euler algorithm for improving the embedded chaos-based engineering applications on FPGA. Then, the design of a novel TRNG having chaotic entropy seed has been performed utilizing FPGA-based 4-D hyperchaotic system structure. The Euler-based model in the creation phase on FPGA has been described using VHDL with 32-bit IEEE 754-1985 floating-point format. The designed hyperchaotic system and TRNG unit have been synthesized using Xilinx ISE Design Tools, and chip statistics obtained from place-and-route process have been presented by testing in the Virtex-6 FPGA chip of Xilinx family. The numbers generated in high data rates of 185.447 Mbit/s have been obtained with 370.894 MHz clock frequency for the implementation of the novel TRNG unit. In the last stage, randomness tests of the generated random numbers have been carried out and the generated random numbers have passed successfully all randomness tests.

One of the practical applications of chaotic systems is the design of a random number generator. In the literature, generally random number generators are designed using discrete time chaotic systems. The reason for the use of the discrete time chaotic systems in the design architecture is that the latter have a simpler structure than the continuous time chaotic systems. In order to observe chaos in continuous time systems, the system must have at least three degrees. It is shown that for fractional order chaotic systems chaos can be observed even in a lower system degree. The aim of this study is to develop a random number generator using a fractional order chaotic Chua system. The proposed generator is analysed using various randomness tests. The analysis results show that the proposed generator passes the random requirements successfully. On the one hand, this study is important because it demonstrates the practical application of fractional order chaotic systems. On the other hand, it provides an alternative to designs based on discrete time chaotic systems.

The discrete Fourier transform test is a randomness test included in NIST SP800-22. However, the variance of the test statistic is smaller than expected and the theoretical value of the variance is not known. Hitherto, the mechanism explaining why the former variance is smaller than expected has been qualitatively explained based on Parseval’s theorem. In this paper, we explore this quantitatively and derive the variance using Parseval’s theorem under particular assumptions. Numerical experiments are then used to show that this derived variance is robust.

Wireless body area network is a low-power and high-security wireless communication protocol specially used in the medical environment. It requires a highly secure encryption algorithm to ensure that information related to a patient’s vital signs cannot be accessed by an attacker. In this article, a security scheme based on chaotic mapping for WBAN is proposed. This algorithm makes use of the hybrid chaotic system obtained by the combination of Logistic and Tent mapping as the sequence generator, which can select the effective precision according to the importance of the transmitted information to ensure the reasonable allocation of computing resources, including floating-point encryption, fixed-point 32-bit encryption, fixed-point 24-bit encryption, and fixed-point 16-bit encryption. In the randomness test of the sequence, it can be seen that the sequence autocorrelation coefficient generated by the combined chaotic system is close to 0 and has a flat power spectrum. At the same time, the sequences produced by the floating-point system and 32-bit fixed-point system have passed the NIST test, which proves that combined chaos overcomes the influence of sequence length and finite precision. Experimental analysis and performance comparison show that the proposed encryption algorithm has sufficient security to resist common attacks.

High-level security with a large keyspace and a short processing time is needed in digital image encryption. Generally, an encryption method that produces a large keyspace is characterized by a relatively slow encryption process. In this paper, we propose a new image encryption method that uses two chaotic pseudosets. A gradual deletion of the input set (GDIS) is introduced to enhance the process of chaotic permutation multicircular shrinking (CPMCS), herein referred to as GDIS CPMCS, to diffuse the image pixels and control the shift distance of the row and column rotations of an image. The proposed encryption scheme offers some advantages: it has a larger keyspace than the referenced image encryption schemes and a shorter processing time than CPMCS. The processing time of the proposed image encryption method with the GDIS CPMCS algorithm is 16.7 times faster for a gray image and 43 times faster for a color image than that in our previous work. Based on histogram and entropy analyses, the proposed scheme is also robust to statistical analysis. Moreover, the ciphered image has a very high degree of randomness according to the National Institute of Standards and Technology (NIST) randomness test results. In terms of differential analysis, a one-bit change in the original image leads to a substantial change in the ciphered image, as indicated by the unified average change intensity (UACI) and number of pixel change rate (NPCR) scores of 33.45% and 99.61%, respectively. Furthermore, GDIS CPMCS is robust to salt-and-pepper, Poisson, Gaussian, and speckle noise, with peak signal-to-noise ratios (PSNRs) higher than 14. The scheme is also robust to data loss since a reconstructed image with 50% data loss can be recognized, as indicated by a PSNR of 11.4.

We experimentally demonstrate a strong physically unclonable function (PUF) circuit featuring >280 challenge-response pair (CRP) capacity, ${F }= 250$ -nm half-pitch $64\times 64$ ReRAM circuits. Passive crossbar circuits with $4{F} ^{2}$ area per crosspoint device and reduced peripheral overhead, not requiring any circuitry for programming, result in an extremely compact design, while low-power consumption is achieved by keeping ReRAM devices in the highly resistive, virgin states. The key contributions of this letter is a novel leakage injection approach using an electrically isolated portion of the crossbar array, which boosts PUF’s robustness, and a key-booking scheme, which dramatically improves reliability across a wide temperature range of operation and further increases PUF circuit density by reducing error correcting overheads. The experimental results showed near-ideal functional performance metrics, including 49.55% uniformity, 49.95% diffuseness, and 49.25% uniqueness. The measured response also passed all relevant NIST randomness tests.

In this paper, we propose a new system for a sequential secret key agreement based on 6 performance metrics derived from asynchronously recorded EEG signals using an EMOTIV EPOC+ wireless EEG headset. Based on an extensive experiment in which 76 participants were engaged in one chosen mental task, the system was optimized and rigorously evaluated. The system was shown to reach a key agreement rate of 100%, a key extraction rate of 9%, with a leakage rate of 0.0003, and a mean block entropy per key bit of 0.9994. All generated keys passed the NIST randomness test. The system performance was almost independent of the EEG signals available to the eavesdropper who had full access to the public channel.

This paper introduces an effective image encryption approach that merges a chaotic map and polynomial with a block cipher. According to this scheme, there are three levels of encryption. In the first level, pixel positions of the image are scuffled into blocks randomly based on a chaotic map. In the second level, the polynomials are constructed by taking N unused pixels from the permuted blocks as polynomial coefficients. Finally, the third level a proposed secret-key block cipher called extended of tiny encryption algorithm (ETEA) is used. The proposed ETEA algorithm increased the block size from 64-bit to 256-bit by using F-function in type three Feistel network design. The key schedule generation is very straightforward through admixture the entire major subjects in the identical manner for every round. The proposed ETEA algorithm is word-oriented, where wholly internal operations are executed on words of 32 bits. So, it is possible to efficiently implement the proposed algorithm on smart cards. The results of the experimental demonstration that the proposed encryption algorithm for all methods are efficient and have high security features through statistical analysis using histograms, correlation, entropy, randomness tests, and the avalanche effect.

In this paper, we propose an in-memory True Random Number Generator (TRNG) using Voltage-Controlled MRAM that doesn't require calibration of the writing pulse's width and amplitude. Previous solution using Spin Transfer Torque (STT) MRAM requires calibration for every MTJ, thus making the multi-row random number generation inside the memory impossible. We also propose a 100% relative throughput digital bias correction circuit that doesn't degrade bit rate. The VC- MTJs are fabricated in CMOS BEOL compatible process with an 80 nm diameter and high TMR ratio of 160%. MRAM array circuits and bias correction circuits are fabricated in 65 nm CMOS technology and wire-bonded with the VC-MTJ devices. Multiple VC-MTJs are tested and shown to pass all NIST randomness tests.

The concept of color visual cryptography with truly random shares is proposed. The randomness was confirmed with the battery of 15 NIST randomness tests. The two shares are generated as two equal purely random sequence of R, G, B and black pixels. Coding is performed by swapping the pixels in the second share in small subregions called segments. The criterion for swapping is that after superimposing the shares, some pixels remain color and the remaining ones are covered so that they appear as black. The color pixels form a color image in the way of dithering in the RGB space. The secret is in principle decrypted with the unarmed human eye; however, it can be easily further reconstructed numerically to attain the quality very close to that of the dithered source image. It was observed that the coding can be optimized by varying the dimensions of the segments and the palettes in the dithering.

True random number generators are in high demand for secure cryptographic algorithms. Unlike algorithmically generated pseudo-random numbers, they are unclonable and non-deterministic. In this paper, we extract the white noise from stochastic Brownian Markov trajectories and use it to generate random numbers that qualify NIST standard tests of randomness. We trap colloidal particles in water using optical tweezers and record its confined Brownian motion in real-time. Next, in a two-step process, we use the initial section of incoming data to train and calibrate our iterative algorithm on the trap stiffness and viscosity of the solution based on the autocorrelation and power spectrum properties of the noise; then, we extract random arrays from the next section of the data. Interestingly, we get the best random number sequence for the best calibration. We test the random number sequence, which we have obtained, using standard randomness tests and observing the randomness to improve with increasing sampling frequencies.1 In the next steps, we extend this method to a wider class of processes, such as an optically trapped particle modulated by a square pulse or an external colored noise generated by an Ornstein Uhlenbeck process – we estimate the timescale of both the modulation and viscous effect using our algorithm.

In this paper, the modulation of the conductance levels of resistive random access memory (RRAM) devices is used for the generation of random numbers by applying a train of RESET pulses. The influence of the pulse amplitude and width on the device resistance is also analyzed. For each pulse characteristic, the number of pulses required to drive the device to a particular resistance threshold is variable, and it is exploited to extract random numbers. Based on this behavior, a random number generator (RNG) circuit is proposed. To assess the performance of the circuit, the National Institute of Standards and Technology (NIST) randomness tests are applied to evaluate the randomness of the bitstreams obtained. The experimental results show that four random bits are simultaneously obtained, passing all the applied tests without the need for post-processing. The presented method provides a new strategy to generate random numbers based on RRAMs for hardware security applications. This research was supported in part by the Spanish Ministry of Science, Innovation and Universities under Grant PID2019-103869RB-C33/ AEI /10.13039/501100011033, and the FEDER program under Grant TEC2017-84321-C4-1-R.

This article presents a reconfigurable physically unclonable function (PUF) design fabricated using 65-nm CMOS technology. A subthreshold-inverter-based static PUF cell achieves 0.3% native bit error rate (BER) at 0.062-fJ per bit core energy efficiency. A flexible, native transistor-based voltage regulation scheme achieves low-overhead supply regulation with 6-mV/V line sensitivity, making the PUF resistant against voltage variations. Additionally, the PUF cell is designed to be reconfigurable with no area overhead, which enables stabilization without redundancy on chip. Thanks to the highly stable and self-regulated PUF cell and the zero-overhead stabilization scheme, a 0.00182% native BER is obtained after reconfiguration. The proposed design shows 0.12%/10 {\deg}C and 0.057%/0.1-V bit error across the military-grade temperature range from -55 {\deg}C to 125 {\deg}C and supply voltage variation from 0.7 to 1.4 V. The total energy per bit is 15.3 fJ. Furthermore, the unstable bits can be detected by sweeping the body bias instead of temperature during enrollment, thereby significantly reducing the testing costs. Last but not least, the prototype exhibits almost ideal uniqueness and randomness, with a mean inter-die Hamming distance (HD) of 0.4998 and a 1020x inter-/intra-die HD separation. It also passes both NIST 800-22 and 800-90B randomness tests., Comment: This work has been accepted by 2020 IEEE Journal of Solid-State Circuits (JSSC)

Recent advancements in the domain of quantum computing are posing a security threat to the classical cryptography algorithms. Popular symmetric and asymmetric cryptosystems including RSA, ECC, DES, Diffie-Hellman etc. can be broken by a quantum computer executing Shors and Grovers algorithms. This motivated scientific community to design newer encryption schemes to address security vulnerabilities. Hash, Code, Lattice, Multivariate Polynomial based cryptography algorithms, known as post-quantum cryptography algorithms (PQC), exhibit resistance against classical as well as quantum crypto-attacks. Apart from these PQC algorithms, a relatively new method of constructing cryptosystems utilizing the unpredictability property of discrete chaotic dynamic systems has become noteworthy from the practical perspective. In this paper, we present a novel approach to design an encryption scheme based on the chaotic dynamic physical system, which is derived from a mechanical model depicting nonlinear dynamics and exhibits resistance against various attacks. The effectiveness of the proposed cryptography scheme is validated against various standard tests, such as Lyapunov exponents test, bifurcation diagrams, sensitivity to parametric and to initial values, ergodicity, collision test, NIST, diehard randomness test etc. This algorithm is also verified through an FPGA implementation to assess its usage in low power high throughput applications as well. The power consumption and resource utilization of the proposed design are 56 % and 72.6 %, respectively, as compared to other known methods while operating at 628.14 MHz. It is observed that the proposed design can work efficiently with various wide range of applications. It is observed that the proposed design can work efficiently with various wide range of applications. The average power and area of its ASIC implementation at 180 nm technology are 61.8836 mW and 0.20374 mm 2 at 250 MHz, respectively.

In this paper a new Pseudorandom Number Generator based on compositions of abstract automata is presented. We show that it has full cycle with length of 2^128. It is also shown that the output satisfies the statistical requirements of the NIST randomness test suite.

A calibration and feedback control-free latch-based true random-number generator (TRNG) is presented. It features a mismatch self-compensation and a random noise enhancement technique to drastically improve the noise-to-mismatch ratio. By employing the XOR function of only 4-bit entropy sources, the proposed TRNG can efficiently operate across a wide voltage (0.3~1.0 V) and temperature (−20~100°C) range. An 8-bit von Neumann with waiting (VN8W) post-processing technique is used to extract full entropy bitstreams, which have been verified by the NIST-SP 800-22 randomness tests. Robustness against supply noise injection attack is also demonstrated. The proposed TRNG is fabricated in 130-nm CMOS technology and achieves the state-of-the-art energy of 0.186 pJ/bit at 0.3 V with a core area of 661 um2 (0.039 MF2).