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Abstract Soft error resilience has become an essential design metric in electronic computing systems as advanced technology nodes have become less robust to high‐charged particle effects. Designers, therefore, should be able to assess this metric considering several software stack components running on top of commercial processors, early in the design phase. With this in mind, researchers are using virtual platform (VP) frameworks to assess this metric due to their flexibility and high simulation performance. In this regard, herein, this goal is achieved by analysing the soft error consistency of a just‐in‐time fault injection simulator (OVPsim‐FIM) against fault injection campaigns conducted with event‐driven simulators (i.e. more realistic and accurate platforms) considering single and multicore processor architectures. Reference single‐core fault injection campaigns are performed on RTL descriptions of Arm Cortex‐M0 and M3 processors, while gem5 simulator is used to multicore Arm Cortex‐A9 scenarios. Campaigns consider different open‐source and commercial compilers as well as real software stacks including FreeRTOS/Linux kernels and 52 applications. Results show that OVPsim‐FIM is more than 1000× faster than cycle‐accurate simulators and up to 312× faster than event‐driven simulators, while preserving the soft error analysis accuracy (i.e. mismatch below to 10%) for single and multicore processors.

Abstract Testability transformation (TT) is a source‐to‐source programme transformation that aims to improve the ability of a given test generation method to generate test data for the original programme. Herein, the correctness of testability transformations is shown. Translation validation is the process of proving that the transformed programme is a correct translation of the source programme being compiled. It is widely used to verify the correctness of various compiler optimizations and transformations during scheduling. The value propagation based equivalence checking (VP) method is an efficient translation validation approach proposed to verify the correctness of various compiler optimization applied during scheduling in high‐level synthesis. VP‐based translation validation of testability transformations is proposed. In particular, it is identified that the existing VP method fails to show the equivalence for some of the TTs. A dynamic cutpoint selection scheme and an enhancement to the VP method to overcome these limitations are shown. The enhanced VP method, called VP_TT, successfully shows the equivalence for the TTs where the VP method fails. Experimental results confirm the usefulness of VP_TT in the verification of testability transformations.

Unified Modelling Language (UML) is essentially a de‐facto standard for software modeling and supported with many modeling tools. In this study, 58 UML tools have been analysed for modelling viewpoints, analysis, transformation & export, collaboration, tool integration, scripting, project management, and knowledge management. The analysis results reveal important findings: (i) 11 UML tools support multiple viewpoints, (ii) 17 tools support large‐viewpoint management, (iii) Umple and Reactive Blocks support formal verification, (iv) 9 tools support the simulation of activity diagrams, (v) while 14 tools check pre‐defined well‐formedness rules, 8 of them support user‐defined rules, (vi) 16 tools support scripting, (vii) 29 tools support code‐generation and 18 of them support round‐trip engineering, (viii) Java is the top popular language, (ix) 38 tools export UML models as image, 32 tools export as HTML, and 32 tools export as XML/XMI, (x) 17 tools enable versioning and 13 of them support multi‐user access, (xi) 15 tools support the plug‐in extensions and 12 tools support the IDE integration, (xii) 6 tools support project management, and (xiii) while most tools provide user‐manuals, interactive guidance is rarely supported. The results will be helpful for practitioners in choosing the right tool(s) and the tool developers in determining the weaknesses/strengths. [ABSTRACT FROM AUTHOR]

In recent years, smart TVs have become more common, making them need to be included as targets for the software industry. In this study, the authors developed a code generator framework and demonstrated it in an architectural view. The proposed framework converts C# programming language based projects, in a Windows Forms or a Windows Phone Application project, into native smart TV Platform applications. The selected primary smart TV platforms assigned for application conversion were Android TV, Firefox OS, and Tizen OS. The authors enabled developers to generate native codes for all three platforms from a single code base using model to model conversion, as in the model driven architecture approach with the use of the open source Roslyn C# language compiler. The need for creating projects for every single platform to make them run on different platforms will thus be eliminated and development cycles shortened. By doing so, the time required to develop an application for each platform is reduced while keeping the generated applications' quality as high as the original application. To show the functionality, the proposed approach is applied in three case studies. The success of the code conversion is satisfactory and converted applications are functional. [ABSTRACT FROM AUTHOR]

This case study analyses the possibilities to improve the execution time of model-based developed software by applying optimisations during code generation and compilation. The present case study is performed on flight control software, for which safety aspects are accounted throughout the development. Therefore, a formally verified compiler is used for the optimisation during the compilation. The optimisation is evaluated by execution time measurements on the target and a static worst-case execution time analysis. Based on the results, recommendations for certain model patterns are given, which impact the worst-case execution time analysis.

A fully automatic translation of unified modeling language (UML) models to complete source code is not reported so far because some implementation details will not be there in the model, or a single UML model is not enough for complete code generation, or some model elements may not be directly convertible to source code. These issues are addressed in this study. The authors take workflow modelling and automation as the focus of their research. Hence, UML activity diagram is considered. Activity diagram alone cannot give the implementation details like object interactions. A formal association is found between activity and sequence diagrams to add object interaction details to the work flow. Moreover, the authors formulate an algorithm, Am_To_Prototype, which is composed of two subroutines named Method_Body & Excecution_Logic, to generate code from the combined model of activity and sequence diagrams consisting of concurrent activities. The authors compare the proposed method with other research outcomes with respect to workflow automation, support for concurrency, etc. The proposed algorithms are able to generate class definition, method definition and control flow. A case study is presented that demonstrates the algorithm, to generate Java code for the ATM operation. [ABSTRACT FROM AUTHOR]

For protecting an intellectual property (IP) core, it must be harder to reverse engineer. Structural obfuscation can play an important role in achieving this goal. A novel structural obfuscation methodology during architectural synthesis using multiple compiler‐based high‐level transformations (HLTs) that yield functionally equivalent designs (data flow graphs) which are camouflaged in identity is proposed. The proposed obfuscation methodology is driven through a number of HLT techniques such as redundant operation elimination, logic transformation and tree height transformation. In addition to performing obfuscation, performing area–delay tradeoff during exploring low‐cost obfuscated design is also possible using these HLT techniques in the proposed methodology. Owing to multiple stages of HLT incorporated in the proposed approach during obfuscation, it yields a highly robust design which on integration with particle swarm optimisation‐based exploration framework produced low‐cost obfuscated IP designs. Results of the proposed approach yielded an enhancement in strength of obfuscation of 20.19% and reduction in obfuscated design cost of 59.66% compared with a similar approach. [ABSTRACT FROM AUTHOR]

Manufacturing variability is an increasingly significant problem. Silicon devices that are designed to be identical will display widely ranging characteristics after manufacture. Power use, supported clock frequencies and lifespan may all vary considerably. This is of particular concern for embedded systems because of their extensive use of complex system‐on‐chip (SoC)‐based architectures. If this variability is not tolerated by the software, then manufacturing yields are reduced and devices are not used efficiently. This study discusses a novel approach to the integration of variability‐mitigation techniques that uses model‐driven engineering to explicitly consider variability as part of the development process. Developers can build systems that are much more resilient to variability effects, allowing systems to have higher yields, lower costs and greater reliability. The approach uses code generation and code transformation to simplify design‐space exploration and reduce time‐to‐market. The approach is illustrated with an example of audio processing on a complex multiprocessor SoC with simulated variability, and it is shown to be increasingly effective as system variability becomes more significant. [ABSTRACT FROM AUTHOR]

Design by contract (DbC) is a software development methodology that focuses on clearly defining the interfaces between components to produce better quality object-oriented software. Though there exists ample support for DbC for sequential programs, applying DbC to concurrent programs presents several challenges. Using Java as the target programming language, we tackle such challenges by augmenting the Java Modelling Language (JML) and modifying the JML compiler (jmlc) to generate runtime assertion checking code to support DbC in concurrent programs. We applied our solution in a carefully designed case study on a highly concurrent industrial software system from the telecommunications domain to assess the effectiveness of contracts as test oracles in detecting and diagnosing functional faults in concurrent software. Based on these results, clear and objective requirements are defined for contracts to be effective test oracles for concurrent programs whilst balancing the effort to design them. Effort is measured indirectly through the contract complexity measure (CCM), a measure we define. Main results include that contracts of a realistic level of completeness and complexity can detect around 76 percent of faults and reduce the diagnosis effort for such faults tenfold. We, therefore, show that DbC can be applied to concurrent software and can be a valuable tool to improve the economics of software engineering. [ABSTRACT FROM PUBLISHER]

Traditional dependence tests detect dependences with linear array subscripts, but only give passive results to those with non‐linear expressions. It may result in a multitude of pseudo‐dependences. To maximise the parallelism of applications and improve an optimising compiler's ability of detecting dependences between program statements, it is necessary to develop a non‐linear dependence test to eliminate these pseudo‐dependences. This study presents a new non‐linear dependence test by analysing the optimal solution of the quadratic subscripts with the index bounds constraints. The authors prove that the non‐linear dependences caused by subscripts, which can be written in the form of quadratic programming model, are able to be detected, and introduce a non‐linear dependence testing algorithm based on quadratic programming. The effectiveness of this algorithm is verified. The authors developed a prototype implementation of the test with the Open64 compiler and evaluated it using some real world applications from Perfect Club benchmarks and Spec2006 benchmark suites. The experimental results indicate that, compared to existing testing methods, the quadratic programming (QP) test is more efficient for quadratic cases. [ABSTRACT FROM AUTHOR]

Unified modelling language (UML) is a visual modelling language, which has gained popularity among software practitioners. In a model‐driven software development environment, the existing UML tools mainly support automatic generation of structural code from UML class diagrams. However, the code generation from UML diagrams such as statechart, activity, collaboration and sequence diagrams (SDs) are not supported by most UML tools and also have scarcely been reported in the literatures. This work proposes an approach to automatic generation of code from UML 2.x SDs of use cases. From the XML metadata interchange (XMI) representation of an SD of a use case, the authors construct a graph model called sequence integration graph (SIG). The SIG encapsulates information related to messages, control flow and method scope of interactions. These information are then used to generate code. The proposed approach has been tested using a number of real‐life application systems and the results substantiate the efficacy of the approach to synthesise the code for controller classes. The authors observe that approximately 48% of the total lines of code within controller class methods can be generated with the proposed approach. The proposed approach can be easily extended to other behavioural UML models such as interaction‐overview diagrams, communication diagrams and activity diagrams. [ABSTRACT FROM AUTHOR]

Single instruction, multiple data (SIMD) extensions have been a feature of choice for processor manufacturers for a couple of decades. Designed to provide significant accelerations, they require expertise, the use of potentially fragile compiler support, or vendor-specific libraries. Here, a C++ template library called Boost.SIMD is presented that simplifies the exploitation of SIMD hardware within a standing C++ programming model. [ABSTRACT FROM AUTHOR]

In this paper, we present a technique for compact representation of execution sequences in terms of efficient looping constructs. Here, by a looping construct, we mean a compact way of specifying a finite repetition of a set of execution primitives. Such compaction, which can be viewed as a form of hierarchical run-length encoding (RLE), has application in many very large scale integration (VLSI) signal processing contexts, including efficient control generation for Kahn processes on field-programmable gate arrays (FPGAs), and software synthesis for static dataflow models of computation. In this paper, we significantly generalize previous models for loop-based code compaction of digital signal processing (DSP) programs to yield a configurable code compression methodology that exhibits a broad range of achievable tradeoffs. Specifically, we formally develop and apply to DSP hardware and software synthesis a parameterizable loop scheduling approach with compact format, dynamic reconfigurability, and low-overhead decompression. [ABSTRACT FROM AUTHOR]

Indirect jumps are used to implement increasingly-common programming language constructs such as virtual function calls, switch-case statements, jump tables, and interface calls. Unfortunately, the prediction accuracy of indirect jumps has remained low because many indirect jumps have multiple targets that are difficult to predict even with specialized hardware. This paper proposes a new way of handling hard-to-predict indirect jumps: dynamically predicating them. The compiler identifies indirect jumps that are suitable for predication along with their control-flow merge (CFM) points. The microarchitecture predicates the instructions between different targets of the jump and its CFM point if the jump turns out to be hard-to-predict at run time. We describe the new indirect jump predication architecture, provide code examples showing why it could reduce the performance impact of jumps, derive an analytical cost-benefit model for deciding which jumps and targets to predicate, and present preliminary evaluation results. [ABSTRACT FROM PUBLISHER]

We propose the use of the confidence interval of estimated mean (CIM), a metric based on statistical sampling theory, to evaluate the quality of a given phase classification and for comparing different phase classification schemes. Previous research on phase classification used the weighted average of coefficient of variation (CoVwa) to estimate phase classification quality. We found that the phase quality indicated by CoVwa could be inconsistent across different phase classifications. We explain the reasons behind this inconsistency and demonstrate the inconsistency using data from several SPEC CPU2000 benchmark programs. We show that the confidence interval of estimated mean (CIM) correctly estimates the quality of phase classification with a meaningful statistical interpretation. [ABSTRACT FROM PUBLISHER]

Two trends - the increasing complexity of computer systems and their deployment in mission- and life-critical applications - are driving the need to provide applications with security and reliability support. Compounding the situation, the Internet's ubiquity has made systems much more vulnerable to malicious attacks that can have far-reaching implications on our daily lives. Clearly, the traditional one-size-fits-all approach to security and reliability is no longer sufficient or acceptable from the user perspective. In this article, we introduce the concept of application-aware checking as an alternative. By extracting application via recent breakthroughs in compiler analysis and enforcing the characteristics at runtime with the hardware modules embedded in the reliability and security engine (RSE), it's possible to achieve security and reliability with low overheads and false-positive rates [ABSTRACT FROM PUBLISHER]

Chip multiprocessors are of increasing importance due to difficulties in achieving higher clock frequencies in uniprocessors, but their success depends on finding useful work for the processor cores. This paper addresses this challenge by presenting a simple compiler approach that extracts non-speculative thread-level parallelism from sequential codes. We present initial results from this technique targeting a validated dual-core processor model, achieving speedups ranging from 9-48% with an average of 25% for important benchmark loops over their single-threaded versions. We also identify important next steps found during our pursuit of higher degrees of automatic threading [ABSTRACT FROM PUBLISHER]

A component based modeling language with the component interfaces derived from the elements of the Petri net theory called CNet is presented in this paper. In contrast to IEC 61499 function blocks that define the flow of events and data separately, CNet models them combined as colored tokens. The event-discrete behavior of CNet components is described by a special class of colored Petri nets with timed arcs and sharpened semantics in order to allow automatic generation of possibly concurrent Java code. In this paper, the state space of CNet components is analyzed and a novel event-discrete "handler-based" execution model that implicitly models an automaton is introduced. [ABSTRACT FROM PUBLISHER]

A large and growing number of digital signal processor (DSP) applications are initially prototyped in Matlab, a high-level language that provides concise, intuitive statement of mathematical computations. Work in this elegant language stops at the prototyping stage due to the absence of an effective automatic path to implementation. This articles overviews a set of techniques for automating an implementation path from Matlab to DSPs and provides preliminary results on the effectiveness of such techniques. [ABSTRACT FROM PUBLISHER]