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Summary: This paper presents a subthreshold CMOS voltage reference (VR) that utilizes self‐biased circuits. This voltage reference includes temperature compensation circuits to expand its operating temperature range and reduce its temperature coefficient. The proposed CMOS voltage reference is designed using a standard 0.18‐μm CMOS process and has a small area of only 0.005 mm2. Post‐layout simulation results demonstrate that the power consumption of the circuit at room temperature (25°C) is only 1.65 nW at a power supply voltage of 1 V. In this case, the voltage reference output is 316.56 mV, with an average temperature coefficient (TC) of 11.14 ppm/°C in a wide temperature range from −40°C to 140°C. Furthermore, the line sensitivity (LS) of the circuit is 0.024%/V, and the power supply rejection ratio (PSRR) of the circuit is −86.5 dB at 10 Hz. In summary, the subthreshold CMOS voltage reference structure proposed in this paper demonstrates excellent performance characteristics, such as low power consumption, a small area, and high‐temperature stability. These features make it a promising candidate for voltage reference for low‐power applications with significant changes in environmental temperature. [ABSTRACT FROM AUTHOR]

This paper describes an analysis of power supply rejection and noise improvement techniques for an envelope-tracking power amplifier. Although the envelope-tracking technique improves efficiency, its power supply rejection ratio is much lower than that of average power tracking or a fixed-supply power amplifier. In FDD systems with the envelope-tracking technique, the low power supply rejection ratio generates much output noise in the RX band and degrades the receiver's sensitivity. An SM is designed by using a 130 nm CMOS process, and the chip die area is 2 × 2 mm2 with a 25-pin wafer-level chip-scale package. The designed SM achieved peak efficiencies of 78–83% for LTE signals with a 5.8 dB PAPR and various channel bandwidths. For the low-output-noise-supply modulator, noise reduction techniques using resonant-frequency tuning and a notch filter are employed, and the measured results show maximum 1.8/5/5.3/3.8/3 dB noise reduction in LTE bands B17/B5/B2/B3/B7, respectively. [ABSTRACT FROM AUTHOR]

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Bandgap reference (BGR) circuits play a crucial role as voltage reference generators for other components within a variety of analog integrated circuits. Therefore, their power supply rejection ratio (PSRR), which represents the BGR’s ability to maintain a stable output in the presence of supply ripples, has a substantial impact on the overall circuit performance and is consequently worthy of attention. In this work, the design of a 65nm-CMOS BGR circuit and the computational approach to optimize its PSRR value are presented. Our proposed BGR circuit incorporates a modification in the op-amp structure to enhance the PSRR parameter. Detailed explanations of the proposed op-amp’s differential gain calculation and the PSRR parameter formula are provided. Additionally, we employ the particle swarm optimization (PSO) algorithm to maximize PSRR while satisfying other specifications. Four distinct approaches for utilizing the inertia weight parameter of the PSO algorithm are explored: two newly developed techniques (PSO - local exploitation orienter (PSO-LEO) and PSO - global exploration orienter (PSO-GEO)) together with two conventional approaches. A comprehensive comparative analysis reveals the superiority of our proposed PSO-GEO technique. Ultimately, our 65 nm CMOS bandgap circuit exhibits exceptional performance, featuring a temperature coefficient of 6.4056 ppm/°C and a PSRR of 99.9896 dB at 1 kHz. In conclusion, this work contributes substantially through op-amp architecture modification, PSRR optimization via the PSO algorithm, and introducing new inertia weight parameter utilization strategies and analyzing them.

This letter proposes an input-independent loop type-III buck converter (ILT3C) enhancing the security of edge devices. Compared to a conventional type-III buck converter, the ILT3C maximally improves power-supply rejection ratio as much as 34.1 dB to be robust against power injection attack. It also reduces the peak of electromagnetic interference as much as 35.8 dBμV to enhance the security from power side-channel attack. Furthermore, the external components such as an inductor and a capacitor of the converter should be integrated into a package to minimize its exposure to unknown hacking risks. Thus, the proposed converter operates with a high switching frequency (fsw) of 20 MHz and it can reduce the size of the external components enough to be placed in the package. The prototype converter was implemented in a 0.18-μm CMOS process. This ILT3C achieves the maximum efficiency of 90.7% and occupies an active area of 0.195 mm2. [ABSTRACT FROM AUTHOR]

In the automotive domain, the vast majority of testing is performed through simulations, which can validate a system design before the actual implementation and can emphasize eventual faults in the design process. Hence, the simulation is of utmost importance. Behavioral models are necessary for the creation of each electronic device desired in the system, and some of the components have very complex behavior: low-dropout linear voltage regulators (LDOs), gate drivers, and switching regulators. In the automotive industry, LDOs are essential components because they power all the other subsystems and very accurate behavior is needed to make sure that the system behaves as in reality. LDO models are already commercially available and most of their intrinsic characteristics are modeled (dropout voltage, line regulation, load regulation, etc.). However, one characteristic that is extremely useful, yet the hardest to model, is the power supply rejection ratio (PSRR). This paper proposes a new PSRR modeling technique for automotive low-dropout voltage regulators. The new PSRR characteristic was modeled for an automotive LDO product in a Texas Instruments portfolio, which has a commercially available model, and was simulated using the PSpice Allegro simulator and the OrCAD Capture CIS environment. [ABSTRACT FROM AUTHOR]

Copyright of Electronic Components & Materials is the property of Electronic Components & Materials and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In order to reduce the temperature coefficient of band-gap reference source and improve the flexibility of temperature compensation，an improved piecewise linear compensation method was designed. A compensation current of seven different slopes in the whole temperature region was generated with the temperature of the bipolar transistor. Finally, The high order temperature components of the reference voltage were superimposed by the current mode. Based on the 0.25 μm BCD process it designed gap reference source here. HSPICE simulation results indicate that under 5 V power supply voltage and within -40 ℃~125 ℃ temperature range, the temperature coefficient of the reference voltage is only 0.37×10-6/℃. The power rejection ratio of the low frequency circuit is -85 dB. Within the range of 2 V~5 V, the linear adjustment rate of the reference voltage is 0.09 mV/V.

In the automotive domain, the vast majority of testing is performed through simulations, which can validate a system design before the actual implementation and can emphasize eventual faults in the design process. Hence, the simulation is of utmost importance. Behavioral models are necessary for the creation of each electronic device desired in the system, and some of the components have very complex behavior: low-dropout linear voltage regulators (LDOs), gate drivers, and switching regulators. In the automotive industry, LDOs are essential components because they power all the other subsystems and very accurate behavior is needed to make sure that the system behaves as in reality. LDO models are already commercially available and most of their intrinsic characteristics are modeled (dropout voltage, line regulation, load regulation, etc.). However, one characteristic that is extremely useful, yet the hardest to model, is the power supply rejection ratio (PSRR). This paper proposes a new PSRR modeling technique for automotive low-dropout voltage regulators. The new PSRR characteristic was modeled for an automotive LDO product in a Texas Instruments portfolio, which has a commercially available model, and was simulated using the PSpice Allegro simulator and the OrCAD Capture CIS environment.

This paper presents design of a high-precision curvature-compensated bandgap reference (BGR) circuit implemented in a 0.35 μm CMOS technology. The circuit delivers an output voltage of 1.09 V and achieves the lowest reported temperature coefficient of ~3.1 ppm/°C over a wide temperature range of [−20°C/+100°C] after trimming, a power supply rejection ratio of −80 dB at 1 kHz and an output noise level of 1.43 μV $$ \sqrt {\text{Hz}} $$ at 1 kHz. The BGR circuit consumes a very low current of 37 μA at 3 V and works for a power supply down to 1.5 V. The BGR circuit has a die size of 980 μm × 830 μm.

A power-efficient bridge-to-digital sensing interface is proposed, which also offers immunity against power supply noise. The interface utilizes duty-cycling to reduce the static power consumption of resistive bridge sensors, which are commonly used in implantable, wearable, and internet of things (IoT) applications, such as intracranial pressure (ICP) sensing and blood pressure (BP) monitoring. The proposed interface uses a revised version of the pseudo-pseudo differential (PPD) topology with the ping-pong technique to reduce the complexity of traditional fully-differential counterparts. A proof-of-concept prototype has been fabricated in 0.35- $\mu \text{m}$ CMOS and occupies an active area of 0.48 mm2. It achieves 9.13 effective number of bits (ENOB) at 3.72 kHz sampling rate and improvement of more than 50 dB in the power supply rejection ratio (PSRR) by employing the ping-pong technique. It reduces the power consumption of a 5- $\text{k}\Omega $ Wheatstone bridge by 99.6% compared to a traditional interface, down to $2.53~\mu \text{w}$ at 1.8 V supply. The functionality of the system has also been demonstrated in an experimental setup in conjunction with an embedded resistive bridge pressure sensor. [ABSTRACT FROM AUTHOR]

Copyright of Electronic Components & Materials is the property of Electronic Components & Materials and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

A low power current reference circuit with an enable-control terminal is presented in this work, which has been developed in 0.5 μm CDMOS technology. The circuit is capable of providing the reference current in a nano-ampere range for the supply voltage from 2 V to 3 V in the temperature range from −30 °C to 85 °C. The simulation and measurement results demonstrated that the reference current achieves the line regulation of 4.67 % /V, the average temperature coefficient of 361.59 ppm / °C when simulations and measurements are carried out for 8 die-samples under the same supply-voltage and temperature variations. The complete designed circuit consumes approximately 765.1 nA current to generate about 90 nA reference current at 3 V power supply while occupying an area of 0.0217 m m 2 . [ABSTRACT FROM AUTHOR]

A high power supply rejection ratio (PSRR) bandgap voltage reference (BGR) with low temperature coefficient (TC) is proposed. The PSRR is enhanced by an improved voltage-self-regulation (VSR) technology which provides a low-impedance branch and negative feedback loop. Furthermore, a curvature compensation structure is proposed to reduce the TC by utilizing the curvature-corrected current (I C U). The proposed BGR supply voltage range is 2.5–3.6 V and its output voltage is 1.2 V. The results of the simulation using a standard 65 nm CMOS process with 3.3 V thick oxide device demonstrate that the line regulation of the proposed BGR is approximately 0.015 mV/V in the supply voltage range of 3–3.6 V. A TC of 1.86 ppm/ ∘ C is obtained in the temperature range of -40 ∘ C to 125 ∘ C , and PSRR of -104 dB@DC are achieved. The active area of the proposed BGR is 0.063 mm 2. [ABSTRACT FROM AUTHOR]

Abstract—: A formalized technique for the automated design of bandgap voltage reference (BVR) is proposed. The distinctive feature of the technique is the automation of the synthesis of the circuit engineering conceptions by the given parameters of the source, which considerably reduces the design time. Based on the developed technique by the 180-nm SOI technology, the circuit of the voltage reference source was designed. The obtained schematic solution has the following desired characteristics: the power supply suppression ratio at the frequencies of 1 kHz in the worst case is -60 dB and at the frequencies of 1 MHz is -44 dB, the maximum consumption current is 25 μA, the temperature coefficient is 24 ppm/°C in the temperature range from -70 to 150°C, and the ratio of changing the output voltage to changing the supply voltage is 354 μV/V in the range of supply voltage from 2.4 to 7 V. [ABSTRACT FROM AUTHOR]

A novel 79-nW CMOS-only subthreshold voltage reference with 328-mV output voltage, which works down to 0.8-V supply voltage, is presented in this brief. In order to reduce the area and power consumption, the proposed circuit avoids the use of resistors and bipolar transistors. A current subtracting technique is proposed to realize the temperature compensation of reference current. Instead of the op-amp in traditional circuits, some cascode current mirrors are used to enhance the power supply rejection ratio (PSRR). A novel structure consisting of a 1.8-V MOS transistor and a 3.3-V MOS transistor is utilized to accomplish the voltage temperature compensation and to further reduce the power consumption of VREF generator. The proposed voltage reference was fabricated in 0.18- ${\mu }\text{m}$ CMOS process. The measured results show that the temperature coefficient of the output voltage is 33.8 ppm/°C in the range from 10 °C to 100 °C, the PSRR is −55 dB @ 100 Hz at 1.2-V power supply, and the line regulation is 0.21%/V in a supply voltage range of 0.8 to 3.4 V. What is more, the power dissipation is 79 nW, and the chip area is 0.01 mm2. It is suitable for low-power applications. [ABSTRACT FROM AUTHOR]

Copyright of Electronic Components & Materials is the property of Electronic Components & Materials and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)