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The effects of quantum mechanics dominate nanoscale devices, where Moore's law no longer holds true. Additionally, with the recent rapid development of quantum computers, the development of reversible gates to overcome the problems of energy and information loss and the nano-level quantum-dot cellular automata (QCA) technology to efficiently implement them are in the spotlight. In this study, a full adder-subtractor, a core operation of the arithmetic and logic unit (ALU), the most important hardware device in computer operations, is implemented as a circuit capable of reversible operation using QCA-based reversible gates. The proposed circuit consists of one reversible QCA gate and two Feynman gates and is designed as a multi-layer structure for efficient use of area and minimization of delay. The proposed circuit is tested on QCADesigner 2.0.3 and QCADesigner-E 2.2 and shows the best performance and lowest energy dissipation. In particular, it shows tremendous improvement rates of 180% and 562% in two representative standard design cost indicators compared to the best existing studies, and also shows the highest circuit average output polarization. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata (QCA) is an emerging technology with high integration density, low power consumption, and high operating speed. This study introduces a QCA-based modified content addressable memory (CAM) cell employing a five-input minority gate. The functionality, temperature sensitivity, and heat distribution of this modified CAM cell are comprehensively analyzed using QCADesigner E and QCA Pro simulation tools. The results reveal significant advancements over existing designs, with a remarkable 8.33% reduction in area and a substantial 63.7% decrease in energy consumption. Additionally, this modified CAM cell exhibits a notable 5% enhancement in temperature tolerance. These findings emphasize the QCA-based modified CAM cell is more efficient and thermally robust. [ABSTRACT FROM AUTHOR]

Reversible computation is very important to minimize energy dissipation and prevent information loss not only in quantum computing but also in digital computing. Therefore, interest in designing efficient universal logic gates has recently increased. In this study, we efficiently design the Fredkin gate (FRG), a well-known conservative reversible operation gate, using quantum-dot cellular automata (QCA), and propose a D-latch using it. The proposed FRG structure can be designed efficiently using the structure of a QCA multiplexer using cell interaction, and a symmetric structure was designed. The proposed structure was simulated using QCADesigner 2.0.3 and QCADesigner-E for accurate comparison of various performance metrics, and the proposed structure clearly shows superiority in most performances and two representative design costs. Therefore, the lightweight design of an efficient reversible gate prevents data loss and increases information reliability. [ABSTRACT FROM AUTHOR]

In image processing, the noticeable variations of the image can be found using the edge detection process. This edge detection process facilitates to identify placement and edges of an object. The Sobel edge detection process is preferred since it is simple and more noise immune. Sobel edge detection calculates gradients of a pixel in horizontal and vertical directions concerning neighboring pixels. The gradients absolute quantities are computed, added, and matched to a threshold for finding whether the pixel is an edge pixel or not. In this paper, the Sobel edge detection system VLSI architecture is designed which consumes less power by using the arithmetic blocks like Brent Kung adders. The source image of different resolutions is taken to perform Sobel edge detection and implemented using various FPGA devices by analyzing power dissipation, delay and device utilization summary. Then, simulation, synthesis processes are performed and finally, power analysis is performed using XPower Analyzer of Xilinx ISE software. [ABSTRACT FROM AUTHOR]

To investigate the system pressure drop distribution when conveying particle using different curvature radius pipes for the pneumatic conveying system, this paper measured the particle velocity distribution, particle-particle collision characteristics, collision energy loss, minimum pressure drop gas velocity, system pressure drop distribution, and power dissipation for R/D = 3.75, R/D = 5, and R/D = 6.25 pipes. Subsequently, the artificial neural network technique is used to predict the pressure drop of the pneumatic conveying system. It is found that the pressure drop of the system is lower when using the pipe with R/D = 6.25 for conveying particles. Compared to the pipe with R/D = 3.75, the reduction in power dissipation is 3.18 and 5.27% for conveying pellets when using R/D = 5 and R/D = 6.25 pipes, respectively. In addition, the energy loss of the system can be effectively reduced when using the pipe with R/D = 6.25 for conveying particles, which is more beneficial for the particles move in the pipe. The pressure drop model built with artificial neural network can predict the pressure drop value of the system more accurately within ±1.5%. [ABSTRACT FROM AUTHOR]

In coherent optics transmission systems, the digital signal processor (DSP) application-specific integrated circuit (ASIC) is the most power-hungry part of the optical transceiver. Already in the edge of transistor technology, to achieve the power budget, we must look for opportunities to further optimize the designs. This letter explores a dynamic duty cycle for reducing the consumption in the pipeline of such DSP ASICs. We exploit the characteristics of estimator algorithms to introduce a dynamic duty cycle, reducing the mean consumption of designs originally constrained only for worst-case scenarios. We present the methodology to implement duty cycle control using the carrier frequency offset estimator (CFE) algorithm as case study, achieving in simulation level from 22% to 74% power consumption reduction in this algorithm, varying on-chip operation conditions. [ABSTRACT FROM AUTHOR]

This work investigates performance improvement the of ring voltage-controlled oscillator. Particle swarm optimization (PSO) techniques are used on both the physical and schematic levels to optimize the design parameter values (width of the NMOS " W n " and PMOS " W p "). By utilizing this strategy, multiple time-taking iterations can be reduced and done in a single cycle, thereby increasing the likelihood that the ring VCO will function to the best of its ability. After getting the optimized values for the design parameters of the ring VCO's, the circuit has been designed for the performance analysis. The same is demonstrated by evaluating the performance of the circuit and confirming the results of the transient analysis and noise analysis carried out with Cadence tools under a variety of different operating conditions using the 45 nm technology process. The analysis has been carried out in a variety of PVT corners (fast–fast, slow–slow, fast–slow, and slow–fast). [ABSTRACT FROM AUTHOR]

The use of rechargeable batteries for electrical energy storage requires a voltage balancing system. The voltage balancing system requires monitoring in the use of rechargeable batteries so that they can be utilized properly and can improve the electrical energy storage system. In this research, a monitored lead acid battery voltage balancing system was designed so that the management of the battery voltage balance level and the storage of electrical energy in rechargeable batteries can be stored and used optimally. In this research a series of lead acid battery voltage detection and power dissipation circuits were designed. The power dissipation circuit uses the controlled shunt resistor method which is used when the voltage of the lead acid battery being charged exceeds the maximum voltage. This method is easy to implement and can display the value of the lead acid battery voltage and other parameters, so that it can be monitored by the user. The results obtained show that the average voltage error for batteries 1 and 2 is 0.09% and 0.3% respectively. The power dissipation circuit can dissipate lead acid battery power above the reference voltage VREF=±7 V, with a balanced voltage of 6.8 V at 140 minutes and 160 minutes. [ABSTRACT FROM AUTHOR]

In recent years, reversible logic gates have garnered significant interest because of their potential to decrease energy consumption and meet the growing need for low-power computing systems. Unlike conventional logic gates, reversible logic gates ensure that no information loss happens during computation, allowing for the reversal of the entire computation process. This unique characteristic opens up new avenues for developing energy-efficient digital circuits. This review paper serves as a vital contribution to the field by addressing a noticeable gap in the existing literature regarding reversible logic gates. The study not only comprehensively analyzes the array of reversible logic gates available but also underscores their practical applications and significance. It encompasses a wide variety of reversible logic gates, including Toffoli gates, Fredkin gates, and newer innovations. It is found that Toffoli gates outperformed in terms of gate count and quantum cost reduction, making them a preferred choice for quantum circuit optimization. Additionally, Fredkin gates showed exceptional performance in specific applications, like data swapping and quantum state control. The digital circuits like adders, multiplexers, ALU etc. are successfully designed using reversible gates like HNG, DKG etc. The significant gap this study fills lies in the need for a consolidated and in-depth analysis of the state-of-the-art reversible logic gates and their real-world utility. While prior research has discussed these gates individually, this paper takes a novel approach by offering a holistic assessment of their performance, quantum cost, gate count, and practical applications, thereby presenting a comprehensive resource for researchers, engineers, and designers in the field. This innovative contribution plays a pivotal role in shaping the progress of energy-efficient and quantum computing systems as well as in optimizing VLSI chip designs for various applications, with a particular emphasis on enhancing cryptographic and data processing capabilities. The findings of this review aim to stimulate further research and development in reversible computing, contributing to the advancement of energy-efficient and information-preserving computing systems. [ABSTRACT FROM AUTHOR]

The effects of quantum mechanics dominate nanoscale devices, where Moore’s law no longer holds true. Additionally, with the recent rapid development of quantum computers, the development of reversible gates to overcome the problems of energy and information loss and the nano-level quantum-dot cellular automata (QCA) technology to efficiently implement them are in the spotlight. In this study, a full adder-subtractor, a core operation of the arithmetic and logic unit (ALU), the most important hardware device in computer operations, is implemented as a circuit capable of reversible operation using QCA-based reversible gates. The proposed circuit consists of one reversible QCA gate and two Feynman gates and is designed as a multi-layer structure for efficient use of area and minimization of delay. The proposed circuit is tested on QCADesigner 2.0.3 and QCADesigner-E 2.2 and shows the best performance and lowest energy dissipation. In particular, it shows tremendous improvement rates of 180% and 562% in two representative standard design cost indicators compared to the best existing studies, and also shows the highest circuit average output polarization.

This paper presents the design and analysis of high-performance N-bit digital comparators for use in modern digital systems. Digital comparators are fundamental building blocks in many electronic systems, performing the critical task of comparing two digital values and generating an output indicating their relative magnitudes. For implementing N-bit digital comparator a new design for an 8T EX-OR-NOR cell with full rail-to-rail output swing has been proposed. The proposed EX-OR-NOR cell is based on the hybrid circuit utilizing CMOS inverter and transmission gate logics, which thereby uses less power and minimizes propagation delay. Thus, a high-speed N-bit digital comparator design is accomplished using the proposed 8T EX-OR-NOR cell. In the present work 4-bit to 32-bit digital comparators are designed and implemented using the proposed circuitry. All the circuits are designed using Cadence electronic design automation (EDA) Virtuoso Design Environment for 180nm CMOS technology node. The outcomes are evaluated and verified with the comparator designs reported in the literature. The proposed modified N-bit digital comparators provide an excellent combination of speed, power consumption, and accuracy, making them a promising solution for modern digital electronics systems. [ABSTRACT FROM AUTHOR]

Nano-communication networks have critical roles in future worldwide communications, which provide efficient data transmission at ultra-high speeds employing nano-circuits that operate with ultra-low power. The quantum cellular automata (QCA) paradigm enables designing molecular-scale devices operating at terahertz frequencies with negligible power consumption. Moreover, reversible logic aids in reducing thermodynamic power dissipation significantly. In this paper, we design and implement a single-layer Fredkin gate and use it to implement reversible QCA devices, including the crossbar switch, multiplexer, demultiplexer, transmitter, and receiver. These devices are then used to implement a reversible switched network in QCA technology. The proposed circuits employ standard 90-degree QCA cells and coplanar crossovers. The results show that the area-time complexity and power dissipation of the designed reversible switched network have been reduced significantly compared to previous designs.

Power consumption plays a significant role in any integrated circuit. In this study, an explicit type pulse trigger flip-flop is implemented using the CMOS 90 nm technology. For low-power dissipation, 1 V supply will optimize the size of gate terminal. This explicit type flip-flop uses an explicit source for pulse generation, that is, the double edge-triggered pulse generator, which requires half of clock frequency compared to the single edge-triggered pulse generator. The proposed new double edge-triggered pulse generator uses the pulse generation logic, which is used to share many numbers of flip-flop results at low power. In this article, circuits with low power, low heat generation, and increased durability are achieved. [ABSTRACT FROM AUTHOR]

This article describes designing a low‐power novel circuit for overflow detection in two's complement arithmetic operations. The quantum‐dot cellular automata (QCA) is employed to achieve the nanoscale design. For designing the circuit of the proposed arithmetic overflow detector, a new layout of the QCA full adder is utilized. Two different designs of arithmetic overflow detectors are outlined in this article. The designs are compared based on latency, cell count, and device area. Based on the comparison, the best design for an arithmetic overflow detector is presented. The circuit cost for all the designs is also shown in this work. Besides, thermal power's effect on the output cell's polarization has also been investigated. The power dissipation of all proposed QCA layouts is estimated. [ABSTRACT FROM AUTHOR]

Purpose: This study aims to gain an in-depth understanding of the effect of the inherent dry friction of inerter devices on the performance of non-linear frictional inerter-based vibration isolation system (NFI-VIS). Methods: The power flow analysis method is used to investigate quantitatively the internal vibration transmission and energy dissipation. The harmonic balance (HB) method with alternating frequency–time (AFT) scheme is used to obtain the steady-state dynamic responses, with verification by numerical integration results. Results: The results show that the use of the non-linear inerter in the system can reduce the force and vibration power flow transmission over a wide frequency band. The inherent friction of the inerter can benefit vibration isolation when the excitation amplitude is large enough to overcome the inerter friction. Conclusion: This research reveals complex non-linear dynamic phenomena of the system emerging from the frictional inerter and shows that the inherent dry friction of the inerter should be considered in future isolator design. [ABSTRACT FROM AUTHOR]

Abstract Except for qubits for which the different possible values are unordered, the different values of m-valued circuits either with voltage levels, current levels or charge levels are totally ordered. Either at the Math level (Post algebras) or at the circuit level, it means that each multiple valued level must be decomposed into binary levels, processed with binary computation and finally converted into a multiple valued level. Using ternary adders as example, we show that the ternary-to-binary decoding and binary encoding should be applied to the whole adder or to restricted parts of the adder. The second approach using multiplexers leads to the most efficient ternary adders. However, a comparison with binary adders shows that the ternary-to-binary and binary-to-ternary conversions is the reason for which the binary adders are more efficient.

Abstract The modern-day computing technologies are continuously undergoing a rapid changing landscape; thus, the demands of new memory types are growing that will be fast, energy efficient and durable. The limited scaling capabilities of the conventional memory technologies are pushing the limits of data-intense applications beyond the scope of silicon-based complementary metal oxide semiconductors (CMOS). Resistive random access memory (RRAM) is one of the most suitable emerging memory technologies candidates that have demonstrated potential to replace state-of-the-art integrated electronic devices for advanced computing and digital and analog circuit applications including neuromorphic networks. RRAM has grown in prominence in the recent years due to its simple structure, long retention, high operating speed, ultra-low-power operation capabilities, ability to scale to lower dimensions without affecting the device performance and the possibility of three-dimensional integration for high-density applications. Over the past few years, research has shown RRAM as one of the most suitable candidates for designing efficient, intelligent and secure computing system in the post-CMOS era. In this manuscript, the journey and the device engineering of RRAM with a special focus on the resistive switching mechanism are detailed. This review also focuses on the RRAM based on two-dimensional (2D) materials, as 2D materials offer unique electrical, chemical, mechanical and physical properties owing to their ultrathin, flexible and multilayer structure. Finally, the applications of RRAM in the field of neuromorphic computing are presented.

Summary: With the end of Dennard's scale, processor designers have been looking for new technical alternatives so that approximate computing (AC) has managed to attract the attention of researchers by offering techniques ranging from the application level to the circuit level. When applying approximate circuits into hardware design, the program user may speed up the application. At the same time, a designer may save area and power dissipation at the cost of less accuracy on the results of operations. This article discusses the compromise between controlled accuracy versus physical efficiency by evaluating a set of arithmetic circuits designs. The article also presents new mixed organization approximate designs. To evaluate the approximate design benefits, we performed a comprehensive set of experiments from tailor‐made approximate arithmetic circuits on field‐programmable gate array and application specific integrated circuits technologies. Our results reveal that our proposed mixed approximate designs have promising results on error rates, area usage, and power dissipation compared to the related work. Another interesting result is that one should care about the prototyping platform where the approximate hardware will be synthesized. Tailor‐made approximate cells may take advantage on intrinsic design details than standard cells or even general prototyping platforms. [ABSTRACT FROM AUTHOR]

Quantum-dot Cellular Automata (QCA) is a piece of optimistic machinery that provides an advanced design for resolving all arithmetic schemes at appreciable nanotechnology. In this paper, based on cell interaction, a novel based three-input XOR gate is designed. For general-purpose task by fixing one of its inputs to two-input XOR gates to achieve. With the help of a 3-input XOR gate, a compact full adder is designed. Besides, we concentrated on creating a Novel for an 8-bit controllable inverter using QCA. All functionalism and performance of the methods can be visualized using the QCA Designer tool. In addition to this, diversified power dissipation characteristics are observed from the QCA Designer tool simulator. [ABSTRACT FROM AUTHOR]

In this paper,we consider solving the topology optimization for steady-state incompressibleNavier-Stokes problems via a new topology optimization method called parameterized level set method, which can maintain a relatively smooth level set function with a local optimality condition. The objective of topology optimization is to [ABSTRACT FROM AUTHOR]

Low power demand of electronics industry and communication systems are driven by technology scaling and marketing. Compressors are the most often used modules in the architecture of an Arithmetic Circuits. Compressor is the basic combinational digital logic circuit for performing numerous arithmetic operations. The design criterion in any Compressor circuit involves the XOR-XNOR and multiplexer circuits. It is a prominent component in the designing of integrated circuit that performs arithmetic operations. The proposed Compressor is design in order to reduce the transistor count which results in curtailing power dissipation and delay. The performance parameter are recorded and tabulated. This compressor has less delay and low power dissipation. The temperature effect has also shown a linear change in power dissipation in lower temperature ranges which shows the robustness of the proposed circuits. The proposed compressor can be used in numerous applications such as multiplier, DSP microprocessor and data processing systems. [ABSTRACT FROM AUTHOR]

This paper utilizes Taguchi design of experiments and Pareto analysis of variance statistical approaches to demonstrate circuit optimization. The phase-frequency detector (PFD) circuit based on dynamic logic has been chosen for optimization. For various MOSFETs of PFD, three levels and three factors of power supply and width of PMOS and NMOS ( V DD , w p , and w n ) are considered to be critical performance governing factors. The Taguchi technique determines the level of significance of a factor that influences a given performance parameter. The crucial factor for a given response is determined via ANOVA analysis. The optimum values for the parameters V DD , w p , and w n are likewise determined using this procedure to maximize the circuit's overall performance. Taguchi DoE and Pareto Anova analyses have been performed using the Minitab software. Simulating the circuit with GPDK 180 nm CMOS technology using these methods ensures that the acquired parameters are correct for best performance. The Cadence Virtuoso tool has been used to conduct pre-layout and post-layout simulations. The simulation outcomes are reasonably close to the ANOVA predicted result. Phase noise, power dissipation, and frequency of operation of the proposed PFD are − 1 5 9. 5 6 dBc/Hz, 9.83 μ W, and 10.21 GHz, respectively, and it occupies a chip area of 300.41 μ m 2 . The proposed PFD is used to implement a charge-pump PLL which performs effectively with a settling time of 2.59 μ s. [ABSTRACT FROM AUTHOR]

This paper proposes a 4-bit FIR filter useful in communication and many application of Digital Signal Processing (DSP) using fully adiabatic technology PAL, which reduces all parametric performance and power consumptions. This research work presents a fully adiabatic low power and high speed efficient FIR Filter design and compared with CMOS FIR filters. The PAL FIR filter is designed using reversible logic and it is simulated and synthesized using CADENCE digital lab for different parameters like transition frequency variations, supply voltage variations and load capacitance variation. This architecture includes the low power dissipation due to adiabatic technology and logarithmic multiplier to reduce the hardware requirements. Synthesis reports show that the proposed PAL FIR filter is capable of reducing approximately 75% power dissipation as compared to CMOS FIR filter at different frequencies, supply voltage and capacitance. [ABSTRACT FROM AUTHOR]

In pressure-controlled ventilation (PCV), a decelerating gas flow pattern occurs during inspiration and expiration. In contrast, flow-controlled ventilation (FCV) guarantees a continuous gas flow throughout the entire ventilation cycle where the inspiration and expiration phases are simply performed by a change of gas flow direction. The aim of this trial was to highlight the effects of different flow patterns on respiratory variables and gas exchange. Anesthetized pigs were ventilated with either FCV or PCV for 1 h and thereafter for 30 min each in a crossover comparison. Both ventilation modes were set with a peak pressure of 15 cmH2O, positive end-expiratory pressure of 5 cmH2O, a respiratory rate of 20/min, and a fraction of inspired oxygen at 0.3. All respiratory variables were collected every 15 min. Tidal volume and respiratory minute volume were significantly lower in FCV (n = 5) compared with PCV (n = 5) animals [4.6 vs. 6.6, MD -2.0 (95% CI -2.6 to -1.4) mL/kg; P < 0.001 and 7.3 vs. 9.5, MD -2.2 (95% CI -3.3 to -1.0) L/min; P = 0.006]. Notwithstanding these differences, CO2-removal as well as oxygenation was not inferior in FCV compared with PCV. Mechanical ventilation with identical ventilator settings resulted in lower tidal volumes and consecutive minute volume in FCV compared with PCV. This finding can be explained physically by the continuous gas flow pattern in FCV that necessitates a lower alveolar pressure amplitude. Interestingly, gas exchange was comparable in both groups, which is suggestive of improved ventilation efficiency at a continuous gas flow pattern. [ABSTRACT FROM AUTHOR]

This paper presents a study on the propagation delay and power dissipation of a 2-bit static random-access memory (SRAM) with two cross-coupled multi-state spatial wave function switching (SWS) CMOS inverters. The proposed SRAM design utilizes the advantages of the CMOS-SWS inverter, such as its small area, low power consumption, and high speed. The 2-bit SRAM circuit simulations were carried out in Cadence to analyze the power dissipation and propagation delay. An Analog Behavioral Model (ABM) and the Berkeley Short-channel IGFET Model (BSIM4.6) in 0.18-μm technology were combined to create this model. The analysis of the propagation delay shows that the multi-state CMOS-SWS SRAM significantly reduces the delay compared to other multi-state 6T SRAM memories. Additionally, the analysis of the power dissipation shows that the multi-state SWS-SRAM is comparable to conventional SRAMs. These results demonstrate the potential of multi-state SWS-SRAM for improving the performance of memory circuits and provide valuable insights for future design optimization. [ABSTRACT FROM AUTHOR]

This work aims to improve the total power dissipation, leakage currents and stability without disturbing the logic state of SRAM cell with concept called sub-threshold operation. Though, sub-threshold SRAM proves to be advantageous but fails with basic 6T SRAM cell during readability and writability. In this paper we have investigated a non-volatile 6T2M (6 Transistors & 2 Memristors) sub-threshold SRAM cell working at lower supply voltage of VDD=0.3V, where Memristor is used to store the information even at power failures and restores previous data with successful read and write operation overcomes the challenge faced. This paper also proposes a new configuration of non-volatile 6T2M (6 Transistors & 2 Memristors) subthreshold SRAM cell resulting in improved behaviour in terms of power, stability and leakage current where read and write power has improved by 40% and 90% respectively when compared to 6T2M (conventional) SRAM cell. The proposed 6T2M SRAM cell offers good stability of RSNM=65mV and WSNM=93mV which is much improved at low voltage when compared to conventional basic 6T SRAM cell, and improved leakage current of 4.92nA is achieved as compared.