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A set of unique features, including large-area solution processing on flexible and stretchable substrates, make polymer semiconductors a promising material choice for a range of state-of-the-art applications in electronics, optoelectronics and sensing. Yet, an inherent weakness of polymer semiconductors remains their low dielectric constants, increasing their susceptibility toward unscreened dipoles. These dipoles are particularly prevalent at polymer-dielectric interfaces with high- k dielectrics, which are essential for the operation of devices such as low-voltage field-effect transistors. This shortcoming can be addressed by using self-assembled monolayers (SAMs) to passivate surfaces that impact charge transport. However, SAM-treatment also increases the hydrophobicity of surfaces and therefore poses a challenge for subsequent solution processing steps and complex packaging of devices. Here, we report low-voltage polymer transistors processed by spin coating of the polymer semiconductors on highly hydrophobic SAM-treated aluminum and hafnium oxide dielectrics (contact angles >100) through fine-tuning of the interfacial tension at the polymer-dielectric interface. This approach enables the processing and detailed characterization of near-amorphous (indacenodithiophene- co benzothiadiazole) as well as semicrystalline ( poly(2,5-bis(2-octyldodecyl)-3,6-di(thiophen-2-yl)diketopyrrolo[3,4-c]pyrrole-1,4-dione-alt-thieno[3,2-b]thiophen )) polymer semiconductors. We demonstrate polymer transistors that exhibit high on-currents and field-independent, charge carrier mobilities of 0.8 cm ^2 V ^−1 s ^−1 at low operating voltages (

Organic field-effect transistors (OFETs) were fabricated using three high-surface area and flexible expanded-poly(tetrafluoroethylene) (ePTFE) membranes in gate dielectrics, along with the semiconducting polymer poly[2,5-bis(2-octyldodecyl)pyrrolo[3,4- c ]pyrrole-1,4(2 H ,5 H )-dione-3,6-diyl)- alt -(2,2':5',2″:5″,2‴-quaterthiophen-5,5‴-diyl)] (PDPP4T). The transistor behavior of these devices was investigated following annealing at 50, 100, 150, and 200 °C, all sustained for 1 h. For annealing temperatures above 50 °C, the OFETs displayed improved transistor behavior and a significant increase in output current while maintaining similar magnitudes of V th shifts when subjected to static voltage compared to those kept at ambient temperature. We also tested the response to NO 2 gas for further characterization and for possible applications. The ePTFE-PDPP4T interface of each membrane was characterized via scanning electron microscopy for all four annealing temperatures to derive a model for the hole mobility of the ePTFE-PDPP4T OFETs that accounts for the microporous structure of the ePTFE and consequently adjusts the channel width of the OFET. Using this model, a maximum hole mobility of 1.8 ± 1.0 cm 2 /V s was calculated for the polymer in an ePTFE-PDPP4T OFET annealed at 200 °C, whereas a PDPP4T OFET using only the native silicon wafer oxide as a gate dielectric exhibited a hole mobility of just 0.09 ± 0.03 cm 2 /V s at the same annealing condition. This work demonstrates that responsive semiconducting polymer films can be deposited on nominally nonwetting and extremely bendable membranes, and the charge carrier mobility can be significantly increased compared to their as-prepared state by using thermally durable polymer membranes with unique microstructures as gate dielectrics.

In this paper, the carrier mobility analytical model in a POFET (Polymer Field Effect Transistor) channel is proposed. The model was developed on the basis of existing models and experimental results. The proposed model is universal because it encompasses the carrier mobility dependence on temperature, electric field and trap density in the POFET channel. The model is comparatively simple, easy for application and gives valuable results. According to the presented model, simulations of mobility as a function of the parameters of interest were performed. The obtained results are shown graphically. In comparison to accessible experimental results excellent correspondence was found. This model enables the calculation of simple POFET current-voltage I (V) characteristics.

Abstract: In this work, we proposed a fast and controllable blade coating process to form non-close-packed nanosphere structures. We investigated the key to obtain well-distributed non-close-packed PS spheres with blade coating. We utilized the blade-coated nanosphere structure to realize colloidal lithography and fabricate a vertical channel polymer transistor, the space-charge-limited transistor (SCLT). We demonstrated that SCLT utilizing blade-coated nanospheres delivered 13.9mA/cm2 at 1.8V with an on/off current ratio as 45,000. The process of blade-coating nanospheres may facilitate the commercialization of low-cost colloidal lithography. [Copyright &y& Elsevier]

Abstract: P3HT thin film transistors (TFT) have been fabricated using inkjet printing technique. The present work aims at the systematic study of the impact of distributed contact resistance including field dependent mobility. The coupled analysis is not yet explored for polymer organic thin film transistors. Numerical simulations are performed to study the coupled influence of field mobility and distributed contact resistance on the FET device behavior. Considering the influence of field mobility and distributed contact resistance, simulated results are consistent with our experimental results. [Copyright &y& Elsevier]