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To solve the problems of overshoot, chattering, and slow response in the traditional sensorless control scheme based on sliding mode observer with PI controller, a novel dual-sliding mode sensorless vector control (NDSMSVC) strategy for permanent magnet synchronous motorized spindle (PMSMS) is proposed. Based on the PMSMS mathematical model, the terminal sliding mode controller and sliding mode observer models are successively established. To solve the singularity problem, the NTSM surface function is redefined. In designing the speed controller, the reaching law is incorporated, and the sigmoid (s) function is used to improve the discontinuities in control. ISMO integrated a phase-locked loop that extracts the rotor position and speed, which enhances the observation accuracy. The validation was carried out in the laboratory using a high-speed electric spindle (FL170-20-15). The experiments show that the proposed strategy is able to achieve the desired results and accurately track the rotor position and speed compared to the existing schemes. [ABSTRACT FROM AUTHOR]

The high penetration of renewable energy sources (RESs) and power electronics devices has led to a continuous decline in power system stability. Due to the instability of grid-following converters (GFLCs) in weak grids, the grid-forming converters (GFMCs) have gained widespread attention featuring their flexible frequency and voltage regulation capabilities, as well as the satisfactory grid-supporting services, such as inertia and damping, et al. Notably, the risk of wideband oscillations in modern power grids is increasingly exacerbated by the reduced number of synchronous generators (SGs). Thus, the wideband oscillation suppression method based on adaptive active power droop control of GFMCs is presented in this paper. First, the stability of the hybrid grid-forming and grid-following system is obtained according to the improved short circuit ratio (ISCR), where the GFMC is in parallel at the point of common coupling (PCC) of the GFLC. Then, an adaptive adjustment strategy of the active power droop control is proposed to enhance the oscillation suppression capability across the full frequency range, thereby mitigating the wideband oscillation caused by phase-locked loop (PLL) synchronization in the GFLCs. Additionally, a first-order inertia control unit is added to the active and reactive power droop controllers to mitigate frequency and voltage variations as well as suppress potential mid-to-high frequency resonance. Finally, the wideband oscillation suppression strategy is validated by the simulation and experimental results. [ABSTRACT FROM AUTHOR]

Robust control mechanisms are needed in microgrids to ensure voltage source inverters (VSIs) effectively integrate renewable energy sources such as solar photovoltaic (PV) systems into the power network. Current control approaches often have limitations regarding velocity, stability, and robustness. The paper details a newly developed method named Point of Common Coupling Direct Power Control (PCC-DPC) for renewable energy systems connected to the grid. PCC-DPC is used to instantly control voltage at the point of common coupling (PCC) inside the microgrid as opposed to other conventional techniques. This leads to a simplified controller design that does not require complex Park transformations and phase-locked loop (PLL) systems, and has a lower computational burden and less power fluctuation in a stable manner. Moreover, this research critically examines power quality phenomena through comparing PCC-DPC with a Vector Current Controller (VCC). Simulations performed on an Opal Re-al-Time simulator showed improved tracking performance and overall system efficiency due to the PCC-DPC approach over others. These results demonstrate that it can effectively be used as one of the most suitable methods for integrating renewable energy into electricity grids, which is reliable in regards to changes in power grid dynamics. [ABSTRACT FROM AUTHOR]

In the realm of analog integrated circuit (IC) design, due to the intricate nonlinear relationships between circuit performance metrics and design variables, as well as the complex interdependencies and trade‐offs between various performance criteria, it is difficult to determine the appropriate geometric width and length of the circuit components to meet all performance specifications. This difficulty makes the task of designing analog IC challenging. To address the challenge of analog IC design, this paper introduces a machine learning methodology—specifically employing the genetic algorithm (GA)—to automate the selection of circuit components' geometrical parameters, aiding the work of analog circuit designers in determining the appropriate dimensions for transistors within the charge‐pump circuit. The GA, implemented in Python and integrated with a script program written in the OCEAN language, synergistically collaborates in the GA‐OCEAN framework. The result, which ensures compliance with all specifications with remarkably low error margins, ranging as low as 0.03% and as high as 1.24%, highlights the proposed GA‐OCEAN framework's remarkable capacity to determine optimal dimensions for components inside the charge‐pump circuit. © 2024 Institute of Electrical Engineers of Japan and Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]

This paper presents a newly proposed high-order cascaded phase-locked loop using a type-I phase-locked loop in the second stage. The type-I phase-locked loop includes a gate-diffusion-input-based phase detector and pulse width amplifier that leads to breaking the trade-off between reference spur and locking time. Moreover, a type-I phase-locked loop deploys a pulse width amplifier after a gate-diffusion-input-based phase detector with variable gain to amplify the phase error between the reference clock and the output of the voltage-controlled oscillator. The proposed architecture has been implemented in a 180-nm semiconductor laboratory CMOS technology. The proposed fifth-order cascaded phase-locked loop achieves the reference spur of −77 dBc, while the conventional first-stage charge-pump-based phase-locked loop achieves −59.7 dBc. It measures the 1.2 $\mu $ μ s settling time, whereas conventional first stage charge-pump-based phase-locked loop measures 2.4 $\mu $ μ s settling time. The cascaded phase-locked loop operates at 2.4 GHz output frequency, and the simulated phase noise at 1 MHz offset frequency is −105.4 dBc/Hz. It consumes 5.8 mW from a 1.8 V power supply. [ABSTRACT FROM AUTHOR]

Summary Generating a quadrature signal in a single‐phase system using a second‐order generalized integrator (SOGI) requires accurate frequency information. The standard SOGI phase‐locked loop (PLL) includes frequency feedback to the SOGI. However, during grid abnormalities such as voltage sag/swell and phase angle jumps, the SOGI‐PLL faces frequency disturbances that propagate to the phase detector (PD) and affects the quadrature signal generator (QSG). Furthermore, the SOGI‐PLL having two loops dependent on each other creates loop coupling phenomena; either a change in phase or frequency affects each other. SOGI‐PLL is tuning sensitive, as the SOGI block has a gain that needs to be adjusted, increases the complexity, and affects the performance of the system. There is a trade‐off between SOGI gain and PLL parameters that needs to be considered for adequate parameter design to provide accurate grid synchronization while maintaining the stability of the system. To attain better performance, researchers have proposed derivative‐based PLL (DPLL). The conventional DPLL faces challenges to noise and harmonics amplification. This paper presents an improved DPLL for single‐phase grid synchronization under adverse grid conditions. The improved derivative‐based PLL (IDPLL) comprises two improved derivative‐based quadrature signal generator (IDQSG) blocks to extract the phase‐error information for accurately estimating phase and frequency. The detailed mathematical modeling and bode plot for the IDQSG and IDPLL are presented. The proposed IDQSG eliminates the requirement of gain tuning, hence reducing complexity. Moreover, there is no interdependent loop in the IDPLL, which significantly improves the dynamic performance. A hardware setup is developed to evaluate the performance of the system in real‐time. The experimental results are obtained using an field programmable gate array (FPGA)‐based controller. [ABSTRACT FROM AUTHOR]

D-estimation method (DEM) is a single-phase synchronization system, which includes a prefilter, a postfilter, an estimate producer, and a frequency feedback (FFB) loop for adapting the prefilter and postfilter to frequency changes. The DEM has a completely different structure compared to phase-locked loops (PLLs), which makes its analysis, tuning, and linear modeling rather challenging, at least for those who are not very experienced in this area. This study aims to bridge this research gap. It is demonstrated in this study that the DEM, in its simplest possible form, is mathematically equivalent to the second-order generalized integrator-based PLL (SOGI-PLL) if a certain condition holds. This equivalence, which is verified numerically and experimentally, makes the linear modeling, analysis, and tuning of the DEM quite straightforward. [ABSTRACT FROM AUTHOR]

The traditional ip-iq harmonic detection method is widely used in APF, but it sacrifices the response speed and detection accuracy of the APF system due to the limitations of the traditional phase-locked loop and LPF. Therefore, in order to make APF both higher detection accuracy and faster response speed, a harmonic detection method based on dual second-order sliding-window discrete Fourier transform (DS-SDFT) is proposed, which can accurately detect harmonics with DSOGI-PLL and greatly reduce the computational effort by using half-cycle sliding-window iterative discrete Fourier transform, solving the inherent defects of traditional phase-locked loops and LPFs. Meanwhile, in order to compensate the harmonics better, the model predictive control with stronger dynamic response capability is used in the current compensation control. Finally, the APF based on this harmonic detection method and current control strategy is fast in response and high in detection accuracy, which is proved by the simulation and experimental results, and the effectiveness of the detection method is verified. [ABSTRACT FROM AUTHOR]

In this paper, to analyze the tuning range (TR) of transistors, we introduced two streamlined modeling approaches that can precisely predict the extent and direction of the TR. The first approach, known as the average DC (Id) method, employed a simplified circuit model to dissect transistor characteristics, enabling us to understand the general trajectory of the TR. The second approach involved the transient current Id (tc) method, which offers a nuanced portrayal of the transistor's real‐world performance. By analyzing the current fluctuations within the transistor during transient states, its tuning capabilities could be more accurately ascertained. Further, this paper presents several designs for ultra‐wide‐tuning‐range complementary metal–oxide–semiconductor (CMOS) voltage‐controlled oscillators (VCOs) that employ a novel two‐mode current‐starved delay cell, featuring a tunable transistor‐based current source for coarse frequency adjustment operating in synergy with a varactor for precise tuning. Using the 65‐nm CMOS process, three prototype VCOs (Designs 2/3/4) based on the new cell and targeting different numbers of phases and performance were fabricated, thoroughly characterized, and compared with their traditional inverter‐based counterpart (Design 1). Design 1 featured an inverter‐based four‐phase structure, with an output frequency range of 3.14–9.82 GHz, i.e., a radio frequency (RF) TR of 103%, with phase noise (PN) ranging from 137.7 to 132.1 dBc/Hz at an offset of 100 MHz, figure of merit with tuning range and area (FoMTA) varying from 200.7 to 205.1 dBc/Hz, and area of 0.0036 mm2. In contrast, Designs 2/3/4, based on the new delay cell, featured 8/3/4 phases, with output frequencies in the ranges of 1.14–9.17, 1.26–16.53, and 1.15–18.32 GHz, respectively, resulting in increased RF TRs of 155.8%, 171.7% and 176.4%, as well as PN at an offset of 100 MHz in the ranges of 142.1–138, 130.5–131.3, and 131.9–129.6 dBc/Hz, respectively. This yielded better FoMTAs in the ranges of 201.2–209.9, 205.3–217.9, and 194.1–209.9 dBc/Hz, thus allowing the VCOs to maintain consistent performance across the frequency band and occupy comparable or smaller silicon areas of 0.00425, 0.000972, and 0.00348 mm2 in the same 65 nm technology. These designs showcase the versatility and efficiency of the two‐mode current‐starved delay architecture, which offers wide TRs, tiny areas, and competitive performance metrics for various applications in RF integrated circuits. [ABSTRACT FROM AUTHOR]

This paper presents a charge pump circuit with a wide output range and low current mismatch applied to phase-locked loops. In this designed structure, T-shaped analog switches are adopted to suppress the non-ideal effects of clock feedthrough, switching time mismatch, and charge injection. A source follower and current splitting circuits are proposed to improve the matching accuracy of the charging and discharging currents and reduce the current mismatch rate. A rail-to-rail high-gain amplifier with a negative feedback connection is introduced to suppress the charge-sharing effect of the charge pump. A cascode current mirror with a high output impedance is used to provide the charge and discharge currents for the charge pump, which not only improves the current accuracy of the charge pump but also increases the output voltage range. The proposed charge pump is designed and simulated based on a 65 nm CMOS process. The results show that when the power supply voltage is 1.2 V, the output current of the charge pump is 100 μA, the output voltage is in the range of 0.2~1 V, and the maximum current mismatch rate and current variation rate are only 0.21% and 1.4%, respectively. [ABSTRACT FROM AUTHOR]

In this paper, an optoelectronic oscillator (OEO) with ultra-low phase noise and high stability based on the injection-locked and phase-locked loop is proposed. In theory, the injection-locked frequency range of the injection signal is studied based on the phase dynamics equation, and the phase noise performance of the injection-locked OEO is analyzed. The role of the phase-locked loop on the frequency stability of the OEO is analyzed based on the phase-locked loop transfer function. In addition, this paper builds an injection-locked OEO based on a phase-locked loop. The injection-locked signal is the high-frequency output of the multiplication crystal oscillator (MCO). At the same time, this MCO synchronously outputs a low-frequency signal, which is used as the reference signal of the phase-locked loop. The experimental results show that the proposed OEO output frequency is 10 GHz, and the phase noise is −89.25 dBc/Hz@100 Hz, −121.71 dBc/Hz@1 kHz, and −145.39 dBc/Hz@10 kHz; the side-mode suppression ratio is 80 dB; the frequency stability is 2.06 × 10 − 11 @1 s, 9.03 × 10 − 11 @10 s, 1.03 × 10 − 10 @100 s, and 3.03 × 10 − 10 @1000 s. Consistent with the theoretical analysis results, the solution takes into account the frequency stability, side-mode suppression ratio, and phase noise performance. The simple structure is more advantageous in practical applications. [ABSTRACT FROM AUTHOR]

The supplementary damping controller (SDC) in the doubly fed induction generator (DFIG) is to suppress the angular oscillations among synchronous generators (SGs). Due to the phase-locking error, the coupling between the SDC and the phase-locked loop (PLL) weakens the suppression effect. This paper proposes a novel triple-branch SDC (TB-SDC) and two-stage optimization to reduce the phase locking error and suppress the angular oscillation. The originalities are, (1) An analytical model to describe the coupling between the SDC and the PLL considering the phase locking error is newly proposed. (2) A triple-branch SDC with an additional input from the PLL is newly proposed to suppress the angular oscillation while reducing the phase-locking error. (3) Based on 2-norm of the trajectory sensitivities, two evaluation indices are newly defined to quantify the impact of the TB-SDC parameters on the oscillation and the phase locking error, and select the critical parameters. (4) A two-stage optimization model is proposed to adjust the parameters of the TB-SDC, where the 1st step is to reduce the phase locking error and decide the input signals of the SDC-P and the SDC-Q, and the 2nd step is to improve the suppression effect and reduce the phase locking error. The simulation results verify the impact of the coupling, and validate the effectiveness and adaptability of the TB-SDC and optimization. © 2017 Elsevier Inc. All rights reserved.

This paper analyzes the factors affecting the stability of phase-locked loops (PLLs) in weak power grids. By establishing a PLL model in weak power grids, it is found that line impedance, grid frequency disturbances, and output power all have an impact on PLL stability. The influence of line impedance, grid frequency disturbances, and output power on PLL is analyzed using the phase plane method. Additionally, it is observed that increasing the PLL damping ratio can enhance PLL stability, but when the damping ratio exceeds the critical damping ratio, PLL instability may occur. Therefore, this paper divides the controllable range of PLL into two cases: damping ratio greater than the critical damping ratio and damping ratio less than the critical damping ratio. For the case where the damping ratio is less than the critical damping ratio, a transient virtual inductance control method is proposed to enhance the PLL damping ratio and improve PLL stability without introducing power coupling. For the case where the damping ratio is greater than the critical damping ratio, PLL adaptive parameter adjustment control is proposed to ensure that the PLL trajectory does not diverge by increasing the PLL adjustment time without increasing the damping ratio, thus improving VSC stability. Finally, a comparison with conventional methods is conducted, and the feasibility and correctness are analyzed through time-domain simulations, followed by presenting the result analysis.

Abstract Aiming at the common problems of frequency variations and harmonics in complex power grids, an improved inverse Park transform phase locked loop (IPT-PLL) technology for single-phase converters suitable for micro grid systems is proposed. Firstly, in the phase detection of PLL, the α component of Park transformation is selected as the reference voltage, and its orthogonal component is constructed using a 1/4 fundamental period delay method. Secondly, Lagrange interpolation polynomials are introduced to approximate fractional delay to solve the problem of delay calculation errors caused by frequency changes. Thirdly, in order to compensate for the poor ability of traditional proportional integral (PI) regulators, multi resonant controllers are superimposed to suppress low order harmonic disturbances. Finally, the design method and system performance of the PI regulator and each resonant controller are analyzed theoretically. The experimental results show that the proposed improved IPT-PLL method has strong adaptability to complex power grids. It can significantly improve the tracking performance of power grid frequency, suppress the interference of low order harmonics and DC bias. And it has good dynamic and static performance.

The synchronous reference frame phase-locked loop (SRF-PLL), also called dqPLL, is an electric circuit commonly used in power electronics to estimate the phase angle of a three-phase AC grid. If the voltage is unbalanced, the PLL is modeled as a periodically forced nonlinear oscillator and is known in practice to converge to a steady oscillation. In the existing literature, the oscillation has been studied via linearization assuming a low level of unbalance. Aiming for stronger nonlocal statements, we present nonlinear analysis. We apply the method of autonomous comparison systems and incremental stability to show that the steady oscillation is unique and attractive in a wider neighborhood. Its lock-in domain is estimated using numerical phase portrait analysis. The oscillation is further approximated up to the terms of the second order in the unbalance factor—it yields an estimation of the time average of the PLL's phase error which is not visible by linearization only. The results provide stability guarantees and can guide the tuning of SRF-PLL. [ABSTRACT FROM AUTHOR]

Aiming at the common problems of frequency variations and harmonics in complex power grids, an improved inverse Park transform phase locked loop (IPT-PLL) technology for single-phase converters suitable for micro grid systems is proposed. Firstly, in the phase detection of PLL, the α component of Park transformation is selected as the reference voltage, and its orthogonal component is constructed using a 1/4 fundamental period delay method. Secondly, Lagrange interpolation polynomials are introduced to approximate fractional delay to solve the problem of delay calculation errors caused by frequency changes. Thirdly, in order to compensate for the poor ability of traditional proportional integral (PI) regulators, multi resonant controllers are superimposed to suppress low order harmonic disturbances. Finally, the design method and system performance of the PI regulator and each resonant controller are analyzed theoretically. The experimental results show that the proposed improved IPT-PLL method has strong adaptability to complex power grids. It can significantly improve the tracking performance of power grid frequency, suppress the interference of low order harmonics and DC bias. And it has good dynamic and static performance. [ABSTRACT FROM AUTHOR]

This study proposes a control method for transferring power generated by a solar photovoltaic system. The control algorithm, called MVF-DSOGI-PLL or Multi-Variable Filter Dual Second-Order Generalized Integrator Phase-Locked Loop), accurately estimates symmetrical components, phase angle, and positive sequence voltages of the Common Point of Interface (CPI) in distorted grid conditions. The approach creates a compensatory current to reduce PQ difficulties by extracting the size of the basic current load undergoing operation employing the SOGI method. These systems can operate in either modes of PV-DSTATCOM or DSTATCOM, depending on solar insolation's availability. The simulation models of the grid-interfaced SPV systems are developed in Matlab/Simulink to evaluate the performances of the suggested control method. The results of simulation demonstrate that the suggested control systems efficiently transfers the power generated by PV arrays to a grid while performing tasks like load balancing, power factor correction (PFC), and harmonics reduction. Furthermore, the MVF-DSOGI-PLL-based control algorithm successfully mitigates PQ issues in distribution networks with weak grids, ensuring that PQ levels remain between a limited set by the IEEE-519 standard. A laboratory prototype of the proposed system is implemented to assess its steady states and dynamic efficient under fluctuating solar insolation, and load imbalance distortions. [ABSTRACT FROM AUTHOR]

The operation of the grid-connected inverter (GCI) in weak grid conditions presents a risk of instability due to the presence of high grid impedance and the negative impedance effect of the phase-locked loop (PLL). In response to this issue, this paper introduces an impedance remodeling control strategy for the GCI utilizing the inertia-damping phase-locked loop (ID-PLL). Firstly, the proposed ID-PLL exhibits certain inertia and damping properties in comparison to the traditional PLL (T-PLL), resulting in an enhanced phase margin of the GCI system's equivalent output impedance. Consequently, the adaptation range of the grid impedance increases from 12mH (SCR = 3.00) to 24mH (SCR = 1.37). Next, from the perspective of impedance analysis, this study remodels the PLL impedance and inverter control loop impedance, further improving the amplitude and phase margin of the system's output impedance. As a result, the adaptation range of the grid impedance extends to 33mH (SCR = 1.00), and the transition of grid-connected currents becomes smooth and free of overshoot. Finally, the effectiveness of the proposed control strategy is validated through theoretical analysis and experimental verification.

Robust control mechanisms are needed in microgrids to ensure voltage source inverters (VSIs) effectively integrate renewable energy sources such as solar photovoltaic (PV) systems into the power network. Current control approaches often have limitations regarding velocity, stability, and robustness. The paper details a newly developed method named Point of Common Coupling Direct Power Control (PCC-DPC) for renewable energy systems connected to the grid. PCC-DPC is used to instantly control voltage at the point of common coupling (PCC) inside the microgrid as opposed to other conventional techniques. This leads to a simplified controller design that does not require complex Park transformations and phase-locked loop (PLL) systems, and has a lower computational burden and less power fluctuation in a stable manner. Moreover, this research critically examines power quality phenomena through comparing PCC-DPC with a Vector Current Controller (VCC). Simulations performed on an Opal Re-al-Time simulator showed improved tracking performance and overall system efficiency due to the PCC-DPC approach over others. These results demonstrate that it can effectively be used as one of the most suitable methods for integrating renewable energy into electricity grids, which is reliable in regards to changes in power grid dynamics.

The high penetration of renewable energy sources (RESs) and power electronics devices has led to a continuous decline in power system stability. Due to the instability of grid-following converters (GFLCs) in weak grids, the grid-forming converters (GFMCs) have gained widespread attention featuring their flexible frequency and voltage regulation capabilities, as well as the satisfactory grid-supporting services, such as inertia and damping, et al. Notably, the risk of wideband oscillations in modern power grids is increasingly exacerbated by the reduced number of synchronous generators (SGs). Thus, the wideband oscillation suppression method based on adaptive active power droop control of GFMCs is presented in this paper. First, the stability of the hybrid grid-forming and grid-following system is obtained according to the improved short circuit ratio (ISCR), where the GFMC is in parallel at the point of common coupling (PCC) of the GFLC. Then, an adaptive adjustment strategy of the active power droop control is proposed to enhance the oscillation suppression capability across the full frequency range, thereby mitigating the wideband oscillation caused by phase-locked loop (PLL) synchronization in the GFLCs. Additionally, a first-order inertia control unit is added to the active and reactive power droop controllers to mitigate frequency and voltage variations as well as suppress potential mid-to-high frequency resonance. Finally, the wideband oscillation suppression strategy is validated by the simulation and experimental results.

To generate high frequency signals for frequency modulated continuous wave (FMCW) application, components such as doubler, tripler or multiplier are usually utilized to process further signals from the low frequency voltage controlled oscillator (VCO). In this paper, a phase-locked loop (PLL) is intended to be the primary part used to generate frequency modulated continuous wave (FMCW) signals from 80 to 84.8 GHz by utilizing a fundamental frequency VCO. To divide those high frequency output signal and large output bandwidth, the auto-tracking Miller divider topology is proposed. This new topology can achieve 9 GHz locking range. In order to generate FMCW signals with a straight-line triangular chirp, the cascaded PLL is used. The integrated jitter from 1 kHz to 1 GHz is 887 fs for the cascaded PLL, while the single stage PLL used 1.264 ps. Moreover, when architecture with doubler or multiplier is used, the fundamental tone has an effect towards the next systems, while the cascaded PLL does not. It can be highlighted that this work achieves the best RMS-FMerror/BWchirp and RMS-FMerror/(BWchirp × fc × Tc) with value of 0.013% and 0.77e−12, respectively. The designed PLL for FMCW signal generator is implemented in 28 nm CMOS technology. By using a supply voltage of 1.2 V, the chip consumes power of 102 mW. Including all the chip pads, the implemented circuit occupies a silicon area of 1440 µm × 820 µm. [ABSTRACT FROM AUTHOR]

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The Internet of Things (IoT) is pivotal in transforming the way we live and interact with our surroundings. To cope with the advancement in technologies, it is vital to acquire accuracy with the speed. A phase frequency detector (PFD) is a critical device to regulate and provide accurate frequency in IoT devices. Designing a PFD poses challenges in achieving precise phase detection, minimising dead zones, optimising power consumption, and ensuring robust performance across various operational frequencies, necessitating complex engineering and innovative solutions. This study delves into optimising a PFD circuit, designed using 90 nm standard CMOS technology, aiming to achieve superior operational frequencies. An efficient and high-frequency PFD design is crafted and analysed using cadence virtuoso. The study focused on investigating the impact of optimising PFD design. With the optimised PFD, an operational frequency of 5 GHz has been achieved, along with a power consumption of only 29 µW. The dead zone of the PFD was only 25 ps. [ABSTRACT FROM AUTHOR]

This paper presents a charge pump circuit with a wide output range and low current mismatch applied to phase-locked loops. In this designed structure, T-shaped analog switches are adopted to suppress the non-ideal effects of clock feedthrough, switching time mismatch, and charge injection. A source follower and current splitting circuits are proposed to improve the matching accuracy of the charging and discharging currents and reduce the current mismatch rate. A rail-to-rail high-gain amplifier with a negative feedback connection is introduced to suppress the charge-sharing effect of the charge pump. A cascode current mirror with a high output impedance is used to provide the charge and discharge currents for the charge pump, which not only improves the current accuracy of the charge pump but also increases the output voltage range. The proposed charge pump is designed and simulated based on a 65 nm CMOS process. The results show that when the power supply voltage is 1.2 V, the output current of the charge pump is 100 μA, the output voltage is in the range of 0.2~1 V, and the maximum current mismatch rate and current variation rate are only 0.21% and 1.4%, respectively.

This study reports on the results of an experimental investigation into a multi-objective nonlinear oscillator-based frequency-locked loop with an advanced pre-filter in a three-phase photovoltaic grid interface employing direct and quadrature hysteresis control for a distribution system. A reference voltage generation approach is also used to obtain the most power out of the solar array. In various case studies, including reactive and real power balance between load, grid, and photovoltaic systems under uncertain and varying solar power conditions, the proposed nonlinear second-order generalized integrator-based frequency-locked loop with an advanced filter performance is compared to a second-order generalized integrator-based frequency-locked loop. The proposed control enabled more stable operation and appropriate synchronization when grid voltages were distorted by the combined action of dc offset and harmonics. According to experiments, the suggested control achieves grid synchronization more correctly under abrupt changes in grid conditions and disturbances. The findings of an experimental laboratory prototype are confirmed using power quality indices for harmonic distortion assessment of source currents, as defined by the IEEE-519 guidelines. [ABSTRACT FROM AUTHOR]

This paper presents the design and performance analysis of a wideband charge-pump phase-locked loop (CPPLL) characterized by low reference spur and low phase noise. The proposed CPPLL, operating as a wideband phase-locked loop (PLL) with a reference frequency of 100 MHz, achieves a wide tuning range of 40% from 2.0 GHz to 3.0 GHz. A clock feedthrough suppressed charge pump with additional bias current branches is used to reduce the PLL's loop reference spur. The 4-stage current mode logic (CML) divide-by-2/3 circuit is utilized in the frequency divider to achieve high-speed frequency division. The circuit of an AND gate and latch in the 2/3 divider adopts a full differential symmetric structure to minimize the phase error of high-frequency differential signals. The voltage-controlled oscillator (VCO) is designed to provide a wide tuning range while optimizing the trade-off between the phase noise and power consumption. The fabricated PLL is implemented using a 0.13 µm CMOS process. Experimental measurements reveal a reference spur of −74.39 dBc at an oscillation frequency of 2.4 GHz. Moreover, the CPPLL achieves phase noise of −102.55 dBc/Hz@100 kHz and −127.15 dBc/Hz@1 MHz, while consuming 33.6 mW under a 1.2 V supply voltage. The integrated root-mean-square (rms) jitter, measured from 10 kHz to 10 MHz, is 340.99 fs, and the figure-of-merit (FoM) is −234.08 dB at a carrier frequency of 2.4 GHz, highlighting the potential of the proposed PLL for integrated circuit applications. [ABSTRACT FROM AUTHOR]

In this paper, an optoelectronic oscillator (OEO) with ultra-low phase noise and high stability based on the injection-locked and phase-locked loop is proposed. In theory, the injection-locked frequency range of the injection signal is studied based on the phase dynamics equation, and the phase noise performance of the injection-locked OEO is analyzed. The role of the phase-locked loop on the frequency stability of the OEO is analyzed based on the phase-locked loop transfer function. In addition, this paper builds an injection-locked OEO based on a phase-locked loop. The injection-locked signal is the high-frequency output of the multiplication crystal oscillator (MCO). At the same time, this MCO synchronously outputs a low-frequency signal, which is used as the reference signal of the phase-locked loop. The experimental results show that the proposed OEO output frequency is 10 GHz, and the phase noise is −89.25 dBc/Hz@100 Hz, −121.71 dBc/Hz@1 kHz, and −145.39 dBc/Hz@10 kHz; the side-mode suppression ratio is 80 dB; the frequency stability is 2.06 × 10−11@1 s, 9.03 × 10−11@10 s, 1.03 × 10−10@100 s, and 3.03 × 10−10@1000 s. Consistent with the theoretical analysis results, the solution takes into account the frequency stability, side-mode suppression ratio, and phase noise performance. The simple structure is more advantageous in practical applications.

A 19‐GHz low‐phase‐noise PLL‐frequency synthesizer is presented in this letter that is intended to be used in a K‐band FMCW radar which requires strict phase noise for detecting a small unmanned aerial vehicle. The 17.9 to 19.5‐GHz PLL includes a Darlington cross‐coupled capacitive‐degeneration VCO which presents higher maximum attainable oscillation frequency (ƒtrans) and larger negative transconductance (gm), thus resulting in low phase noise. Manufactured using the SiGe BiCMOS process, the K‐band synthesizer demonstrates −114 dBc/Hz at 1 MHz offset and −138 dBc/Hz at 10 MHz offset from 19.456 GHz locking carrier frequency. [ABSTRACT FROM AUTHOR]

Summary: In this article, an injection‐locked frequency divider (ILFD) is presented. By assuming the maximum phase of the tank current, we obtain a relation for the lock range. Besides, the effects of parasitic capacitors on the lock range have been probed. The analysis shows that the greater the phase difference between the tail current and injected signal, the phase of the tank current increases and, consequently, the lock range also increases. The accomplished simulations confirm the correct performance of the proposed design and the extracted relationships. The simulations have been CMOS technology and with a 0.9‐V supply voltage. The results show that the current consumption equals 3.7 mA and the power consumption equals 3.33 mW. The proposed ILFD lock range with phase shift technique with power input signal 0 dBm is equal to 5.1 GHz (3.6–8.7 GHz), and the relative percentage of the lock range is also 83%. [ABSTRACT FROM AUTHOR]

The dynamic monitoring, control, and protection of modern power systems in real time require time-stamped electrical measurements to accurately estimate the bus voltage phasors using the state estimation function under normal and abnormal conditions. These measurements can be acquired by time-synchronized devices, known as phasor measurement units (PMUs). PMUs can measure bus voltage and branch current phasors of a three-phase network, as well as the frequency and the rate of change of frequency (ROCOF), with high speed, accuracy and time stamping provided by global positioning system (GPS) at the coordinated universal time (UTC). Various phasor estimation algorithms have been proposed in the literature, while most of them are concentrated in the discrete Fourier transform (DFT) algorithm, where an integer number of samples multiple of the nominal frequency is required for the computations. In cases where the frequency of the power grid deviates from its nominal value, the raw application of the DFT approach can lead to large errors during phasor estimation. Another approach of the phasor estimation is based on the phase-locked loop (PLL) techniques, widely used in grid tie inverters. PLL techniques can track dynamically (continuous time) the estimated frequency to the time-variant frequency of the power grid. A brief introduction to the basic concepts of the synchrophasor definition is provided, while the main DFT methods for synchrophasor estimation according to recent literature are mentioned. PLL-based PMU techniques are reviewed for both steady-state and dynamic conditions according to IEEE standards. In conclusion, the performance of PLL-based PMU algorithms presented in this literature review is discussed. [ABSTRACT FROM AUTHOR]

Determining the loop noise bandwidth and the coherent integration time is essential and important for the design of a reliable digital phase-locked loop (DPLL) in global navigation satellite system (GNSS) receivers. In general, designers set such parameters approximately by utilizing the well-known fact that the DPLL is stable if the normalized bandwidth, which is the product of the integration time and the noise bandwidth, is much less than one. However, actual limit points are not fixed at exactly one, and they vary with the loop filter order and implementation method. Furthermore, a lower limit on the normalized bandwidth may exist. This paper presents theoretical upper and lower limits for the normalized bandwidth of DPLL in GNSS receivers. The upper limit was obtained by examining the stability of DPLL with a special emphasis on the digital integration methods. The stability was investigated in terms of z-plane root loci with and without the consideration of the computational delay, which is a delay induced by the calculation of the discriminator and the loop filter. The lower limit was analyzed using the DPLL measurement error composed of the thermal noise, oscillator phase noise, and dynamic stress error. By utilizing the carrier-to-noise density ratio threshold which indicates the crossing point between the measurement error and the corresponding threshold, the lower limit of the normalized bandwidth is obtained. [ABSTRACT FROM AUTHOR]

This paper presents a wide‐band charge‐pump phase‐locked loop (CPPLL) with reference spur reduction techniques. To broaden the frequency range without deteriorating phase noise, a 6‐bit capacitor array‐based VCO and an automatic frequency calibrator (AFC) are used. A compact loop filter technique saves the capacitor area and maintains the bandwidth. Also, a novel charge pump with dynamic current matching circuit is proposed to reduce the reference spur of the PLL. The current mismatch is less than 0.22 μA (0.16%) over the voltage range from 0.75 to 1.55 V. Fabricated in 0.13 μm CMOS technology, the proposed PLL achieves a locking range of 7.6–12.3 GHz (47.2%), with a 25 MHz frequency interval. The PLL consumes 23.3 mA from a 2.5 V supply voltage and occupies a core area of 0.92 mm × 0.72 mm. The reference spur of the proposed PLL is measured to be −81.1 dBc, and in‐band phase noise reaches −110.8 dBc/Hz at 1 MHz offset frequency from the 9.5 GHz carrier frequency. [ABSTRACT FROM AUTHOR]

The biggest challenge associated with a renewable energy source (RES) based microgrids is to maintain their frequency stability. In solving this challenge, virtual inertia control (VIC) could be viewed as an unavoidable part of alternating current (AC) microgrids. For VIC, a phase-locked loop (PLL) is essential for obtaining information regarding the changes in the frequency of the microgrid. However, implementation of PLL might cause greater oscillation in frequency because of its system dynamics. Such type of issues can be resolved by using a multistage proportional integral derivative (PID) controller which restricts the undesirable frequency measurement and thus helps in improving the stability of the microgrid. In this paper, a novel Sine augmented scaled arithmetic optimization algorithm is proposed in purpose to tune the parameters of the aforementioned controller. The effectiveness of the proposed methodology is validated through contrastive simulation results, and the impact of a few standard strategies such as a change in system boundaries and various steps of RESs penetration are also demonstrated. • The concept of virtual inertia control (VIC) is proposed for frequency control in an AC microgrid. • Impact of RESs on virtual inertia control-based AC microgrid is investigated. • By altering the original AOA algorithm, a Sine augmented scaled AOA algorithm is created. • SCA-AOA algorithm is compared with AOA and other algorithms in terms of fitness function. • A MSPID controller is designed with the SCA-AOA algorithm for the VIC-based AC microgrid. [ABSTRACT FROM AUTHOR]

A thorough investigation of major contributors to out-of-band emission (OOBE) in transmitters (TXs) utilizing digital modulation schemes is provided. Specifically, the paper delves into the detrimental effects of phase noise of the local oscillator (LO), typically realized using a phase-locked loop (PLL), on the OOBE phenomenon. Furthermore, the effects of the circuit nonlinearity in a TX, widely recognized as a primary contributor to spectral regrowth and elevated levels of OOBE, are investigated. Additionally, the impact of filtering and bandwidth (BW) limitation on OOBE is taken into account. Comprehensive simulations verify the accuracy of the analytical study. The results provided throughout this paper can be used to determine the linearity and phase noise requirements of different blocks, such as PLL and power amplifier (PA) within a TX chain to design a system complying with a specific mask emission dictated by a particular standard.

The dynamic coupling effect, which is introduced by the dual-sequence phase-locked loops (PLLs) used in doublyfed induction generator (DFIG) based wind energy generation systems (WEGSs) during asymmetric low voltage ride-through (LVRT) in weak grid, needs attention. In order to study this new dynamic coupling effect, an equivalent two-degree-of-freedom (2-DOF) spring damper particle model is used in this paper to develop a small-signal model for the dual-sequence PLLs. The dynamic interaction between the positive-sequence (PS) and negative-sequence (NS) PLLs is unveiled. Moreover, the impact of the dynamic coupling between the dual-sequence PLLs on the dynamic stability during the steady-state stage of an asymmetric fault is analyzed. The analysis results show that the dynamic coupling between the dual-sequence PLLs will cause drift in the frequency and damping for the PS and NS PLL modes. This will change the instability modal of the system and introduce the risk of dynamic instability. Hence, the effectiveness of existing control strategies for enhancing the dynamic stability will be decreased. Finally, a novel PLL structure is designed to improve the dynamic stability of the system during the steady-state stage of an asymmetric fault. The effectiveness of the proposed strategy is verified by simulations and experiments.

This article presents an enhanced power-synchronized grid-following inverter (ePSGFLI) for reliable and stable integration of renewable energy resources into the grid. By eliminating the use of a phase-locked loop (PLL) in the control loop, the ePSGFLI resolves instability issues commonly associated with conventional PLL-based grid-following inverters (GFLIs). Furthermore, in contrast to existing PLL-less strategies like linear parameter-varying control of power-synchronized GFLI (LPV-PSGFLI), which suffer from steady-state errors and instability during grid frequency deviations, the proposed ePSGFLI ensures stable performance without steady-state errors, regardless of the strength of the grid. To achieve robust and accurate tracking of grid frequency, even under significant deviations, while effectively decoupling the active and reactive power loops, the ePSGFLI employs a loop-shaping design procedure for real-time auto-tuning of the multivariable second-order 2-by-2 outer power controller. The effectiveness of the proposed ePSGFLI is validated via simulations in MATLAB/Simulink and experimental testing under both strong and weak grid connections. The results demonstrate its superior performance compared to existing PLL-based and PLL-less control strategies in terms of stable operation and accurate tracking of power and grid frequency.

Voltage source converter based high-voltage direct current (VSC-HVDC) transmission technology has been extensively employed in power systems with a high penetration of renewable energy resources. However, connecting a voltage source converter (VSC) to an AC weak grid may cause the converter system to become unstable. In this paper, a phase-shift phase-locked loop (PS-PLL) is proposed wherein a back electromotive force (BEMF) observer is added to the conventional phase-locked loop (PLL). The BEMF observer is used to observe the voltage of the infinite grid in the stationary $\alpha\beta$ frame, which avoids the problem of inaccurate observations of the grid voltage in the $dq$ frame that are caused by the output phase angle errors of the PLL. The VSC using the PS-PLL can operate as if it is facing a strong grid, thus enhancing the stability of the VSC-HVDC system. The proposed PS-PLL only needs to be properly modified on the basis of a traditional PLL, which makes it easy to implement. In addition, because it is difficult to obtain the exact impedance of the grid, the influence of short-circuit ratio (SCR) estimation errors on the performance of the PS-PLL is also studied. The effectiveness of the proposed PS-PLL is verified by the small-signal stability analysis and time-domain simulation.

This paper offers a detailed analysis as well as a tuning and discretization approach of the presented frequency-fixed dual second order generalized integrator based phase-locked loop (FFDSOGI-PLL) for three-phase power systems. The method combines different single- and three-phase PLL approaches by ensuring high phase- and frequency tracking properties. The comparison with the standard frequency-variable DSOGI-PLL and three different recently published three-phase frequency and phase-angle estimation systems shows, that this approach gives a fast and stable phase and frequency detection of the grid voltage with very low computational burden. The results are applicable to, for instance, photovoltaic or frequency converters or active power filters.

A low‐noise fully‐integrated charge‐pump phase‐locked loop (CPPLL) for 5G applications is presented in this letter. The PLL architecture includes a phase and frequency detector (PFD), a charge pump (CP), a low‐pass filter (LPF), a voltage‐controlled oscillator (VCO), and a programmable divider. To achieve low phase noise, class‐C VCO, TSPC logic, and other methods are employed in the PLL circuit design. Fabricated in 65 nm technology, the PLL measures a tuning range of 5.91–8.94 GHz. The minimum and maximum measured phase noise are −125 dBc/Hz and −116.6 dBc/Hz @1 MHz. The size of CPPLL core area is 0.8 mm by 0.95 mm without the pads while having a 50‐mW power consumption. [ABSTRACT FROM AUTHOR]

This study develops a multiphase voltage-controlled oscillator (VCO) by using the subfeedback loop technique. The proposed N-stage ring oscillator with k-stage subfeedback loops (where N is not a multiple of k) has N output phases, and its operating frequency is as high as that of the k-stage subfeedback loops. Circuit analysis and simulation processes for design optimization are presented herein. The first-order linear inverter model of the proposed ring oscillator defines the relationship between its operating frequency and phase number. In the topology of the proposed oscillator, the operating frequency does not decrease as the number of stages of the ring oscillator increases. The proposed multiphase VCO is verified in a 5-GHz 12-phase phase-locked loop. The test chip is implemented in a 0.18-μm complementary metal–oxide–semiconductor process, and its core area is determined to be 260 × 355 μm2. The root mean square jitter and peak-to-peak jitter are 1.03 and 8.85 ps, respectively. The phase noise of the output signal is − 91.44 dBc/Hz at 1-MHz. [ABSTRACT FROM AUTHOR]