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The development of ultrathin (≤5 nm) hafnia‐based ferroelectric (FE) films is essential for achieving low operating voltages, facilitating their integration into advanced process nodes for low‐power and non‐volatile memory applications. However, challenges in ultrathin FE films arise from the depolarization field and interface‐related issues, leading to an antiferroelectric‐like (AFE‐like) polarization switching behavior and more significant wake‐up effects, causing operational inconvenience and reliability concerns. Here, interface‐modulated ferroelectricity is reported in 4 nm Hf0.5Zr0.5O2 (HZO) thin films, demonstrating excellent properties with low operating voltage, enhanced switching speed, and high reliability. Electrical and structural characterizations reveal that adjusting interface asymmetry may introduce a substantial built‐in field (Ebi) and an AFE‐like switching behavior can exhibit a robust FE‐like characteristic. This AFE‐to‐FE‐like transition is driven by switching kinetics rather than commonly proposed phase transitions. Furthermore, a comprehensive model is developed to elucidate the intricate physics of the modulation mechanism by asymmetric interfaces, emphasizing the critical roles of depolarizing effects and Ebi on ferroelectricity. This work underscores the importance of interfaces in engineering ferroelectricity for advanced electronic applications. [ABSTRACT FROM AUTHOR]

Resistive Random-Access Memory (RRAM) presents a transformative technology for diverse computing and artificial intelligence applications. However, variability in the high resistance state (HRS) has proved to be a challenge, impeding its widespread adoption. This study focuses on optimizing TaOx -based RRAMs by strategically placing a nitrogen-doped TaOx barrier-layer (BL) to mitigate variability in the HRS. Through comprehensive electrical characterization and measurements, we uncover the critical influence of BL positioning on HRS variability and identify the optimal location of the BL to achieve a 2x lowering of HRS variability as well as an expanded range of operating voltages. Incremental reset pulse amplitude measurements show that the TaOx :N maintains a low HRS variability even at higher operating voltages when the position of the BL is optimized. Our findings offer insights into stable and reliable RRAM operation, highlighting the potential of the proposed BL to enhance the functionality of TaOx -based RRAMs and elevate overall device performance. [ABSTRACT FROM AUTHOR]

Resistive Random-Access Memory (RRAM) presents a transformative technology for diverse computing and artificial intelligence applications. However, variability in the high resistance state (HRS) has proved to be a challenge, impeding its widespread adoption. This study focuses on optimizing TaOx-based RRAMs by strategically placing a nitrogen-doped TaOx barrier-layer (BL) to mitigate variability in the HRS. Through comprehensive electrical characterization and measurements, we uncover the critical influence of BL positioning on HRS variability and identify the optimal location of the BL to achieve a 2x lowering of HRS variability as well as an expanded range of operating voltages. Incremental reset pulse amplitude measurements show that the TaOx:N maintains a low HRS variability even at higher operating voltages when the position of the BL is optimized. Our findings offer insights into stable and reliable RRAM operation, highlighting the potential of the proposed BL to enhance the functionality of TaOx-based RRAMs and elevate overall device performance.

Neuromorphic Computing, a concept pioneered in the late 1980s, is receiving a lot of attention lately due to its promise of reducing the computational energy, latency, as well as learning complexity in artificial neural networks. Taking inspiration from neuroscience, this interdisciplinary field performs a multi-stack optimization across devices, circuits, and algorithms by providing an end-to-end approach to achieving brain-like efficiency in machine intelligence. On one side, neuromorphic computing introduces a new algorithmic paradigm, known as Spiking Neural Networks (SNNs), which is a significant shift from standard deep learning and transmits information as spikes (“1” or “0”) rather than analog values. This has opened up novel algorithmic research directions to formulate methods to represent data in spike-trains, develop neuron models that can process information over time, design learning algorithms for event-driven dynamical systems, and engineer network architectures amenable to sparse, asynchronous, event-driven computing to achieve lower power consumption. On the other side, a parallel research thrust focuses on development of efficient computing platforms for new algorithms. Standard accelerators that are amenable to deep learning workloads are not particularly suitable to handle processing across multiple timesteps efficiently. To that effect, researchers have designed neuromorphic hardware that rely on event-driven sparse computations as well as efficient matrix operations. While most large-scale neuromorphic systems have been explored based on CMOS technology, recently, Non-Volatile Memory (NVM) technologies show promise toward implementing bio-mimetic functionalities on single devices. In this article, we outline several strides that neuromorphic computing based on spiking neural networks (SNNs) has taken over the recent past, and we present our outlook on the challenges that this field needs to overcome to make the bio-plausibility route a successful one. [ABSTRACT FROM AUTHOR]

This paper considers coding for so-called partially stuck (defect) memory cells. Such memory cells can only store partial information as some of their levels cannot be used fully due to, e.g., wearout. First, we present new constructions that are able to mask u partially stuck cells while correcting at the same time t random errors. The process of "masking" determines a word whose entries coincide with writable levels at the (partially) stuck cells. For u > 1 and alphabet size q > 2 , our new constructions improve upon the required redundancy of known constructions for t = 0 , and require less redundancy for masking partially stuck cells than former works required for masking fully stuck cells (which cannot store any information). Second, we show that treating some of the partially stuck cells as erroneous cells can decrease the required redundancy for some parameters. Lastly, we derive Singleton-like, sphere-packing-like, and Gilbert–Varshamov-like bounds. Numerical comparisons state that our constructions match the Gilbert–Varshamov-like bounds for several code parameters, e.g., BCH codes that contain all-one word by our first construction. [ABSTRACT FROM AUTHOR]

Due to its non-volatility and large capacity, NVM devices gradually take place at various levels of memories. However, their limited endurance is still a big concern for large-scale data centres. Compression algorithms have been used to save NVM space and enhance the efficiency of those lifetime extension methods. However, their own influence on the NVM lifetime is not clear. In order to fully investigate the impact of compression on NVM, this paper first studies bit flips involved in several typical compression algorithms. It is found that more bit flips would happen in the shrunken area of a memory block. This induces the phenomenon of intra-block wear unevenness, which sacrifices NVM lifetime. We propose a new metric called local bit flips to describe this phenomenon. In order to relieve the intra-block wear unevenness caused by compression, this paper proposes a sliding write method named SlidW to distribute the compressed data across the whole memory block. We first divide the memory block into several areas, and then consider five cases about the relationship between new data size and left space. Then, we place the new data according to the case. Comprehensive experimental results show that SlidW can efficiently balance wear and enhance NVM lifetime. [ABSTRACT FROM AUTHOR]

Non-volatile memories based on the flash architecture with self-assembled III–V quantum dots (SAQDs) used as a floating gate are one of the prospective directions for universal memories. The central goal of this field is the search for a novel SAQD with hole localization energy (Eloc) sufficient for a long charge storage (10 years). In the present work, the hole states' energy spectrum in novel InGaSb/AlP SAQDs was analyzed theoretically with a focus on its possible application in non-volatile memories. Material intermixing and formation of strained SAQDs from a GaxAl1−xSbyP1−y, InxAl1−xSbyP1−y or an InxGa1−xSbyP1−y alloy were taken into account. Critical sizes of SAQDs, with respect to the introduction of misfit dislocation as a function of alloy composition, were estimated using the force-balancing model. A variation in SAQDs' composition together with dot sizes allowed us to find that the optimal configuration for the non-volatile memory application is GaSbP/AlP SAQDs with the 0.55–0.65 Sb fraction and a height of 4–4.5 nm, providing the Eloc value of 1.35–1.50 eV. Additionally, the hole energy spectra in unstrained InSb/AlP and GaSb/AlP SAQDs were calculated. Eloc values up to 1.65–1.70 eV were predicted, and that makes unstrained InGaSb/AlP SAQDs a prospective object for the non-volatile memory application. [ABSTRACT FROM AUTHOR]

New technologies for non-volatile memories combine the speed and byte addressability of current memory technologies with the low cost, density, and non-volatility of current storage technologies. They use energy only when writing or reading data. While some newer technologies have practically unlimited endurance, others, such as Phase Change Memory do not. However, this limited endurance surpasses that of solid state drives by several orders of magnitude. They can be integrated into the current memory storage hierarchy as a replacement for DRAM. To manage limited endurance, age-based wear leveling divides the memory into pages and counts the number of writes to a page. Pages with high counts can then be relegated to store more stable data. Counters experience “write concentration” as they are incremented as frequently as a page is written, but the changes are concentrated in a much smaller area around the least significant bit. Current designs store page write counters with the page table in the main memory unit.We propose and investigate an alternative counter design based on Gray codes that distributes the bit-flips resulting from the increments over the vast majority of the bits making up the counter. This is a bit-flip aware data structure that can be used in other contexts as well. We show that this design allows us to integrate the page counters into the phase change memory device. We also investigate counters using error control codes.

The rapid increase in CPU processing speeds has significantly advanced artificial intelligence, yet it has also exacerbated the disparity in CPU utilization and data throughput rates due to the shared memory architecture of traditional von Neumann systems. To enhance computational efficiency, there is a critical need to explore advanced functional materials and integrate these into novel computing architectures. Two-dimensional (2D) ferroelectric materials, characterized by their atomic-scale ferroelectric non-volatile properties and low switching barriers, emerge as promising candidates. These materials are particularly suitable for use as non-volatile resistors and artificial synapses within in-memory computing frameworks. Furthermore, their compatibility with Si-CMOS technology enables the high-density integration of devices, potentially driving a new paradigm in integrated computation between processing units and storage architectures. This review focuses on recent developments in 2D ferroelectric materials, including their structural properties, polarization switching mechanisms, and diverse applications. Special emphasis is placed on their potential in integrated applications such as non-volatile memories, neural network computing, non-volatile logic operations, and optoelectronic memories within neuromorphic computing devices. [ABSTRACT FROM AUTHOR]

Ge–Sb–Te (GST) alloys are an important family of phase‐change materials employed in non‐volatile memories and neuromorphic devices. Conventional memory cells based on GST rely on the switching between an amorphous state and a metastable, disordered rocksalt‐like phase. Recently, however, it has been proposed that a special type of defect in layer‐structured GST—the so called "swapped bilayer" defect—is responsible for a novel phase‐change mechanism observed in GST‐based superlattices. Thus, disorder appears to play an important role in both types of switching mechanisms. Here, the observation of a new in‐plane twinning defect in hexagonal GeSb2Te4 by direct atomic‐scale imaging experiments is reported, which serves as the key ingredient to account for the abundance of inverted stacking faults in hexagonal GST and superlattices. Ab initio simulations reveal a low energy cost for these extended defects, and indicate that such defects can affect the electrical properties by inducing electron localization. This work provides additional insight into the nature and effects of structural disorder in GST phase‐change materials. [ABSTRACT FROM AUTHOR]

Ge–Sb–Te (GST) alloys are an important family of phase‐change materials employed in non‐volatile memories and neuromorphic devices. Conventional memory cells based on GST rely on the switching between an amorphous state and a metastable, disordered rocksalt‐like phase. Recently, however, it has been proposed that a special type of defect in layer‐structured GST—the so called "swapped bilayer" defect—is responsible for a novel phase‐change mechanism observed in GST‐based superlattices. Thus, disorder appears to play an important role in both types of switching mechanisms. Here, the observation of a new in‐plane twinning defect in hexagonal GeSb2Te4 by direct atomic‐scale imaging experiments is reported, which serves as the key ingredient to account for the abundance of inverted stacking faults in hexagonal GST and superlattices. Ab initio simulations reveal a low energy cost for these extended defects, and indicate that such defects can affect the electrical properties by inducing electron localization. This work provides additional insight into the nature and effects of structural disorder in GST phase‐change materials. [ABSTRACT FROM AUTHOR]

Nowadays, many electronic systems store valuable Intellectual Property (IP) information inside Non-Volatile Memories (NVMs). Designers widely use encryption mechanisms to enhance the integrity of such IPs and protect them from any unauthorized access or modification. At the same time, often such IPs are critical from a reliability standpoint. Thus, dedicated techniques are employed to detect possible reliability threats (e.g., transient faults affecting the NVM content). The weights of a neural network (NN) model (e.g., integrated into an object detection system for autonomous driving or robotics) are typical examples of precious IP items. Indeed, NN weights often constitute proprietary data, stemming from an extensive and costly training process; moreover, their correctness is key for the NN to work reliably. In this article, we explore the capability of encryption mechanisms to ensure protection from both reliability threats. In particular, we assess, via extensive fault injection campaigns, the capability of different memory encryption schemes – usually used only for security purposes – to detect faults and thus, enhance the reliability of the system. Experimental results show that, by cleverly choosing the proper encryption scheme, it is possible to achieve very high fault detection rates (greater than 99%) with respect to Multiple Bit Upsets. The gathered results pave the way to the integration of reliability and security mechanisms to achieve better results with lower costs.

Multi-level-cell (MLC) spin-torque transfer magnetic random access memory (STT-MRAM) suffers from reliability issues due to the highly asymmetric error rates of its hard and soft domains. In this communication, we have proposed to include a symbol mapper prior to writing bits to the MRAM and have jointly optimized the mapping and polar codes with iterative, soft-cancellation (SCAN) decoder. Specifically, we perform code search and symbol mapping based on the extrinsic information transfer curves of a posteriori probability demapper and the SCAN decoder. We identify a number of variations of Gray code-based mappings, each promising best waterfall, convergence, and/or error-floor performances. In particular, our simulation results demonstrate that one of our proposed mapping achieves a bit-error-rate which is nearly three orders of magnitude lower than that of the conventional binary mapping and outperforms other Gray-code variants at a resistance spread up to 18% and hard bit write errors up to multiples of 10−3. [ABSTRACT FROM AUTHOR]

In this paper, we study a model that mimics the programming operation of memory cells. This model was first introduced by Lastras-Montano et al. for continuous-alphabet channels, and later by Bunte and Lapidoth for discrete memoryless channels (DMC). Under this paradigm we assume that cells are programmed sequentially and individually. The programming process is modeled as transmission over a channel, such that it is possible to read the cell state in order to determine its programming success, and in case of programming failure, to reprogram the cell again. Reprogramming a cell can reduce the bit error rate, however this comes with the price of increasing the overall programming time and thereby affecting the writing speed of the memory. An iterative programming scheme is an algorithm which specifies the number of attempts to program each cell. Given the programming channel and constraints on the average and maximum number of attempts to program a cell, we study programming schemes which maximize the number of bits that can be reliably stored in the memory. We extend the results by Bunte and Lapidoth and study this problem when the programming channel is either discrete-input memoryless symmetric channel (including the BSC,BEC, BI-AWGN) or the $Z$ channel. For the BSC and the BEC our analysis is also extended for the case where the error probabilities on consecutive writes are not necessarily the same. Lastly, we also study a related model which is motivated by the synthesis process of DNA molecules. [ABSTRACT FROM AUTHOR]

Due to its non-volatility and large capacity, NVM devices gradually take place at various levels of memories. However, their limited endurance is still a big concern for large-scale data centres. Compression algorithms have been used to save NVM space and enhance the efficiency of those lifetime extension methods. However, their own influence on the NVM lifetime is not clear. In order to fully investigate the impact of compression on NVM, this paper first studies bit flips involved in several typical compression algorithms. It is found that more bit flips would happen in the shrunken area of a memory block. This induces the phenomenon of intra-block wear unevenness, which sacrifices NVM lifetime. We propose a new metric called local bit flips to describe this phenomenon. In order to relieve the intra-block wear unevenness caused by compression, this paper proposes a sliding write method named SlidW to distribute the compressed data across the whole memory block. We first divide the memory block into several areas, and then consider five cases about the relationship between new data size and left space. Then, we place the new data according to the case. Comprehensive experimental results show that SlidW can efficiently balance wear and enhance NVM lifetime.

Ambipolar field‐effect transistors allowing both holes and electrons transport can work in different states, which are attractive for simplifying the manufacture of circuits and endowing the circuits with reconfigurable multi‐functionalities. However, conventional ambipolar transistors intrinsically suffer from poor switching‐off capability because the gate electrode is not able to simultaneously deplete holes and electrons across the entire transport channel, which hurdles the practical applications. This study shows that the switching‐off capability of polymer ambipolar transistor is significantly improved by up to three orders by introducing non‐uniformly distributed compensation potentials along the channel to synchronically tune the charge transport at different channel locations. The non‐uniform compensation potential is experimentally generated by the non‐uniformly distributed electret charges, which are pre‐injected into the insulators from source and drain electrodes. By this method, both n‐type and p‐type operations with high mobility (2.2 and 0.8 cm2s−1V−1 respectively) and high on/off ratio (105) are obtained in the same device, and the different states are reversibly switchable. Moreover, this method endows the device with diverse device characteristics and reconfigurable multi‐functionalities, which promotes the application of ambipolar transistors in complementary metal‐oxide semiconductors‐like circuits and some emerging electronics, including reconfigurable devices, multi‐level memories, and artificial synapses. [ABSTRACT FROM AUTHOR]

We report on the feasibility of k-means clustering techniques for the dynamic threshold detection of encoded q-ary symbols transmitted over a noisy channel with partially unknown channel parameters. We first assess the performance of k-means clustering technique without dedicated constrained coding. We apply constrained codes which allows a wider range of channel uncertainties so improving the detection reliability.

Hafnia‐based ferroelectric tunnel junctions (FTJs) hold great promise for nonvolatile memory and emerging data storage applications. In this article, a large tunnel electroresistance effect with ultrathin Hf0.5Zr0.5O2 (HZO) barrier based FTJs is reported. Robust ferroelectricity is achieved with ≈1 nm films by stabilizing the rhombohedral polar phase of HZO (R‐HZO) through a large compressive strain, induced by growing the film epitaxially on a SrTiO3 (001) substrate. The OFF/ON ratio of the junction resistance at zero bias is about 135 with ≈1 nm thick barrier, which increases to ≈105 with increasing the barrier thickness to ≈2.5 nm. The resistance‐area product (RA) of tunnel junctions is reduced by nearly three orders of magnitude by using an ≈1 nm R‐HZO barrier as compared with typically reported RA values for doped‐HfO2 barrier based FTJs, which significantly improves signal‐to‐noise ratio during the read operation. These results set the stage for further exploration of Hafnia‐based FTJs for non‐volatile memory applications. [ABSTRACT FROM AUTHOR]

Through a functional unit‐transmutation strategy, a fatigue‐free layered hybrid perovskite ferroelectric (C6H5CH2NH3)2CsPb2Br7 (BCPB) has been developed, which demonstrates stable spontaneous polarization (Ps) of 6.5 μC cm−2 and high Curie temperature up to 425 K. Meanwhile, BCPB shows splendid bulk photovoltaic effect (BPVE) properties with noticeable zero‐bias photocurrent density (5 μA cm−2), and high on/off switching ratio of current (over 3×105); these merits even overmatch the most known ferroelectric semiconductor BiFeO3. The unique structure with self‐regulated net electrical charged layers gives rise to the fatigue‐free feature of Ps and BPVE (no significant fatigue after 108 polarity switching cycles), promoting the potential applications of BCPB in photovoltaic non‐volatile memories. This work offers an efficient approach for exploring fatigue‐free semiconducting ferroelectrics as well as excavates their further applications in next‐generation electronic devices. [ABSTRACT FROM AUTHOR]

Carbon nanotubes based non-volatile memories (NVMs) with excellent electronic properties can provide high bit density and energy efficiency. But with the limit of the process conditions, obtaining steep flanks with large hysteresis is still a challenge, while it is the prerequisite for stable program/erase/read operations. Herein, we adopt a novel treatment of supercritical CO 2 (SCCO 2) fluids to improve the performance of all-carbon-nanotube thin-film transistor (A-CNT-TFT) memory elements. By the treatment, the transfer characteristics of the A-CNT-TFTs achieve a 13.20 V hysteresis window, which is larger than 50% of the whole sweeping-voltage range. The disappearance of hump effect greatly improves the switching characteristics. The material analysis confirms that the SCCO 2 fluids can reduce the defects in dielectric layer sufficiently and strengthen the connection between channel and gate dielectric. Furthermore, it is proposed that existence of hydroxyl groups in the carbon nanotubes contributes dominantly to the mechanism for charge storage, and the SCCO 2 treatment enhances the charge storage by increasing the number of the hydroxyl groups. The work shows that the low-temperature SCCO 2 treatment can better improve the performance of A-CNT-TFTs, which provides a promising option for nonvolatile charge storage memory devices. Image 1 [ABSTRACT FROM AUTHOR]

Energy consumption and predictability are two important constraints in designing real-time embedded systems and one of the recently proposed solutions for the energy consumption problem is the use of non-volatile memories instead of conventional SRAM due to their lower leakage power consumption and smaller cell area. Furthermore, because of their non-volatile nature, the use of these memories helps normally-off computing and energy harvesting systems to resume their execution without a large startup delay. However, the write access latency of non-volatile memories is considerably more than that of SRAM which can decrease the performance and predictability of the system if not managed correctly. In this article, we present a predictable fully non-volatile data memory for real-time embedded systems which improves both worst-case execution time (WCET) and performance of the system using a hybrid hardware-software solution. As part of this solution, we add a special write buffer to the memory controller and adopt a multi-bank memory configuration which improves the overall latency of write operations. Since write buffers usually help with the performance problem but they make WCET estimation more complex, we also present a new low-overhead software-based optimization technique that makes the proposed system more predictable without imposing considerable overhead. Furthermore, we present the WCET analysis algorithm which can be used to estimate the WCET of applications during the design time. The results show that compared to a hybrid SRAM-NVM architecture, the proposed solution improves the WCET and performance by 33 and 47 percent, respectively. [ABSTRACT FROM AUTHOR]

Herein, we investigate the technologically relevant blend of the ferroelectric polymer poly(vinylidene fluoride-co-trifluoroethylene), P(VDF-co-TrFE), with the semiconducting polymer poly(3-hexylthiophene), P3HT, by means of a combination of scanning probe microscopy techniques, namely atomic force microscopy, conductive force microscopy, kelvin probe force microscopy, and piezoresponse force microscopy. This combination proves to be a powerful tool for the non-destructive morphological reconstruction of multi-functional nano-structured thin films, as those under study. Each modality allows discerning the two blend constituents based on their functionality, and, additionally, probes layers of different thickness with respect to the film surface. The depth-dependent information that is collected allows a qualitative reconstruction of the blend's composition and morphology both in-plane and out-of-plane of the film. We demonstrate that P3HT exhibits the tendency to reside the film surface at an almost constant composition of 15%, independent of blend's composition. Increasing the P3HT content in the blend results in the segregation of P3HT at the upper layers of the films, partially buried below a P(VDF-co-TrFE) superficial layer. The depletion of P3HT from the substrate/film interface is reflected by the poor existence of conducting pathways that connect the top and bottom planes of the film. The three-dimensional morphology of this polymer blend that is revealed thanks to the employed techniques deviates substantially from the ideal morphology proposed for the efficient performance of the targeted memory devices. [ABSTRACT FROM AUTHOR]

The phenomena of resistance random access memory (RRAM) depending on the altering of resistance between at least two values has been found in materials such as transition metal oxides, some semiconductors or insulators materials, named as resistive switching. The developments on RRAM have been started due to its low power consumption, simple structure, high-density, high - speed resistive switching, impressive retention with smallfeature size. Regardless of the wide-ranging research, basic switching conduction mechanisms of the resistive memory structures are basically depending on the certain special materials. To improve the current structure performance, the Cellulose Acetate as a polymer was added to the active layer (cadmium selenide CdSe). The polymer material was used to form the second active coating to construct the Au/CdSe/polymer/Au as new structure. This material may enhance the cell performance by increasing the charges traps. This procedure leads to increasing resistance ratio (Rratio) and decreasing the working voltages of structure. A spin coating apparatus was used to coating the polymer layer on CdSe. The glass was used as a substrate and the first active layer deposited under vacuum by thermal evaporating system. The cell was sandwiched between the two electrodes in the same materials (Au) which deposited also under the same system. Bipolar resistive switch, in this memory structure, is observed in its switching operation. The zone of the upper electrode (Au) has a significant affect upon the resistive performance. This influence is became further in the big upper electrode zone (TEL=13.5mm2) where the high-resistance (HRS) are inversely related to the upper electrode zone (A). This occurs inducing more traps in case TEL (hanging sentence). Finally, the (Rratio) is directly proportional with the electrode zone (A). The compliance current (Icc=30mA) are used for protecting the structure from the damage. The current structure has many properties, such as Vset = 3.9V, VReset = -1.9V and Rratio about 176 in case of TEL. We conclude from this research that the embedment of a thin layer of a polymer which have been used in this research are improving the high density, enhancing high speed with low cost as well. [ABSTRACT FROM AUTHOR]

The combination of specialized hardware and embedded nonvolatile memories (eNVM) holds promise for energy-efficient deep neural network (DNN) inference at the edge. However, integrating DNN hardware accelerators with eNVMs still presents several challenges. Multilevel programming is desirable for achieving maximal storage density on chip, but the stochastic nature of eNVM writes makes them prone to errors and further increases the write energy and latency. In this article, we present MEMTI, a memory architecture that leverages a multitask learning technique for maximal reuse of DNN parameters across multiple visual tasks. We show that by retraining and updating only 10% of all DNN parameters, we can achieve efficient model adaptation across a variety of visual inference tasks. The system performance is evaluated by integrating the memory with the open-source NVIDIA deep learning architecture. [ABSTRACT FROM AUTHOR]

Abstract The rapid growth of miniaturized electronic devices has raised the demand for compact, flexible, wearable, and non-volatile memory units. However, integration into nanoelectronic devices requires a scaled-down data-storage component, but this often results in the deterioration of the ferroelectric switching performance. Herein, we demonstrate a simple and scalable fabrication of poly (vinylidene fluoride trifluoroethylene) [P(VDF-TrFE)] film with graphene oxide (GO) nanosheets. Using piezoresponse force microscopy (PFM), the storage features of this multilayer film were investigated, including establishment of two stable memory states, ferroelectric switching dynamics in the point-polarization and linear-polarization modes, and time and thermal stability of information storage. Remarkably, the GO-P(VDF-TrFE) film favored formation of low-temperature (LT) ferroelectric phase with much more ordered sequences of trans conformations relative to pristine P(VDF-TrFE) due to the presence of electrostatic interaction between GO nanosheets and C F dipoles of P(VDF-TrFE), thus affording improved ferroelectric properties. The GO-P(VDF-TrFE) film showed several excellent storage features, such as ultra-high density of more than 300 Gbits in−2, good writing & erasing repeatability, long data retention time, and elevated device operation temperature. In-depth understanding and utilization of the excellent non-volatile memory performance of this new GO-ferroelectric system will open new avenues for the next generation of nanoelectronic devices. Graphical abstract The GO-P(VDF-TrFE) multilayer film showed several excellent storage features, such as a significant asymmetry in the nucleation and domain growth, ultra-high density of >300 Gbits in−2, good writing & erasing repeatability, long data retention time and elevated device operation temperature. These excellent properties were closed related that low-temperature (LT) ferroelectric phase with much more ordered sequences of trans conformations relative to pristine P(VDF-TrFE) were formed in the GO-P(VDF-TrFE) multilayer film. Image 1 [ABSTRACT FROM AUTHOR]

Extensive research focuses on 2D MXenes ascribed to their adaptable behavior under external parameters, intrinsic ferroelectric nature through oxidation and their tailored conductive ability, resulting in exceptional electrochemical and flexible data storage applications. By virtue of these tunable capabilities, titanium carbide Ti 3 C 2 T x MXene (M) has been incorporated as electrodes in free-standing novel memory devices comprising of Bismuth Ferrite (BFO), Graphene Oxide (GO) and heated Ti 3 C 2 T x MXene (h-M) as active functional layers. These devices, owing to their distinct conduction mechanisms, transform the capacitive like resistive switching in M/BFO/M scheme to pure memristor switching with the addition of GO in M/BFO/GO/M, exhibiting potential ON/OFF ratio along with increased endurance of > 102, the factor crucial for practical implementations. Here also, the assistance of heated Ti 3 C 2 T x MXene as an additional active layer with BFO has marked the co-existence of negative differential resistance (NDR) along with resistance switching (RS) as a novel report, observed for the first time in M/BFO/h-M/M. The reproducibility of NDR and RS under 103 sweeps and three memory architectures with an ON/OFF resistance ratio of 102 have made them emerge as a potential ensemble for multi-level storage and multifunctional characteristics. This work fits the noticeable increase in ON/OFF ratio of M/BFO/h-M/M out of the three explored memristor devices and its current-voltage feature mimicking the charge-discharge response in energy storage domain will pave the way for next generation, non-volatile energy-efficient computing architectures as it holds immense importance for enhancing the density of integrated flexible electronics. [Display omitted] [ABSTRACT FROM AUTHOR]

Nowadays, the Ge-Sb-Te system is studied extensively for use in the field of both electrical and optical non-volatile memories. The key of this application is based on the changes in the physical properties (electrical conductivity or refractive index) of these films as a result of structural transformation between amorphous and crystalline states. Both states are highly stable and it is relatively easy to change between them when they are prepared as thin films. In this work, structural and electrical behaviours with the temperature of thin films with compositions Ge13Sb5Te82, Ge1Sb2Te4, Ge2Sb2Te5, Ge1Sb4Te7 and Sb70Te30 (atomic fraction) were studied. Films were obtained by pulsed laser deposition (PLD) using a pulsed Nd:YAG laser (λ = 355 nm) and they were structurally characterized by X-ray diffraction. Temperature dependence of electrical resistance was studied for these films from room temperature to 520 K at a heating rate about 3 K/min. During crystallization, their electrical resistance falls several orders of magnitude in a narrow temperature range. The electrical conduction activation energies of the amorphous and crystalline states and the crystallization temperature were determined. The crystallization products were characterized by X-ray diffraction. The results were compared with those obtained by other authors.

Due to the appealing piezoelectric, pyroelectric, and ferroelectric (FE) properties, poly(vinylidene fluoride) (PVDF)-based dielectric polymers have been attracting great attention from both the academic and industrial communities. Depending on the molecular structure and the processing method, PVDF-based dielectric polymers can exhibit rich dielectric polarisation behaviours covering normal FE, relaxor FE, anti-FE-like and linear dielectric responses, which enables a wide spectrum of application fields such as non-volatile memories, piezoelectric and pyroelectric sensors, actuators, electrocaloric refrigeration, and film capacitors. In this study, the authors first briefly introduce the current practical/promising applications of PVDF-based dielectric polymers, and the corresponding optimum dielectric polarisation behaviour and crystal structure are proposed accordingly. The chemical synthesis and modification strategies for obtaining various fluoropolymers beyond PVDF homopolymer are then summarised with an emphasis on the relationship between the molecular structure and the dielectric polarisation behaviour. In addition, the effect of processing methods on the crystal structure and dielectric properties of the PVDF-based polymers is discussed. Finally, some newly developed processing techniques applicable to PVDF-based polymers are described.

We consider the transmission and storage of encoded strings of symbols over a noisy channel, where dynamic threshold detection is proposed for achieving resilience against unknown scaling and offset of the received signal. We derive simple rules for dynamically estimating the unknown scale (gain) and offset. The estimates of the actual gain and offset so obtained are used to adjust the threshold levels or to re-scale the received signal within its regular range. Then, the re-scaled signal, brought into its standard range, can be forwarded to the final detection/decoding system, where optimum use can be made of the distance properties of the code by applying, for example, the Chase algorithm. A worked example of a spin-torque transfer magnetic random access memory with an application to an extended (72, 64) Hamming code is described, where the retrieved signal is perturbed by additive Gaussian noise and unknown gain or offset. [ABSTRACT FROM AUTHOR]

Besides the omnipresent noise, other important inconveniences in communication and storage systems are formed by gain and/or offset mismatches. In the prior art, a maximum likelihood (ML) decision criterion has already been developed for Gaussian noise channels suffering from unknown gain and offset mismatches. Here, such criteria are considered for Gaussian noise channels suffering from either an unknown offset or an unknown gain. Furthermore, ML decision criteria are derived when assuming a Gaussian or uniform distribution for the offset in the absence of gain mismatch. [ABSTRACT FROM AUTHOR]

Ferroelectric poly(vinylidene fluoride) (PVDF) based polymers are attracting tremendous interest because of their potential applications in flexible non-volatile memories. Current research suggests that the existence of a large hysteresis loop results in high-voltage operation and low writing/erasing speed, which is originated from uniform chain packing and coherent ferroelectric sequences in the crystalline regions. Here, we demonstrate the novel approach to understand the defect-mediated switching mechanisms in ferroelectric polymers by PFM-probe based technology. The single-point and linear polarization reversal is well controlled by defect-mediated ferroelectric phases that determine activation energy, switching rate, and the thermal stability. By the regulation of VDF/TrFE ratio and varying processing conditions, the coherent ferroelectric phase with all-trans sequence in the P(VDF-TrFE) has been disrupted by defects. Specially, the crystallites formed at high temperature in the copolymer P(VDF-TrFE) 50:50 mol% exhibit less ordered ferroelectric crystalline sequences, thus attaining the excellent features of the low operation voltage of about 4 V with a switching time of 100 ms, ultra-high memory density of 43.9 Gbit∙in −2 (by a 7 V, 1 ms pulse) and a high usage temperature of 60 °C. Compared with P(VDF-TrFE) 68:32 mol%, normal ferroelectric, it saves approximate 50% ratio of energy cost, and realizes four times higher resolution. Understanding and controlling defect functionality in ferroelectric materials is as critical for realizing their reliable applications in ferroelectric memories. [ABSTRACT FROM AUTHOR]