Search

After more than five decades, Moore's Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures. [ABSTRACT FROM AUTHOR]

After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

Design optimization of emerging nanoscale transistor technologies often requires careful design tradeoff between many objectives, including speed, power, variability, and so on. By leveraging machine learning (ML) methods, we develop a multiobjective optimization (MOO) framework for 2-D-material-based field-effect transistors (FETs) near the scaling limit. The MOO design framework performs gradient-free efficient global optimization and offers the option of using active learning. Optimum designs with a tradeoff between transistor speed, power, and variability are identified automatically for transition metal dichalcogenide (TMDC) and black phosphorene FETs by applying the MOO design framework that couples ML methods to quantum transport device simulations. The design optimization results show that the International Roadmap of Devices and Systems (IRDS) target of 2025 and 2028 technology nodes can be met by 2-D FETs. [ABSTRACT FROM AUTHOR]

Despite the large body of research conducted on organic transistors, the transit frequency of organic field‐effect transistors has seen virtually no improvement for a decade and remains far below 1 GHz. One reason is that most of the research is still focused on improving the charge‐carrier mobility, a parameter that has little influence on the transit frequency of short‐channel transistors. By examining the fundamental equations for the transit frequency of field‐effect transistors and by extrapolating recent progress on the relevant device parameters, a roadmap to gigahertz organic transistors is derived. [ABSTRACT FROM AUTHOR]

Due to the significance of electron and heat transfer in designing the nanoscale semiconductor devices, the transient analysis of electrothermal properties has attracted extensive attention. In this paper, the density-gradient and dual-phase-lag (DPL) equations are first combined to predict the electron and heat transport in nanoscale transistors. The DPL equation is solved with the consideration of the temperature jump boundary condition that dealing with phonon–wall collisions. We have shown that the temporal and spatial distributions of related physical variables can be obtained by self-consistently solving these equations. Furthermore, the spectral element time-domain method is used to discretize these equations. Numerical results of electrothermal properties for both 2-D and 3-D field-effect transistors have been demonstrated to show the robustness and universality of the proposed model. Therefore, the model we proposed can be used with the temporal and spatial distributions, which could be helpful for evaluating the electrothermal performance and computational designing of nanoscale transistors. [ABSTRACT FROM AUTHOR]

The quest for developing graphene-based nanoelectronics puts new requirements on the science and technology of device modeling. It also heightens the role of device modeling in the exploration and in the early assessment of technology options. Graphene-based nanoelectronics is the first form of molecular electronics to reach real prominence, and therefore the role of single atoms and of chemical properties acquires more relevance than in the case of bulk semiconductors. In addition, the promising perspectives offered by band engineering of graphene through chemical modifications increase the role of quantum chemistry methods in the assessment of material properties. In this paper, we review the multiphysics multiscale (MS) approaches required to model graphene-based materials and devices, presenting a comprehensive overview of the main physical models providing a quantitative understanding of the operation of nanoscale transistors. We especially focus on the ongoing efforts to consistently connect simulations at different levels of physical abstraction in order to evaluate materials, device, and circuit properties. We discuss various attempts to induce a gap in graphene-based materials and their impact on the operation of different transistor structures. Finally, we compare candidate devices in terms of integrated circuit performance and robustness to process variability. [ABSTRACT FROM PUBLISHER]

Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are the leading reliability concerns for nanoscale transistors. The de facto modeling method to analyze CHC is based on substrate current Isub, which becomes increasingly problematic with technology scaling as various leakage components dominate Isub. In this paper, we present a unified approach that directly predicts the change of key transistor parameters under various process and design conditions for both NBTI and CHC effects. Using the general reaction-diffusion model and the concept of surface potential, the proposed method continuously captures the performance degradation across subthreshold and strong inversion regions. Models are comprehensively verified with an industrial 65-nm technology. By benchmarking the prediction of circuit performance degradation with the measured ring oscillator data and simulations of an amplifier, we demonstrate that the proposed method very well predicts the degradation. For 65-nm technology, NBTI is the dominant reliability concern, and the impact of CHC on circuit performance is relatively small. [ABSTRACT FROM PUBLISHER]