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This paper examines routing algorithms for networks on a chip (NoC). An analysis of existing routing algorithms is provided; their limitations and areas of application are highlighted. The algorithms were evaluated taking into account the requirements of specific applications and architecture features. The results of comparing the performance of the considered algorithms are presented. Analysis and comparison of various routing algorithms for NoC are carried out taking into account critical characteristics. The main attention is paid to such routing algorithms as the deterministic XY algorithm, the model rotation algorithm, congestion-aware routing, fault-tolerant routing, Quality of Service routing, and the ant colony algorithm. It is shown that the choice of routing algorithm should be based on the specific requirements and conditions of use of the network. The importance of adapting to a variety of conditions and tasks that NoC users and developers may encounter is shown. Based on data from existing studies, an analysis of algorithms was carried out based on several key indicators: latency, throughput, adaptability, fault tolerance and implementation complexity. The strengths and weaknesses of each algorithm are identified in various use scenarios and under different network loads. It is shown that the choice of a routing algorithm should be based on the specific requirements and conditions of use of the network, as well as on the balance between performance, adaptability, fault tolerance and implementation complexity. The study contributes to the understanding of the effectiveness of various routing algorithms in NoC, providing recommendations for their selection depending on the specific application requirements and system architecture. The study contributes to a better understanding of the impact of routing algorithms on the overall performance of NoC, suggesting directions for further improvements in this area. The results of the work can be applied in the design and development of highperformance multiprocessor systems on a chip where efficient data routing between various systems components is a key factor in ensuring high performance. The importance of developing fault-tolerant routing algorithms that can ensure the continuity of system operation in the event of failures of individual components or units is emphasized. This is especially important for mission-critical applications where service continuity and reducing the risk of data loss are top priorities.

Particle trajectory and collision simulation is a critical step of the design and construction of novel particle accelerator components. However it requires a huge computational effort which can slow down the design process. We started from a sequential simulation program which is used to study an event called Multipacting. Our work explains the physical problem that is simulated and the implications it can have on the behavior of the components. Then we analyze the original program's operation to find the best options for parallelization. We first developed a parallel version of the Multipacting simulation and were able to accelerate the execution up to ∼ 35 × with 48 or 56 cores. In the best cases, parallelization efficiency was maintained up to 16 cores ( ∼ 95 %) and the speed-up plateaus at around 40–48 cores. When this first parallelization effort was tried for multi-power simulations, we found that parallelism was severely limited with a maximum of 20 × speed-up. For this reason, we introduced a new method to improve the parallelization efficiency for this second use case. This method uses a shared processor pool for all simulations of electrons (OnePool). OnePool improved scalability by pushing the speed-up to over 32 × . [ABSTRACT FROM AUTHOR]

In the scheduling of hard real-time systems on multicore platforms, significant unpredictability arises from interference caused by shared hardware resources. The objective of this paper is to offer a schedulability analysis for such systems by assuming a general model that introduces interference as a time parameter for each task. The analysis assumes constrained deadlines and is provided for fixed priorities. It is based on worst-case response time analysis, which exists in the literature for monocore systems. We demonstrate that the worst-case response time is an upper bound, and we evaluate our proposal with synthetic loads and execution on a real platform. [ABSTRACT FROM AUTHOR]

Modern multi-processor systems-on-chip (MPSoCs) are characterized by caches shared by multiple cores. These shared caches receive requests issued by the processor cores. Requests that are subject to cache misses may result in the generation of responses. These responses are received from the lower level of the memory hierarchy and written to the cache. The outstanding requests and responses contend for the shared cache bandwidth. To mitigate the impact of the cache bandwidth contention on the overall system performance, an efficient request and response arbitration policy is needed. Research on shared cache management has neglected the additional cache contention caused by responses, which are written to the cache. We propose CABARRE, a novel request and response arbitration policy at shared caches, so as to improve the overall system performance. CABARRE shows a performance improvement of 23% on average across a set of SPEC workloads compared to straightforward adaptations of state-ofthe- art solutions. [ABSTRACT FROM AUTHOR]

In the scheduling of hard real-time systems on multicore platforms, significant unpredictability arises from interference caused by shared hardware resources. The objective of this paper is to offer a schedulability analysis for such systems by assuming a general model that introduces interference as a time parameter for each task. The analysis assumes constrained deadlines and is provided for fixed priorities. It is based on worst-case response time analysis, which exists in the literature for monocore systems. We demonstrate that the worst-case response time is an upper bound, and we evaluate our proposal with synthetic loads and execution on a real platform.

Summary: Selection from several computer systems with different hardware features resulting in different software performance is a critical problem to solve. The problem becomes even more challenging when access to computer systems with different features is difficult. We had proposed a novel solution, "cross performance prediction with scaling," in our previous work. In the scaling model, we predicted the physical system's runtime using a machine learning model trained only on a performance dataset of simulation‐based systems applying a scaling factor to the predicted runtime. In this article, we propose another novel idea, "cross performance prediction with transfer learning," that uses transfer learning to solve the same problem. This model predicts the target physical system's performance using a machine learning model trained on a combined performance dataset from simulation‐based systems and an accessible source physical system. We evaluate both the models using several benchmark algorithms from SD‐VBS and MiBench suites. Our scaling model results have achieved a prediction error of 10%–25% for general‐purpose systems, whereas the transfer learning model has higher errors in the range of 50%. We have also developed a method to extract the rules built during the decision tree model's training to predict the runtime. [ABSTRACT FROM AUTHOR]

Multicore systems integrated with hardware accelerators provide better performance for executing real-time applications in time-critical fields, such as robots, avionics, and aerospace. The integration of hardware accelerators brings new challenges for system scheduling; the software scheduling problem is extended to a hardware–software co-scheduling problem. Efficient co-scheduling strategy maximizes the benefits of hardware acceleration, which is important for time-critical systems. To solve this problem, we propose a co-scheduling strategy to minimize the system execution time. It combines hardware–software resource allocation and a real-time schedule method. Our scheduling can fit the different parallel in software and hardware (e.g., CPUs and FPGAs). The key component of our strategy is its novel hardware–software resource allocation and a high-performance heuristic scheduling algorithm. In the experiments, we evaluate our approach using both simulated and real parallel applications. The results illustrate that our algorithm obtains efficient solutions within reasonable runtimes compared to the state of the art. [ABSTRACT FROM AUTHOR]

Software application when executed on computer systems having disparate hardware features, result in dissimilar performance and power. Therefore, selecting systems with optimal performance and power values for application execution is an essential problem to address. However, access to many physical systems is required to collect performance power, which is a demanding task. Therefore, our first objective is to build an accurate prediction model for physical systems to achieve the second objective of computer system selection. To achieve the first objective, we propose a novel model, "cross performance and power prediction with scaling." We develop a cross prediction model for physical systems by training a decision tree machine learning algorithm on performance and power datasets obtained from a large number of simulation systems built in the Gem5 simulator using emulation mode. However, design differences between Gem5 systems and physical systems lead to large prediction inaccuracies. We determine the application-specific "scaling factor" to compensate for the prediction inaccuracies and apply it to the predicted values for accurate physical systems predictions. We evaluate our model on well-known applications from SD-VBS and MiBench benchmarks achieving errors of 10–25% and 6–40% for performance and power for general-purpose systems. With accurate predictions for physical systems from our model, we achieve the second goal of computer system selection. [ABSTRACT FROM AUTHOR]

The RSA (Rivest–Shamir–Adleman) asymmetric-key cryptosystem is widely used for encryptions and digital signatures. Let (n , e) be the RSA public key and d be the corresponding private key (or private exponent). One of the attacks on RSA is to find the private key d using continued fractions when d is small. In this paper, we present a new technique to improve a small private exponent attack on RSA using continued fractions and multicore systems. The idea of the proposed technique is to find an interval that contains ϕ (n) , and then propose a method to generate different points in the interval that can be used by continued fraction and multicore systems to recover the private key, where ϕ is Euler's totient function. The practical results of three small private exponent attacks on RSA show that we extended the previous bound of the private key that is discovered by continued fractions. When n is 1024 bits, we used 20 cores to extend the bound of d by 0.016 for de Weger, Maitra-Sarkar, and Nassr et al. attacks in average times 7.67 h, 2.7 h, and 44 min, respectively. [ABSTRACT FROM AUTHOR]

This article studies the model predictive control (MPC) for a twisted buck–boost inverter based on unfolding circuit. The focus is on the practical implementation of the MPC algorithm for the microcontroller designed for application in power electronics. Selection of proper cost function parameters along with a continuous control set reduced prediction horizon, at the same time keeping good quality of the grid current. The results showed that simplified differential equations and a multicore microcontroller contribute to the sample time reduction, which in turn increases the sampling frequency with the corresponding increase in the output current quality. The simulation and experimental results confirmed theoretical predictions. In conclusion, the MPC technique suits for reducing zero-crossing distortion and in applications based on unfolding circuit. [ABSTRACT FROM AUTHOR]

The RSA (Rivest–Shamir–Adleman) asymmetric-key cryptosystem is widely used for encryptions and digital signatures. Let (n,e) be the RSA public key and d be the corresponding private key (or private exponent). One of the attacks on RSA is to find the private key d using continued fractions when d is small. In this paper, we present a new technique to improve a small private exponent attack on RSA using continued fractions and multicore systems. The idea of the proposed technique is to find an interval that contains ϕ(n), and then propose a method to generate different points in the interval that can be used by continued fraction and multicore systems to recover the private key, where ϕ is Euler’s totient function. The practical results of three small private exponent attacks on RSA show that we extended the previous bound of the private key that is discovered by continued fractions. When n is 1024 bits, we used 20 cores to extend the bound of d by 0.016 for de Weger, Maitra-Sarkar, and Nassr et al. attacks in average times 7.67 h, 2.7 h, and 44 min, respectively.

This paper was motivated by the two open research challenges in the area of STMs. The first challenge is the development of STM based concurrent queues, whereas the second, maybe even greater, challenge is the development of distributed STMs. Python is assumed as a target language. In this paper, four main contributions are made. First, the concurrent queue data structure on the local Python STM is developed. Second, a distributed STM in Python, called Distributed Python STM, is developed. Third, the developed concurrent queue is ported on the Distributed Python STM. Fourth, the developed concurrent queue is verified using unit and system testing. The developed concurrent queue successfully passed all of the unit and the system tests on both local Python STM and Distributed Python STM.

In this paper we present meta-heuristics to solve the energy aware reward based scheduling of real-time tasks with mandatory and optional parts in homogeneous multi-core processors. The problem is NP-Hard. An objective function to maximize the performance of the system considering the execution of optional parts, the benefits of slowing down the processor and a penalty for changing the operation power-mode is introduced together with a set of constraints that guarantee the real-time performance of the system. The meta-heuristics are the bio-inspired methods Particle Swarm Optimization and Genetic Algorithm. Experiments are made to evaluate the proposed algorithms using a set of synthetic systems of tasks. As these have been used previously with an Integer Lineal Programming approach, the results are compared and show that the solutions obtained with bio-inspired methods are within the Pareto frontier and obtained in less time. Finally, precedence related tasks systems are analyzed and the meta-heuristics proposed are extended to solve also this kind of systems. The evaluation is made by solving a traditional example of the real-time precedence related tasks systems on multiprocessors. The solutions obtained through the methods proposed in this paper are good and show that the methods are competitive. In all cases, the solutions are similar to the ones provided by other methods but obtained in less time and with fewer iterations.

Synchronous dataflow graphs are widely used tomodel digital signal processing andmultimedia applications. Self-timed execution is an efficient methodology for the analysis and scheduling of synchronous dataflow graphs. In this article, we propose a communication-aware self-timed execution approach to solve the problem of scheduling synchronous dataflow graphs on multicore systems with communication delays. Based on this communication-aware self-timed execution approach, four communication-aware scheduling algorithms are proposed using different allocation rules. Furthermore, a code-size-aware mapping heuristic is proposed and jointly used with a proposed scheduling algorithm to reduce the code size of SDFGs on multicore systems. The proposed scheduling algorithms are experimentally evaluated and found to perform better than existing algorithms in terms of throughput and runtime for several applications. The experiments also show that the proposed code-size-aware mapping approach can achieve significant code size reduction with limited throughput degradation in most cases. [ABSTRACT FROM AUTHOR]

The application workloads in modern multicore platforms are becoming increasingly dynamic. It becomes challenging when multiple applications need to be executed in parallel in such systems. Mapping and scheduling of these applications are critical for system performance and energy consumption, especially in Networkon-Chip– (NoC) based multicore systems. These systems with multitasking processors offer a better opportunity for parallel application execution. Mapping solutions generated at design time may be inappropriate for dynamic workloads. To improve the utilization of the underlying multicore platform and cope with the dynamism of application workload, often task allocation is carried out dynamically. This article presents a hybrid task allocation and scheduling strategy that exploits the design-time results at runtime. By considering the multitasking capability of the processors, communication energy, and timing characteristics of the tasks, different allocation options are obtained at design time. During runtime, based on the availability of the platform resources and application requirements, the design-time allocations are adapted for mapping and scheduling of tasks, which result in improved runtime performance. Experimental results demonstrate that the proposed approach achieves an on average 11.5%, 22.3%, 28.6%, and 34.6% reduction in communication energy consumption as compared to CAM [18], DEAMS [4], TSMM [38], and CPNN [32], respectively, for NoC-based multicore platforms with multitasking processors. Also, the deadline satisfaction of the tasks of allocated applications improves on an average by 32.8% when compared with the state-of-the-art dynamic resource allocation approaches. [ABSTRACT FROM AUTHOR]

Taking advantage of multicore architectures can provide significant improvement for many design automation problems. However, the parallelization procedure introduces challenges, such as workload duplication, limited search space exploration, and race contention among different threads. In this article, we propose a parallel framework for automatic test pattern generation using shared memory multicore systems that support test generation (TG) for both single-detect and multiple-detect fault models. The framework follows a two-epoch approach, each focusing on a different category of faults, during which a test seed generation is followed by compatibility merging. Various optimization techniques are incorporated in each epoch, designed to achieve higher speedup for the overall TG procedure without impacting much the test set size. A cluster-based approach is also presented, extending the proposed framework to consider multiple-detect fault models without affecting its efficiency. The obtained experimental results demonstrate increased speedup rates compared with the state-of-the-art multicore-based tools while, at the same time, the test inflation problem is restrained. For the multiple-detect extension, these properties are maintained despite the increased workload and the additional constraint of retaining the number of detections for each fault while merging. [ABSTRACT FROM AUTHOR]

Due to the high integration density and roadblock of voltage scaling, modern multicore processors experience higher power densities than previous technology scaling nodes. When unattended, this issue might lead to temperature hot spots, that in turn may cause nonuniform aging, accelerate chip failure, impair reliability, and reduce the performance of the system. This paper presents an overview of several research efforts that propose to use machine learning (ML) techniques for power and thermal management on single-core and multicore processors. Traditional power and thermal management techniques rely on a certain a-priori knowledge of the chip’s thermal model, as well as information of the workloads/applications to be executed (e.g., transient and average power consumption). Nevertheless, these a-priori information is not always available, and even if it is, it cannot reflect the spatial and temporal uncertainties and variations that come from the environment, the hardware, or from the workloads/applications. Contrarily, techniques based on ML can potentially adapt to varying system conditions and workloads, learning from past events in order to improve themselves as the environment changes, resulting in improved management decisions. [ABSTRACT FROM AUTHOR]

Spin-Transfer Torque RAM (STT-RAM) is widely considered a promising alternative to SRAM in the memory hierarchy due to STT-RAM's non-volatility, low leakage power, high density, and fast read speed. The STT-RAM's small feature size is particularly desirable for the last-level cache (LLC), which typically consumes a large area of silicon die. However, long write latency and high write energy still remain challenges of implementing STT-RAMs in the CPU cache. An increasingly popular method for addressing this challenge involves trading off the non-volatility for reduced write speed and write energy by relaxing the STT-RAM's data retention time. However, in order to maximize energy saving potential, the cache configurations, including STT-RAM's retention time, must be dynamically adapted to executing applications' variable memory needs. In this paper, we propose a highly adaptable last level STT-RAM cache (HALLS) that allows the LLC configurations and retention time to be adapted to applications' runtime execution requirements. We also propose low-overhead runtime tuning algorithms to dynamically determine the best (lowest energy) cache configurations and retention times for executing applications. Compared to prior work, HALLS reduced the average energy consumption by 60.57 percent in a quad-core system, while introducing marginal latency overhead. [ABSTRACT FROM AUTHOR]

Technology scaling has enabled integration of a large number of intellectual property cores, memory units and processing elements on a single chip. This has led to the evolution of multicore systems. In recent years, these systems have gained popularity as execution platforms for real-time applications. However, due to the close spacing of the cores and uneven heat dissipation among the processors of the multicore platform, thermal hotspots are formed. Ensuring thermal safety in real-time systems is a challenging task, especially when various applications are executed with different timing constraints. In real-time dynamic systems, applications unknown at design-time, are submitted by users at runtime. In order to perform on-the-fly task assignment to the processors of the multicore platform, different dynamic resource allocation approaches are reported in the literature. However, most of the dynamic task allocation approaches lack in thermal awareness and do not consider thermal safety of the chip. Also, most of the existing thermal-aware task mapping methods rely on offline thermal analysis which is either unavailable in dynamic scenarios or is computationally too expensive for providing end-to-end thermal-aware solution at runtime. In this work, we propose an improved algorithm for dynamic thermal-aware task mapping and scheduling using a non-profiling based strategy for NoC based multi-core systems. By using a combination of threshold based thermal management scheme and dynamic task (re)allocation, the proposed thermal-aware approach helps to maintain the thermal safety of the chip. Simulation results demonstrate that the proposed algorithm achieves 25.3% and 45.6% reduction in chip peak temperature compared to recent dynamic task allocation approaches ATM [1] and DEAMS [2] respectively. Also, the proposed thermal-aware strategy satisfies the task deadline while reducing the average packet delay of the allocated applications. When compared to other thermal-aware methods such as ATM [1] and TAPP [3], the proposed strategy improves the deadline satisfaction of the tasks by 37.8% and 67.3% respectively. [ABSTRACT FROM AUTHOR]

Current and future multicore architectures can significantly accelerate the performance of test automation procedures depending on the underlying architecture and the scalability of their algorithms. This paper proposes a new parallel methodology targeting the fault simulation problem, for shared memory multicore systems, that maintains scalability with the increase of the number of cores. The method is based on a simple single thread process that allows focusing on the optimization of the parallelization process in different dimensions. Additionally, a number of optimizations are incorporated in the approach to control fault dropping and to avoid unnecessary work. The reported experimental results, for both random and deterministic test sets, demonstrate the scalability of the method. As the number of cores increases, the reported speed-up increases proportionally, where comparable recent methods report saturation or even reduction of the obtained speed-up. [ABSTRACT FROM AUTHOR]

Rapid advancement in deep sub-micron regime has made the integration of multiple processing elements possible on a single chip. This has enabled parallel execution of applications on Network-on-Chip (NoC) based multiprocessor platforms. Task mapping and scheduling play crucial roles in timing response and energy consumption of such systems. Tasks present in these applications can be of mixed critical in nature with different importance. However, the on-chip processors executing these tasks of any given application might fail during runtime. Fault tolerance becomes challenging when real-time applications with mixed critical requirements are hosted on such fault prone environment. The complexity of the problem is further magnified in dynamic scenarios when such real-time applications can enter or leave the multicore platform at any time instant. Although several prior works have addressed fault tolerant resource allocation for mixed critical applications, few of these consider permanent processor faults. In this work, an improved fault tolerant resource allocation strategy is presented to mitigate the effect of permanent processor faults on mixed critical applications. The proposed algorithm offers a runtime solution to the unified problem of fault tolerant mapping and scheduling for real-time applications. Both the temporal property of the tasks and the timing information of the faults have been considered while implementing a suitable fault tolerance strategy that reduces the communication energy consumption and provides an improved level of quality of service for the executing applications. A detailed evaluation of the performance of the proposed algorithm has been conducted for different applications. On comparing with other state-of-the-art fault tolerant approaches, the proposed policy shows 28.5% average reduction in communication energy consumption while achieving 34.7% improved quality of service. Additionally, the proposed scheme shows better scalability in comparison to the recent techniques reported in literature. [ABSTRACT FROM AUTHOR]

Abstract Hybrid Wireless Network on Chip (WNoC) architecture has been proposed as a promising solution for addressing on-chip communication problems in many multicore systems. The choice of infrastructure topology directly affects the performance gain of the architecture. For exploiting the benefits offered by both mesh and tree topologies, we employ Mesh-of-Tree (MoT) topology as a new communication infrastructure for hybrid WNoC architectures. Moreover, long-distance links are effectively added to the MoT topology to form wireless MoT architecture and an appropriate communication routing scheme is presented to employ this paradigm. The performance and the system cost of the proposed WNoC architecture have been evaluated and compared with other notable WNoC architectures through comprehensive network-level simulations. Experimental results demonstrate the effectiveness of this wireless MoT architecture under both synthetic and realistic traffic patterns in terms of network throughput, latency, and power consumption. The results demonstrate that the proposed architecture can approximately achieve 35% improvement in saturation throughput, 58% reduction in transmission latency, and 43% improvement in power consumption over a wireline MoT-NoC, on average. Highlights • We propose a novel Mesh-of-Tree WNoC architecture for multicore systems. • We introduce an effective wireless MAC and routing mechanisms for the proposed architecture. • We conduct a series of experiments to evaluate the MoT topology for WNoC architectures. • The proposed MoT-WNoC architecture provides an efficient backbone for multicore systems. [ABSTRACT FROM AUTHOR]

Purpose: The purpose of this study was to present a parallel solution for the EGSnrc Monte Carlo code system combining MPI and OpenMP programming models as an alternative to the provided implementation, based on the use of a batch‐queueing system (BQS). Methods: Relying on a previous implementation based on OpenMP by E. Doerner and P. Caprile [Med. Phys. 44, 6672 (2017)], this work incorporates MPI features to efficiently distribute the simulation on current high‐performance computing (HPC) systems. These features are introduced through properly defined macros, which are enabled depending on the compilation flags given by the user. The presented solution was benchmarked using the DOSXYZnrc code for a 6 MV clinical photon beam impinging on an homogeneous water phantom. Results: The platform validation against the serial run results confirmed that the introduction of new features does not modify the final dose distribution. The performance tests indicated that the new implementation was able to handle efficiently the workload distribution among the computing units available. Using all the resources available, the hybrid simulation was 10% faster than the MPI only solution and 30% faster than the BQS implementation. Conclusions: The hybrid method presented is a viable solution to parallelize MC simulations using the EGSnrc codes in distributed computing systems in an simple and efficient way, taking advantage of the available resources and giving the user the possibility of choosing between different parallelization schemes (only OpenMP/MPI or a combination of both). [ABSTRACT FROM AUTHOR]

In mixed-criticality (MC) systems, multiple activities with various certification requirements (thus with different criticality levels) can co-exist on shared hardware platforms, where multicore processors have emerged as the de facto computing engines. In this paper, by using the partitioned earliest-deadline-first with virtual deadlines (EDF-VDs) scheduler for a set of periodic MC tasks running on multicore systems, we derive a criticality-aware utilization bound for efficient feasibility tests and then identify its characteristics. Our analysis shows that the bound increases with increasing number of cores and decreasing system criticality level. We show that, since the utilizations of MC tasks at different criticality levels can vary considerably, the utilization contribution of a task on different cores may have large variations and thus can significantly affect the system schedulability under the EDF-VD scheduler. Based on these observations, we propose a novel and efficient criticality-aware task partitioning algorithm (CA-TPA) to compensate for the inherent pessimism of the utilization bound. In order to improve the system schedulability, the task priorities are determined according to their utilization contributions to the system in CA-TPA. Moreover, by analyzing the utilization variations of tasks at different levels, we develop several heuristics to minimize the utilization increment and balance the workload on cores. The simulation results show that the CA-TPA scheme is very effective in achieving higher schedulability ratio and yielding balanced workloads. The actual implementation in Linux operating system further demonstrates the applicability of CA-TPA with lower run-time overhead, compared to the existing partitioning schemes. [ABSTRACT FROM PUBLISHER]

Device scaling, increasing number of components in a single chip, varying environmental issues, and aging effects have brought severe reliability challenges that impose tight constraints on the operation of a system. To cope with these challenges, this paper proposes a reliability-aware scheduling framework that combines static and dynamic analyses to improve the overall system resiliency to different kinds of faults (i.e., intermittent, transient, and permanent). The static analysis technique employs genetic algorithms to optimize the overall system reliability by considering reliability level (RL) as an intermediate scheduling dimension and creating a task-to-RL mapping. This enables the RL-to-core mapping to be efficiently adapted at runtime according to fault rate variations, while the task-to-RL mapping can still be reused. The dynamic analysis tracks faults appearing in each core and measures the time correlation of those faults to update the RL-to-core mapping. The proposed reliability-aware framework is implemented in a state-of-the-art runtime system, Delaware Adaptive Run-Time System, so as to quantitatively show the advantages of using the overall framework in existing multicore platforms. Experimental results show that the proposed technique delivers up to 30% improvement in application execution time and up to 72% improvement in faults occurring at runtime. [ABSTRACT FROM PUBLISHER]

Purpose To present the implementation of a new option for parallel processing of the EGSnrc Monte Carlo system using the OpenMP API, as an alternative to the provided method based on the use of a batch queuing system (BQS). Methods The parallel solution presented, called OMP_EGS, makes use of OpenMP features to control the workload distribution between the compute units. These features were inserted into the original EGSnrc source code through properly defined macros. In order to validate the platform, the possibility of producing results in exact agreement with the serial implementation was assessed. The performance of OMP_EGS was evaluated against the BQS method, in terms of parallel speedup and efficiency. Results As the OpenMP features can be activated or deactivated depending on the compilation options, the implementation of the platform allowed the direct recovery of the original serial implementation. The validation tests showed that OMP_EGS was able to reproduce the exact same results as the serial implementation. The performance and scalability tests showed that OMP_EGS is a better alternative than the EGSnrc BQS parallel implementation, both in terms of runtime and parallel efficiency. Conclusions The presented solution has several advantages over the BQS-based parallel implementation available for the EGSnrc system. One of the main advantages is that, in contrast to the BQS alternative, it can be implemented using different compilers and operative systems, which turns it into a compact and portable solution that can be used on a wide range of working environments. It does not introduce artifacts on the simulated distributions, as it only handles the distribution of work among the available computing resources and it proved to have a better performance. [ABSTRACT FROM AUTHOR]

Energy and temperature are the main constraints for modern high-performance multicore systems. To save power or increase performance, dynamic voltage and frequency scaling (DVFS) is widely applied in literally all computing systems. As CMOS technology continues scaling, FinFET has recently become the common choice for multicore systems. In contrast with planar CMOS, FinFET is characterized by lower delay under higher temperatures in super-threshold voltage region, an effect called temperature effect inversion (TEI). This paper explores TEI-aware performance improvement and energy savings for multicore systems. Our experimental results show that on average 15.70% throughput improvement or 31.26% energy savings can be achieved in steady state by a TEI-aware DVFS policy over a TEI-agnostic one. By further investigation, multiple sweet spots (SSs) resulting from TEI effects are observed. Based on these SS operation regimes, this paper introduces fast algorithms which provide iso-power maximum performance or iso-performance minimum energy consumption. Experimental results confirm the effectiveness of the proposed approach by exhibiting a $45.9 \times $ – $55.3 \times $ speedup when compared to state-of-the-art algorithms while losing only 0.22% or 0.68% in achieved performance or energy, respectively. [ABSTRACT FROM PUBLISHER]

The ITER neutral beam test facility, currently under the construction at Padua, Italy, consists of two experiments: source for production of ions of deuterium extracted (SPIDER) to test the ITER size ion source and megavolt iter injector and concept advancement (MITICA) to test the full ITER neutral beam injector. While the former represents an intermediate step, also finalized to the ITER Diagnostic Neutral Beam, the latter will represent the final design and implementation of the full prototype of the ITER heating neutral beam (HNB) injectors. Consequently, for the control and data acquisition system (CODAS) of SPIDER, there are no requirements for compliance with ITER, whereas the MITICA HNB Plant System will comply with the ITER directives for plant instrumentation and control because final system will be eventually integrated in ITER. SPIDER CODAS is currently under commissioning and the integration of the different frameworks that operate in an integrated way is proven to be successful. The experience and solutions gained in SPIDER CODAS development will be reused as far as possible in MITICA and to provide at the same time the required ITER plant system compatibility, a set of ITER-like layers (networks) will be defined, using exactly the same protocol defined for ITER interfaces. [ABSTRACT FROM PUBLISHER]

Community detection is a demanded technique in analyzing complex and massive graph-based networks. The quality of the detected communities in an acceptable time is an important aspect of an algorithm, which aims at passing through an ultra large scale graph, for instance a social network graph. In this paper, an efficient method is proposed to tackle Louvain community detection problem on multicore systems in the line of thread-level parallelization. The main contribution of this article is to present an adaptive parallel thread assignment for the calculation of adding qualified neighbor nodes to the community. This leads to obtain a better load balancing method for the execution of threads. The proposed method is evaluated on an AMD system with 64 cores, and can reduce the execution time by 50% in comparison with the previous fastest parallel algorithms. Moreover, it was observed in the course of the experiments that our method could find comparably qualified communities. [ABSTRACT FROM AUTHOR]

The multicore revolution is having limited impact in safety-critical application domains. A key reason is the 'one-out-of- m' problem: when validating real-time constraints on an m-core platform, excessive analysis pessimism can effectively negate the processing capacity of the additional $$m-1$$ cores so that only 'one core's worth' of capacity is utilized even though m cores are available. Two approaches have been investigated previously to address this problem: mixed-criticality allocation techniques, which provision less-critical software components less pessimistically, and hardware-management techniques, which make the underlying platform itself more predictable. A better way forward may be to combine both approaches, but to show this, fundamentally new criticality-cognizant hardware-management tradeoffs must be explored. Such tradeoffs are investigated herein in the context of a new variant of a mixed-criticality framework, called $$\textsf {MC}^\textsf {2} $$ , that supports configurable criticality-based hardware management. This framework allows specific DRAM memory banks and areas of the last-level cache (LLC) to be allocated to certain groups of tasks. A linear-programming-based optimization framework is presented for sizing such LLC areas, subject to conditions for ensuring $$\textsf {MC}^\textsf {2} $$ schedulability. The effectiveness of the overall framework in resolving hardware-management and scheduling tradeoffs is investigated in the context of a large-scale overhead-aware schedulability study. This study was guided by extensive trace data obtained by executing benchmark programs on the new variant of $$\textsf {MC}^\textsf {2} $$ presented herein. This study shows that mixed-criticality allocation and hardware-management techniques can be much more effective when applied together instead of alone. [ABSTRACT FROM AUTHOR]