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A novel dual mode logic (DML) model has a superior energy-performance compare to CMOS logic. The DML model has unique feature that allows switching between both modes of operation as per the real-time system requirements. The DML functions in two dissimilar modes (static and dynamic) of operation with its specific features, to selectively obtain either low-energy or high-performance. The sub-threshold region DML achieves minimum-energy. However, sub-threshold region consequence in performance is enormous. In this paper, the working of DML model in the moderate inversion region has been explored. The near-threshold region holds much of the energy saving of subthreshold designs, along with improved performance. Furthermore, robustness to supply voltage and sensitivity to the process temperature variations are presented. Monte carol analysis shows that the projected near-threshold region has minimum energy along with the moderate performance.

In this work we propose an optimal back plane biasing (OBB) scheme to be used in a UTBB FD SOI technology that minimizes the energy per operation consumption of sub threshold digital CMOS circuits. By using this OBB scheme, simulations show that more than 30% energy savings can be obtained with low threshold voltage (LVT) devices in comparison with classic symmetric back plane biasing (SBB) schemes. Additionally, this OBB scheme allows to adjust the performance of the circuit with very small energy penalties. A very simple and intuitive model, for sub threshold digital CMOS circuits, was developed to justify the benefits obtained by OBB. The results predicted by the model are confirmed with extensive simulation results. We show that the OBB approach can be applied easily to a given circuit just based on the information provided by a logic simulation of the circuit (or even an analysis of its structure) and simple electrical simulations of the pMOS and nMOS transistors. Finally, we show that the variability in the energy consumption is improved by using OBB and suggests that new sizing methodologies must be studied to fully benefit from the wide back plane voltage range available in UTBB FD SOI technology for the design of robust energy efficient digital circuits. • This work presents a novel back plane biasing scheme (OBB). • The OBB scheme reduces energy consumption of sub/near threshold digital designs. • Modeling the impact of NMOS and PMOS imbalance in energy per operation consumption. • We show there is an optimum imbalance that minimizes energy consumption. • OBB consists on using the back plane voltage to work in this optimum. • Circuits simulations show more than 30% energy reductions in the studied circuits. [ABSTRACT FROM AUTHOR]

The design of ultra-low-voltage microcontroller (MCU) systems with high energy-efficiency operations is a key concept to achieve fully autonomous energy-harvesting powered Internet-of-Things applications. In this paper, a system-on-chip (SoC) is presented, embedding an ARM® Cortex®-M0+ MCU, $2 \times 4$ KB SRAM, an ultra-low power frequency synthesizer, a custom power switch, and a power management unit enabling the active and sleep modes. The 28 nm fully depleted silicon-on-insulator (FD-SOI) technology has been used to fabricate the device. The whole system operates at a fixed voltage of 0.5 V, and can switch from active and sleep/deep sleep modes, adjusting its frequency from 16 to 8 MHz or 32 kHz in one cycle upon energy availability. Silicon measurements report an SoC’s power consumption of 2.7 pJ/cycle at 16 MHz during active mode, and a total power consumption of 0.7 $\mu \text{W}$ during deep sleep mode. By combining frequency and power modes switching with extra reverse body-biasing, the system power consumption is drastically reduced by $2\times $ and $61\times $ in, respectively, sleep and deep sleep modes. [ABSTRACT FROM AUTHOR]

Energy consumption is a key issue in portable biomedical devices that require uninterrupted biomedical data processing. As the battery life is critical for the user, these devices impose stringent energy constraints on SRAMs and other system on chip (SoC) components. Prior work shows that operating CMOS circuits at subthreshold supply voltages minimizes energy per operation. However, at subthreshold voltages, SRAM bitcells are sensitive to device variations, and conventional 6T SRAM bitcell is highly vulnerable to readability related errors in subthreshold operation due to lower read static noise margin (RSNM) and half-select issue problems. There are many robust subthreshold bitcells proposed in the literature that have some improvements in RSNM, write static noise margin (WSNM), leakage current, dynamic energy, and other metrics. In this paper, we compare our proposed bitcell with the state of the art subthreshold bitcells across various SRAM design knobs and show their trade-offs in a column mux scenario from the energy and delay metrics and the energy per operation metric standpoint. Our 9T half-select-free subthreshold bitcell has 2.05× lower mean read energy, 1.12× lower mean write energy, and 1.28× lower mean leakage current than conventional 8T bitcells at the TT_0.4V_27C corner. Our bitcell also supports the bitline interleaving technique that can cope with soft errors.

Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the operation at the minimum energy point (MEP) is effective for ULP CMOS circuits, its slow operation speed often means that it is not used in many applications. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for the ultralow-power (ULP) electronics because of its small variability and back-bias control. Proper power and performance optimization with adaptive Vth control taking advantage of SOTB’s features can achieve the ULP operation with acceptably high speed and low leakage. This paper describes our results on the ULV operation of logic circuits (CPU, SRAM, ring oscillator and other logic circuits) and shows that the operation speed is now sufficiently high for many ULP applications. The “Perpetuum-Mobile” micro-controllers operating down to 0.4 V or lower are expected to be implemented in a huge number of electronic devices in the internet-of-things (IoT) era.

Circuits operating in the subthreshold region are synonymous to low energy operation. However, the penalty in performance is colossal. In this paper, we investigate how designing in moderate inversion region recuperates some of that lost performance, while remaining very near to the minimum energy point. An α power based minimum energy delay modeling that is continuous over the weak, moderate, and strong inversion regions is presented. The value of α is obtained through interpolation following EKV model. The effect of supply voltage and device sizing on the minimum energy and performance is determined. The proposed model is utilized to design a temperature to time generator at 32nm technology node as the application of the proposed model. The abstract goes here. [ABSTRACT FROM AUTHOR]

Ultra-low voltage operation is key to achieving energy-efficient operation for microcontroller (MCU) systems. Variation resiliency, high speed operation, and short design time are the most important challenges for these systems. This paper overcomes these challenges in a new design strategy that enables standard cell design with differential transmission gate logic. The commercial toolchain is extended with in-house developed add-ons and makes use of two custom libraries with different device lengths to allow high speed vs. low leakage trade-offs. The design flow is used to prototype two highly efficient 32-bit ARM Cortex-M0 MCU systems in 40-nm CMOS. The core of the first prototype scales down to 190 mV and 0.8-MHz and reaches 16.07 pJ/cycle at 31.2-MHz and 440 mV. The second prototype benefits from the dual libraries and reduces core energy consumption by 50% at the same speed performance. Minimum energy operation is thus achieved at an even lower voltage (370 mV) with the M0 core consuming only 8.80 pJ/cycle at 13.7-MHz, breaking the sub-10-pJ/cycle barrier for a 6–35-MHz range. [ABSTRACT FROM AUTHOR]

To achieve energy efficiency in the Internet-of-Things (IoT), more intelligence is required in the wireless IoT nodes. Otherwise, the energy required by the wireless communication of raw sensor data will prohibit battery lifetime, the backbone of IoT. One option to achive this intelligence is to implement a variety of machine learning algorithms on the IoT sensor instead of the cloud. Shown here is sub-milliwatt machine learning accelerator operating at the Ultra-Low Voltage Minimum-Energy Point. The accelerator is a Transport Triggered Architecture (TTA) Application-Specific Instruction-Set Processor (ASIP) targeted for running various Machine Learning algorithms. The ASIP is implemented in 28 nm FDSOI (Fully Depleted Silicon On Insulator) CMOS process, with an operating voltage of 0.35 V, and is capable of 5.3pJ/cycle and 1.8nJ/iteration when performing conventional machine learning algorithms. The ASIP also includes hardware and compiler support for approximate computing. With the machine learning algorithms, computing approximately brings a maximum of 4.7% energy savings. [ABSTRACT FROM AUTHOR]

Energy consumption is a key issue in portable biomedical devices that require uninterrupted biomedical data processing. As the battery life is critical for the user, these devices impose stringent energy constraints on SRAMs and other system on chip (SoC) components. Prior work shows that operating CMOS circuits at subthreshold supply voltages minimizes energy per operation. However, at subthreshold voltages, SRAM bitcells are sensitive to device variations, and conventional 6T SRAM bitcell is highly vulnerable to readability related errors in subthreshold operation due to lower read static noise margin (RSNM) and half-select issue problems. There are many robust subthreshold bitcells proposed in the literature that have some improvements in RSNM, write static noise margin (WSNM), leakage current, dynamic energy, and other metrics. In this paper, we compare our proposed bitcell with the state of the art subthreshold bitcells across various SRAM design knobs and show their trade-offs in a column mux scenario from the energy and delay metrics and the energy per operation metric standpoint. Our 9T half-select-free subthreshold bitcell has 2.05x lower mean read energy, 1.12x lower mean write energy, and 1.28x lower mean leakage current than conventional 8T bitcells at the TT_0.4V_27C corner. Our bitcell also supports the bitline interleaving technique that can cope with soft errors. [ABSTRACT FROM AUTHOR]

This paper develops and demonstrates the design and optimization method for fixed coefficient Finite Impulse Response (FIR) filters using sub-threshold circuits to achieve the minimum energy per operation. Sub-threshold circuit current, delay, power consumption, energy per operation and temperature dependence are modeled theoretically and analyzed using Matlab. Then the filter design and optimization are presented. With a frequency characteristic of 80 dB magnitude and 9.6 kHz bandwidth, the 16-bit fixed-point coefficients of the linear phase equiripple low-pass filter are generated from Matlab. Canonical Signed Digit (CSD) arithmetic is used for multiplierless design to improve both cost and performance. The transposed structure and symmetry structure are applied to optimize the delay and cost further. Horner's rule is used to improve the precision. Tree-height reduction and subexpression sharing at Register Transfer Level (RTL) are used for further delay and cost reduction. Six versions of the filter with the same group of coefficients are designed and synthesized using Design Compiler with a 65 nm process. Synthesis results show that the area of the final version is reduced by 44% compared with the original design at a fixed frequency of 250 MHz, and at the highest frequency of each design, the area is reduce by about 23% while the performance is improved by 60%. These results show the design and optimization method developed in this paper can improve both the area and performance significantly. One adder from the synthesis netlist is simulated at the transistor-level using HSPICE to obtain characteristics of sub-threshold operations. The supply voltage varies from 1.2 to 0.08 V and temperatures from 0 to 110°C. The experiment results verify most characteristics of the sub-threshold models, but also reveal some limitations and defects of the theoretical models and previous results. The observations are discussed carefully with quantitative and qualitative analysis. For 25°C, the minimum energy point for the adder is 0.22 V. Finally, the results of the adder are used to estimate the energy per operation for the filters. For a fixed frequency of 36.4 kHz at 0.22 V, the estimated energy values vary from 4.8 to about 2.7 pJ for the six designed filters. [ABSTRACT FROM AUTHOR]

This work presents measured results from test chips containing circuits implemented with micro-electro-mechanical (MEM) relays. The relay circuits designed on these test chips illustrate a range of important functions necessary for the implementation of integrated VLSI systems and lend insight into circuit design techniques optimized for the physical properties of these devices. To explore these techniques a hybrid electro-mechanical model of the relays' electrical and mechanical characteristics has been developed, correlated to measurements, and then also applied to predict MEM relay performance if the technology were scaled to a 90 nm technology node. A theoretical, scaled, 32-bit MEM relay-based adder, with a single-bit functionality demonstrated by the measured circuits, is found to offer a factor of ten energy efficiency gain over an optimized CMOS adder for sub-20 MOPS throughputs at a moderate increase in area. [ABSTRACT FROM AUTHOR]

Minimizing the energy consumption of battery-powered systems is a key focus in integrated circuit design. This paper presents an energy minimization loop, with on-chip energy sensor circuitry, that can dynamically track the minimum energy operating voltage of arbitrary digital circuits with changing workload and operating conditions. An embedded DC-DC converter which enables this minimum energy operation is designed to deliver load voltages between 0.25 V to 0.7 V. The minimum energy tracking loop along with the DC-DC converter and test circuitry were fabricated in a 65 nm CMOS process. The area overhead of the control loop is only 0.05 mm². Measured energy savings of the order of 50%-100% are obtained on tracking the minimum energy point (MEP) as it varies with workload and temperature. The DC-DC converter delivers load voltages as low as 250 mV and achieved an efficiency >80% while delivering load powers of the order of 1 μW and higher from a 1.2 V supply. [ABSTRACT FROM AUTHOR]

This paper examines energy minimization for circuits operating in the subthreshold region. Subthreshold operation is emerging as an energy-saving approach to many energy-constrained applications where processor speed is less important. In this paper, we solve equations for total energy to provide an analytical solution for the optimum VDD and VT to minimize energy for a given frequency in subthreshold operation. We show the dependence of the optimum VDD for a given technology on design characteristics and operating conditions. This paper also examines the effect of sizing on energy consumption for subthreshold circuits. We show that minimum sized devices are theoretically optimal for reducing energy. A fabricated 0.18-µm test chip is used to compare normal sizing and sizing to minimize operational VDD and to verify the energy models. Measurements show that existing standard cell libraries offer a good solution for minimizing energy in subthreshold circuits. [ABSTRACT FROM AUTHOR]