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Modern SoCs require increasingly complex embedded control deep within their numerous sub-blocks without adding significant die area. This motivated the creation of $\mu $ RTL, a novel toolset for systematically designing efficient pipelined implementations of embedded instruction sets originally intended for multicycle execution. $\mu $ RTL utilizes hardwired micro-op translation, a technique commonly used in the instruction decoders of large super-scalar microprocessors, however this technique has been overlooked for designing smaller, more efficient embedded microprocessors. Furthermore, the tools to develop instruction decoders with micro-op translation are proprietary and the techniques are trade secrets. The $\mu $ RTL toolset is open-source and this letter clearly presents the methodology. The methodology emphasizes direct opcode decoding from multiple synthesized Verilog blocks versus traditional microprogramming which uses sequential decoding from a ROM. Our results show that a pipelined $\mu $ RTL microarchitecture achieves a 21.8% reduction in size compared to a hardwired multicycle implementation of the same instruction set. Additionally, the performance of 0.75 DMIPS/MHz surpasses the RISC-V PicoRV32 by 44.2% and the AVR RISC by 82.9%. These improvements in performance, power, and area are of interest to embedded system architects. [ABSTRACT FROM AUTHOR]

Low density parity check code (LDPC) is the most popular error correction code (ECC) for current nand flash memory controllers. Next generation flash memory, such as triple-level cell (TLC) and quad-level cell (QLC) with a higher bit error rate, bring up the demand for superior ECC algorithms providing excellent performance and acceptable hardware overhead. This letter proposes turbo product code (TPC) as an alternative to LDPC by exploring embedding of a TPC engine into a solid-state drive (SSD) controller architecture. The implementation of this TPC engine uses 2-D error coding and applies the Bose-Chaudhuri–Hocquenghem (BCH) code in each dimension. The algorithm is further improved by flipping the dedicated bit matrix when the basic TPC decoding algorithm terminates with uncorrectable conditions. This bit-flipping enhanced TPC (BFE-TPC) module is finally integrated into a nonvolatile memory express (NVMe) SSD controller driving eight flash memory channels. This BFE-TPC module illustrates the potential of 2D-TPCs as a replacement for LDPCs due to its high throughput and low hardware overhead. [ABSTRACT FROM AUTHOR]

In computer-numerical-controlled (CNC) machine tools, factors affecting machining precision mainly stem from the machine's own geometric errors and errors occurring during cutting due to thermal effects on its structure. Typically, thermal errors contribute to more than 70% of the total error. Hence, minimizing thermal errors in CNC machine tools is highly regarded. One significant and commonly used approach is the thermal error compensation (TEC) method. Although the TEC method has been extensively applied in both laboratory and industrial CNC machines, several challenges remain. For instance, the determination of optimal temperature characteristic points for various CNC machine tools requires improved methods, the mathematical models for predicting and compensating thermal errors are not sufficiently accurate, and there is poor compensation performance under varying cutting conditions. In this research, we focus on thermal error prediction and compensation technology for a CNC highspeed four-rail vertical machining center. Through actual cutting experiments, we measure temperatures at feature points on the machine and spindle deformation using various high-tech sensors. Subsequently, precise prediction and rapid compensation models for thermal errors are established using support vector regression and transfer function matrix methods, respectively. Finally, a TEC system based on a single-chip microprocessor is developed. In this system, we perform real-time TEC during actual machining by adjusting the machine's original point drift. Results from actual cutting experiments demonstrate that the developed TEC system can effectively reduce the target machine's thermal deformation from 110 µm to within 10 µm in real time. [ABSTRACT FROM AUTHOR]

MicroRNA (miRNA) biogenesis is initiated upon cleavage of a primary miRNA (pri-miRNA) hairpin by the Microprocessor (MP), composed of the Drosha RNase III enzyme and its partner DGCR8. Multiple pri-miRNA sequence motifs affect MP recognition, fidelity, and efficiency. Here, we performed cryoelectron microscopy (cryo-EM) and biochemical studies of several let-7 family pri-miRNAs in complex with human MP. We show that MP has the structural plasticity to accommodate a range of pri-miRNAs. These structures revealed key features of the 5′ UG sequence motif, more comprehensively represented as the "flipped U with paired N" (fUN) motif. Our analysis explains how cleavage of class-II pri-let-7 members harboring a bulged nucleotide generates a non-canonical precursor with a 1-nt 3′ overhang. Finally, the MP-SRSF3-pri-let-7f1 structure reveals how SRSF3 contributes to MP fidelity by interacting with the CNNC motif and Drosha's Piwi/Argonaute/Zwille (PAZ)-like domain. Overall, this study sheds light on the mechanisms for flexible recognition, accurate cleavage, and regulated processing of different pri-miRNAs by MP. [Display omitted] • The Microprocessor has the plasticity for accommodating a diversity of pri-miRNAs • RNA drives Microprocessor domain repositioning for pri-let-7 cleavage • The UG motif is redefined as a fUN motif for a comprehensive pri-miRNA classification • SRSF3 assists Drosha by positioning it at the basal junction of the pri-miRNA Garg et al. used cryo-EM to determine several structures of different pri-let-7 pri-miRNAs in complex with the Microprocessor, highlighting structural features important for flexible recognition, pri-miRNA cleavage, and cleavage regulation. The fUN structural motif and CNNC-SRSF3-assisted Drosha loading present insights applicable to the processing of hundreds of pri-miRNAs. [ABSTRACT FROM AUTHOR]

Chua's circuit represents a paradigm for nonlinear dynamics and chaos in electronic circuits. In this paper, its discrete-time counterpart is considered showing the occurrence of nonlinear resonance when driven by an external sinusoidal input. Evidences of jump resonance are revealed from several regions of the parameter space. An approach based on quasi-analytic methods, numerical simulations and several experiments with digital microprocessors is presented, further confirming the richness of Chua's circuit dynamical behavior. The high selectivity of the jump resonance observed from the discrete-time Chua's circuit paves the way for the implementation of low-cost high-resolution frequency drift sensing devices. [ABSTRACT FROM AUTHOR]

Wearable devices have generally been rigid due to their reliance on silicon‐based technologies, while future wearables will utilize flexible components for example transistors within microprocessors to manage data. Two‐dimensional (2D) semiconducting flakes have yet to be investigated in fiber transistors but can offer a route toward high‐mobility, biocompatible, and flexible fiber‐based devices. Here, the electrochemical exfoliation of semiconducting 2D flakes of tungsten diselenide (WSe2) and molybdenum disulfide (MoS2) is shown to achieve homogeneous coatings onto the surface of polyester fibers. The high aspect ratio (>100) of the flake yields aligned and conformal flake‐to‐flake junctions on polyester fibers enabling transistors with mobilities μ ≈1 cm2 V−1 s−1 and a current on/off ratio, Ion/Ioff ≈102–104. Furthermore, the cytotoxic effects of the MoS2 and WSe2 flakes with human keratinocyte cells are investigated and found to be biocompatible. As an additional step, a unique transistor 'knot' architecture is created by leveraging the fiber diameter to establish the length of the transistor channel, facilitating a route to scale down transistor channel dimensions (≈100 µm) and utilize it to make a MoS2 fiber transistor with a human hair that achieves mobilities as high as μ ≈15 cm2 V−1 s−1. [ABSTRACT FROM AUTHOR]

Persistent security challenges in Industry 4.0 due to the limited resources of IoT devices necessitate innovative solutions. Addressing this, this study introduces the ASCON algorithm for lightweight authenticated encryption with associated data, enhancing confidentiality, integrity, and authenticity within IoT limitations. By integrating Digital Twins, the framework emphasizes the need for robust security in Industry 4.0, with ASCON ensuring secure data transmission and bolstering system resilience against cyber threats. Practical validation using the MQTT protocol confirms ASCON's efficacy over AES-GCM, highlighting its potential for enhanced security in Industry 4.0. Future research should focus on optimizing ASCON for microprocessors and developing secure remote access tailored to resource-constrained devices, ensuring adaptability in the digital era. [ABSTRACT FROM AUTHOR]

In the present paper, the use of programmable microprocessors to develop a computerized stand for the preparation of a mixture of flammable/toxic/explosive gases in order to obtain mixtures at concentrations in explosive range is presented. The operating principle of the stand is based on the mixing of two volumetric flows, controlled with the help of microprocessors, where gases are stored and circulated at atmospheric pressure through cylindrical injectors, driven by stepper motors so that the gas circuit does not require valves. The exit of the stand is a homogenization chamber, with agitator and sensor to confirm the desired concentration of the mixture. This automated stand eliminates mechanical, electric or pneumatic valves from the gas circuits, avoiding elements with high mechanical resistance suitable for high pressures/depressions, removing the possibility of the return of the gas flow, without sensitivity to sudden pressures variations. [ABSTRACT FROM AUTHOR]

Wireless medical telemetry systems (WMTSs) are typical radio communication–based medical devices that monitor various biological parameters, such as electrocardiograms and respiration rates. In Japan, the assigned frequency band for WMTSs is 400 MHz. However, the issues accounting for poor reception in WMTS constitute major concerns. In this study, we analyzed the effects of electromagnetic interferences (EMIs) caused by other radio communication systems, the intermodulation (IM) effect, and noises generated from electrical devices on WMTS and discussed their management. The 400-MHz frequency band is also shared by other radio communication systems. We showed the instantaneous and impulsive voltages generated from the location-detection system for wandering patients and their potential to exhibit EMI effects on WMTS. Further, we presented the IM effect significantly reduces reception in WMTS. Additionally, the electromagnetic noises generated from electrical devices, such as light-emitting diode lamps and security cameras, can exceed the 400 MHz frequency band as these devices employ the switched-mode power supply and/or central processing unit and radiate wideband emissions. Moreover, we proposed and evaluated simple and facile methods using a simplified spectrum analysis function installed in the WMTS receiver and software-defined radio for evaluating the electromagnetic environment. [ABSTRACT FROM AUTHOR]

Collecting data such vibration signal or others from elevators is crucial for a regular maintenance or emergency repair in industry. However, traditional methods for data transmission through compression and decompression process usually require large input data arrays to be assigned. Therefore, a long computational time is unavoidable so that it may affect system performance efficiency significantly. Therefore, an elevator vibration and loading data collection system was developed using simple compression encoding mechanism. First, in Data Acquisition Unit, the signal-acquiring microprocessor is used for data acquisition through Inter-Integrated Circuit (I2C) bus. Second, in Data Storage Unit, the collected data from the signal-acquiring microprocessor is compressed and transmitted to the signal-processing microprocessor. Third, in Monitor Unit, the elevator analysis tool is developed to analyze the vibration data, which can be viewed directly from APP. Experimental results demonstrated that the restored data are consistent with the results measured from the standard instrument. The proposed hexadecimal compression process can make the data transmission mechanism simple, but two times faster than that using traditional way without compression. Consequently, the demanded memory capacity for signal transmission can be therefore reduced considerably. [ABSTRACT FROM AUTHOR]

As microprocessor currents exceed 500 A and slew rate reaches 1000 A/µs, increasing the decoupling capacitance on the motherboard to ensure normal operation of the microprocessor is inevitable because of the limited response capability of the voltage regulator. However, the area of the motherboard used for capacitors is usually narrow. To reduce the required capacitance, a novel buck converter with an auxiliary circuit for charge compensation using switched capacitors is proposed. The auxiliary circuit is not activated during the steady state. When the load current changes rapidly, the switched capacitors can quickly absorb or release charge to suppress voltage fluctuations. A 12 V–0.9 V buck converter has been built and tested under a 480 A load current step and a 960 A/µs current slew rate. The proposed scheme with 9.964 mF capacitance has an overshoot of 115 mV and an undershoot of 89 mV. Compared with the conventional PID scheme, the proposed scheme can save 58.4% of the capacitance for the same voltage fluctuations or suppress 39.5% of overshoot and 37.3% of undershoot with the same capacitance. [ABSTRACT FROM AUTHOR]

In response to the problem of disturbance in the imaging equipment of stratospheric airships, this study designs a vibration isolation and stability system for carrying imaging equipment. The system mainly consists of microprocessor, gimbal, voice coil motor (VCM) and rubber ring. By using adaptive control law based on characteristic model to control the double closed control loop of the motor composed of position loop and speed loop, the camera deflection caused by disturbance is effectively eliminated. Furthermore, in vertical vibration suppression, the adaptive control law based on the characteristic model is also applied to the double closed control loop of the voice coil motor, which removes most of the vertical vibration and realizes active vibration isolation. The passive isolation of the system is completed by rubber rings. The experimental results show that the vibration isolation and stabilization system have good performance in complex disturbance environments, effectively stabilizing the imaging equipment. [ABSTRACT FROM AUTHOR]

With the advancement in artificial intelligence technology, autonomous mobile robots have been utilized in various applications. In autonomous driving scenarios, object classification is essential for robot navigation. To perform this task, light detection and ranging (LiDAR) sensors, which can obtain depth and height information and have higher resolution than radio detection and ranging (radar) sensors, are preferred over camera sensors. The pillar-based method employs a pillar feature encoder (PFE) to encode 3D LiDAR point clouds into 2D images, enabling high-speed inference using 2D convolutional neural networks. Although the pillar-based method is employed to ensure real-time responsiveness of autonomous driving systems, research on accelerating the PFE is not actively being conducted, although the PFE consumes a significant amount of computation time within the system. Therefore, this paper proposes a PFE hardware accelerator and pillar-based object classification model for autonomous mobile robots. The proposed object classification model was trained and tested using 2971 datasets comprising eight classes, achieving a classification accuracy of 94.3%. The PFE hardware accelerator was implemented in a field-programmable gate array (FPGA) through a register-transfer level design, which achieved a 40 times speedup compared with the firmware for the ARM Cortex-A53 microprocessor unit; the object classification network was implemented in the FPGA using the FINN framework. By integrating the PFE and object classification network, we implemented a real-time pillar-based object classification acceleration system on an FPGA with a latency of 6.41 ms. [ABSTRACT FROM AUTHOR]

Although molecular vibronic spectra generation is pivotal for chemical analysis, tackling such exponentially complex tasks on classical computers remains inefficient. Quantum simulation, though theoretically promising, faces technological challenges in experimentally extracting vibronic spectra for molecules with multiple modes. Here, we propose a nontrivial algorithm to generate the vibronic spectra using states with zero displacements (squeezed vacuum states) coupled to a linear optical network, offering ease of experimental implementation. We also fabricate an integrated quantum photonic microprocessor chip as a versatile simulation platform containing 16 modes of single-mode squeezed vacuum states and a fully programmable interferometer network. Molecular vibronic spectra of formic acid and thymine under the Condon approximation are simulated using the quantum microprocessor chip with high reconstructed fidelity (> 92%). Furthermore, vibronic spectra of naphthalene, phenanthrene, and benzene under the non-Condon approximation are also experimentally simulated. Such demonstrations could pave the way for solving complicated quantum chemistry problems involving vibronic spectra and computational tasks beyond the reach of classical computers. Proof-of-principle photonic quantum simulations of molecular vibronic spectra have been realised, but scalability to more complex systems is hindered by the difficulties in generating squeezed coherent states with multiple modes. Here, the authors demonstrate an alternative approach relying on vacuum-squeezed state. [ABSTRACT FROM AUTHOR]

This study aimed to apply a microprocessor on a wireless automated vehicle to achieve real-time tracking of moving objects. The targets captured by the camera on the vehicle were first separated from their background through background subtraction. Next, morphological processing was performed to remove unnecessary information. An enhanced seeded region growing method was used to achieve image segmentation by labeling and segmenting the targets effectively, thus enhancing the accuracy and resolving the problem of object concealment. The corresponding red, green, and blue colors of each target were calculated through a color space, which was then converted into an enhanced luminance/chroma blue/chroma red (YUV) color space for color histogram modeling and storage, so as to increase the system's tracking speed. The enhanced YUV colors also achieved accurate tracking in dark places. After inputting the next image, an enhanced agglomerative hierarchical clustering method was used to agglomerate and connect pixels with the same YUV for tracking. A proportional-integral-derivative controller controlled the motors on the camera lens and the vehicle so that the target could be tracked properly in real-time. The experimental results revealed that our proposed tracking method performed better than conventional tracking methods. [ABSTRACT FROM AUTHOR]

This work is an original contribution consisting in the implementation and evaluation of a selective value predictor in a multicore environment, with focus on long latency arithmetical instructions, having the goal to break the dataflow bottleneck of each core, thus increasing the overall performance. The Sniper simulator was used to augment the Intel Nehalem architecture with a value predictor and to estimate the computing performance, area of integration, power consumption, energy efficiency and chip temperature for the enhanced architecture. We run simulations and study the impact of the number of values which are used for prediction for each instruction. By increasing the history length, we measured on average more than 3 % increase in performance (core speed-up), a reduction in chip temperature from 57.8 C to 56.17 C, and lower energy consumption in most cases compared with the baseline configuration. We also realized a comparison between the value prediction and dynamic instruction reuse techniques in equitable condition (to exploit the same value locality), where we highlight the advantages and disadvantages of each technique in the given context.