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The evolution of Digital Predistortion (DPD) for Power Amplifier (PA) linearization in wireless communications has seen a natural progression towards increasingly complex DPD models. This complexity directly correlates with improved accuracy in modeling PAs, thereby enhancing the linearization performance of DPD systems. As the demand for bandwidth and PA operation frequencies continues to rise, there is a growing trend towards achieving higher accuracy at the expense of increased complexity. This trend poses challenges for DPD design, necessitating the introduction of more complex algorithms to ensure effective PA linearization. This phenomenon is especially apparent in Volterra Series DPD algorithms, which are widely used for modelling nonlinear systems like PAs. This paper showcases the steps of reducing the modelling operations complexity of the Simplified Volterra (SV) method. The treated SV method presented in this paper is compared against the original SV method through simulation. The DPD model operations complexity is evaluated using the number of required multiplication operations. The DPD PA linearization performance is evaluated with respective model’s Normalized Mean Square Error (NMSE). A 57% reduction on the number of multiplication operations is observed in the treated SV against the original SV. Measured NMSE is similar for both models, indicating the treated SV model achieves this reduction in complexity without sacrificing linearization performance. [ABSTRACT FROM AUTHOR]

Summary: The nonlinear power amplifier and the analogue output channel filter with nonconstant group delay add nonlinear and linear distortions to the satellite transmitted signal, respectively. Recently, there has been growing interest in using Wiener predistorters, consisting of separate nonlinear and linear components, to compensate for these distortions in the satellite downlinks. The Wiener predistorter has been shown to effectively deal with signal distortions and has lower complexity compared to other state‐of‐the‐art methods. In this paper, we argue that fully compensating the nonconstant group‐delay distortion degrades the overall performance of the Wiener predistortion systems. This is primarily due to the increased peak‐to‐average power ratio of the signal at the output of the linear predistorter. We show that the overall performance of the Wiener predistorter can be improved by undercompensating the group‐delay distortion. We propose two optimizations to address the PAPR growth problem and show using simulations that our approach leads to significant improvement in predistortion performance. Using our Wiener predistorter, the total degradation gap to the ideal limiter channel can be reduced to merely 0.34 dB for 64‐APSK modulated signals. [ABSTRACT FROM AUTHOR]

Radio frequency (RF) power amplifiers (PA) are efficiently linearized by adaptive digital predistortion (DPD). However, performance of DPD is severely degraded in presence of transmitter’s frequency-selective in-phase/quadrature (I/Q) imbalance. We propose DPD/IQ method that compensates the effects of transmitter I/Q imbalance and PA nonlinearity, which is dedicated for implementation in low-cost software radio defined (SDR) cellular base stations. The advantage of DPD/IQ is low complexity in terms of reduced number of DPD coefficients which provides significant savings of FPGA resources. The DPD/IQ has been evaluated after method has been implemented in SDR board. Measured results clearly demonstrate efficient compensation of PA and transceiver impairments enabling transmission of wide bandwidth waveforms and realization of sophisticated modulation schemes. Improvement in image rejection ratio of 10-15dB is achieved. Considering compensation of PA nonlinearities, the ACPR at PA output is decreased by 15dBc.

The Volterra framework plays an important role in digital pre-distortion (DPD) for power amplifier (PA) linearization. In practice, the full-Volterra (FV) model is avoided due to the so-called curse of dimensionality, which has motivated several Volterra pruning techniques in the literature. However, choosing the pruned-Volterra structure with a given complexity that most accurately describes a PA or DPD with unknown characteristics often requires trial and error. The motivation of this article is to propose a reduced-Volterra model that extends traditional memory polynomials, e.g., the generalized memory polynomial (GMP), by including higher-dimensional terms in a flexible and controlled way, avoiding the curse of dimensionality of the Volterra model and resulting in a model that can apply to a wide range of PA and DPD. Furthermore, the article investigates the parsimonious sizing of the proposed model using least absolute shrinkage and selection operator (LASSO) and sparse-group LASSO (SGL) convex optimization, significantly reducing the model’s running cost, while preserving its performance. In our experimental validation, the sparse versions of the proposed model achieved 3 dB better adjacent channel power ratio (ACPR) than the conventional GMP model for the same or lower DPD running cost, at the expense of a more costly estimation, which is performed off-line.

This paper proposes a novel predistorter architecture suitable for hybrid baseband/RF implementation. The distortion function is split into a memory polynomial and an AM/AM only look-up table (LUT). The memory polynomial function is to be applied in the baseband digital domain whereas the LUT predistorter is suitable for low complexity implementation in either the baseband digital or the RF analog domains. The proposed model was compared to benchmark models using 20MHz and 40MHz wide 5G test signals, and found to be superior in terms of adjacent channel leakage ratio performance and complexity. Experimental results showed that the model can achieve ACLR levels of better than −50dBC with a relatively low number of coefficients. The proposed model requires around 20% less coefficients than the reverse twin-nonlinear two-box model, and achieves slightly better ACLR while easing the analog implementation of the static nonlinearity predistortion function. Most importantly, the low-complexity hybrid implementation of the proposed model can drastically reduce the speed requirements in the digital to analog converter of the signal transmit path by up to 80% when compared to traditional DPD systems.

In this paper, an efficient neural-network-based adaptive DPD design which performs well under power varying conditions is presented. The DPD design is derived on the basis of the envelop time-delay neural network (ETDNN). The redefined ETDNN-DPD requires the part of parameter updates, which enables to adapt it to the rapid change of power amplifier (PA) distortion. Additionally, the redefined ETDNN-DPD also maintains the stability of the compensation performances under varying power condition while its structure is pruned by the structured pruning. Furthermore, to verify its practical use, we also propose the weight scaling technique, which reduces multiplications of the redefined ETDNN-DPD, and applied it to the implementation of the redefined ETDNN-DPD on FPGA. Compared FPGA-implemented ETDNN-DPD with FPGA-implemented conventional memory polynomial DPD, we verified that our proposed DPD achieved 3.2 dB better error vector magnitude (EVM) while lower hardware resource utilization at the fixed power level. Moreover, our proposed DPD kept better performance under the varying power condition only by the partial update of its parameters than memory polynomial DPD.

With the rise of 5G and beyond, the ever-increasing data-rates demanded by mobile access are severely challenging the capacity of optical fronthaul networks. Despite its high reliability and ease of deployment, legacy digital radio-over-fiber (RoF) technologies face an upcoming bandwidth bottleneck in the short term. This has motivated a renewed interest in the development of analog RoF alternatives, owing to their high spectral efficiency. However, unlike its digital counterpart, analog RoF transmission requires a highly linear transceiver to guarantee signal fidelity. Typical solutions exploited in recent research works tend to adopt the use of bulky benchtop components, such as directly modulated lasers (DML) and photodiodes. Although this provides a convenient and quick path for proof-of-concept demonstrations, there is still a considerable gap between lab developments and commercial deployment. Most importantly, a key question arises: can analog-RoF transceivers meet the 5G requirements while being competitive in terms of cost and footprint? Following this challenge, in this work we exploit the use of a low-cost commercial off-the-shelf (COTS) small form-factor pluggable (SFP) transceiver, originally designed for digital transmission at 1 Gbps, which is properly adapted towards analog RoF transmission. Bypassing the digital electronics circuitry of the SFP, while keeping the original transmitter optical sub-assembly (TOSA) and receiver optical sub-assembly (ROSA), we demonstrate that high-performance 5G-compatible transmission can be performed by reusing the key built-in components of current low-cost SFP-class transceivers. Particularly, we demonstrate error vector magnitude (EVM) performances compatible with 5G 64QAM transmission both at 100MHz and 400MHz. Furthermore, employing a memory polynomial model for digital pre-distortion of the transmitted signal, we achieve 256QAM-compatible performance at 100MHz bandwidth, after 20 km fronthaul transmission.

Copyright of Telecommunication Engineering is the property of Telecommunication Engineering and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Radio frequency (RF) power amplifiers (PA) are efficiently linearized by adaptive digital predistortion (DPD). However, performance of DPD is severely degraded in presence of transmitter's frequency-selective in-phase/'quadrature (I/Q) imbalance. We propose the DPD/IQ method that compensates the effects of transmitter 's I/Q imbalance and PA nonlinearity and is dedicated for implementation in low-cost software defined radio (SDR) cellular base stations. The advantage of DPD/IQ is low complexity in terms of reduced number of DPD coefficients which provides significant savings of FPGA resources. The performance of DPD/IQ has been evaluated after the method has been implemented in SDR board. Measured results clearly demonstrate efficient compensation of PA and transceiver impairments enabling transmission of wide bandwidth waveforms and realization of sophisticated modulation schemes. Improvement in image rejection ratio of 10-15 dB is achieved. Considering compensation of PA nonlinearities, the ACPR at PA output is decreased by 15 dBc. [ABSTRACT FROM AUTHOR]

This paper proposes an efficient neural-network-based digital predistortion (DPD), named as envelope time-delay neural network (ETDNN) DPD. The method complies with the physical characteristics of radio-frequency (RF) power amplifiers (PAs) and uses a more compact DPD model than the conventional neural-network-based DPD. Additionally, a structured pruning technique is presented and used to reduce the computational complexity. It is shown that the resulting ETDNN obtained after applying pruning becomes so sparse that its complexity is comparable to that of conventional DPDs such as memory polynomial(MP) and generalized memory polynomial (GMP), while the degradation in performance due to the pruning is negligible. In an experiment on a 3.5-GHz GaN Doherty power amplifier (PA), our method with the proposed pruning had only one-thirtieth the computational complexity of the conventional neural-network-based DPD for the same adjacent channel leakage ratio (ACLR). Moreover, compared with memory-polynomial-based digital predistortion, our method with the proposed pruning achieved a 7-dB improvement in ACLR, despite it having lower computational complexity.

In this paper, a software-defined radio (SDR) based transceiver system is designed and implemented on the system-on-chip (SoC) platform, which consists of a high-speed Arm embedded processor and a reconfigurable field-programmable gate array (FPGA). In the proposed SDR transceiver, the real-time baseband signal generation and adaptive digital predistortion (ADPD) units are implemented on the SoC platform. Memory polynomial model based ADPD solution is implemented to linearize the radio frequency (RF) power amplifiers (PAs). The implementation of the ADPD on a reconfigurable FPGA platform makes the system flexible and cost-effective. The PA characterization, in terms of model extraction and coefficient calculation, is done in real-time. These calculated coefficients are updated in the transmission path to precondition the transmitted signal before it is applied to the PA. The proposed ADPD is applied at the baseband level. Therefore, it can be used for different classes of PA operating at different RF carrier frequencies. A long-term evolution (LTE) signal with 20 MHz bandwidth and 11 dB peak to average power ratio (PAPR) is used for simulation and measurement purposes. The LTE signal is amplified using a GaN-based harmonically tuned continuous Class-F PA in measurement. The performance of the implemented ADPD scheme is analyzed in terms of NMSE, ACPR and EVM.

This paper introduces the measurement/modeling of a nonlinear RF power amplifier (PA) model extraction of spectral overlaps and peak-to-average power ratio (PAPR). The modeling consists of a weighted cubic-spline basis approach that preserves a relationship by its generic asymptotic properties under adequate PAPR regime to estimate signaling conditions. To jointly provide a data-driven model a field-programmable gate array (FPGA) testbed is proposed, in which a precomputed approach with deterministic signals is used to perform: (i) parameter estimation; (ii) adequate PAPR levels; (iii) reinforcement of sparsity data with extrapolation fitting; and (iv) FPGA implementation. Moreover, a technique for parameter identification is introduced to provide insights of a digital predistortion (DPD) PA model extraction with cubic-spline to efficiently improve the linearization performance. A theoretical analysis that states on the benefits from coefficients precomputation to preserve multiple-input multiple-output (MIMO) relationship with antenna selection technique estimation, is also proposed. Also, a Cholesky FPGA algorithm implementation to matrix inversion is validated, which aims to show the good numerical and computational complexity for up to $64\times 64$ MIMO arrays. Experimental results prove a good accuracy and close agreement between the modeling and estimation yielding a reliable model with a little overfitting.

Multiple-input multiple-output (MIMO) beamforming array gain can make multi-antenna transmitters (TXs) more power efficient. However, these MIMO TXs require more complex digital predistortion (DPD). In this brief, analytical expressions are derived for the power consumption of both MIMO power amplifier (PA) arrays and their respective DPD, taking into account the effects of precoding on PA output power and peak-to-average power ratio (PAPR). It is shown that for complex DPD algorithms such as cross-over DPD (CO-DPD) in combination with wide bandwidths, the overall DPD power consumption can exceed the overall PA power consumption already for scenarios with more than two antennas. [ABSTRACT FROM AUTHOR]

We demonstrate experimentally, for the first time, a distributed digital predistortion model for radio-over-fiber (RoF) downlink suitable for broadband 5G signals. The model reduces the analog-to-digital converter sampling frequency up to 1/3 of the required sampling in the example of the conventional memory polynomial DPD model, hence reducing demodulator costs and hardware complexity. This model also provides better intercarrier interference by reducing the adjacent channel leakage ratio (ACLR). This leads to reduced crosstalk, which impacts the multi-core and multimode RoF links. Long-term evolution advanced signals of a 256-quadratic-amplitude modulation of different bandwidths are used to validate the model. We achieved an average reduction of 2.5 dB in ACLR for signal bandwidths in the range 100–300 MHz while maintaining minimum error vector magnitude (EVM). The RoF downlink can deliver a peak bit rate of 2.016 Gb/s with a spectral efficiency of 6.72 b/Hz and EVM less than 4%.

The analog front of the direct conversion transmitter suffers from the effects of various unavoidable nonlinearities, such as local oscillator (LO) leakage, power amplifier (PA) nonlinearities, and in-phase and quadrature (I/Q) branch amplitude and phase imbalance, etc. To overcome these nonlinear effects, an accurate three-input nonlinear model is proposed for joint compensation of frequency-dependent I/Q imbalance and PA nonlinear distortion in this paper. The proposed nonlinear model is an augmented version of the modulator I/Q imbalance compensation model, where the magnitudes of the input signal are included as the model input, and a three-input nonlinear compensation model with linear parameters is developed. The advantage of the proposed model is that the augmented envelope-dependent terms can produce the basis function sets for compensating the PA nonlinear distortions in the transmitter. Furthermore, the computational complexity of the proposed model is analyzed in detail for practical digital implementation. To verify the validity of the proposed model, the imperfect transmitters based on single-device gallium nitride (GaN) PA and GaN Doherty PA, which are driven by different communication signals, are used for experimental verification and analysis. The experimental results show that the proposed model is able to give improved modeling and distortion mitigation capability than the other reported I/Q imbalance compensation methods when the effects of I/Q imbalance and nonlinear characteristics of PA are considered together.

The light-emitting diode (LED) is the major source of nonlinearity in LED communications, and the nonlinearity needs to be effectively modeled and mitigated to avoid the degradation of communication performance. In indoor LED communications, multipath dispersion can lead to inter-symbol interference (ISI) at high data rates. In this paper, we jointly estimate the LED nonlinearity and ISI channel based on an orthogonal polynomial based technique. Then, frequency domain equalization and post-distortion are adopted to mitigate the ISI and nonlinearity. Simulation results are provided to demonstrate the effectiveness of the proposed technique.

Digital predistortion (DPD), based on complex-valued memory polynomials (MP), is established as an efficient method for power amplifier (PA) linearization. The DPD facilitates compliance of the telecommunication infrastructure to strict standard specifications (transmit spectrum mask (TSM), error vector magnitude (EVM), bit error rate (BER), ...) by making PA more linear, while at the same time reduces the running cost of the wireless infrastructure (at both Base Transceiver Station (BTS) and User Equipment (UE) sides) by making PA more power efficient. Even when DPD is utilized, signals with high peak-to-average power ratio (PAPR) produce out-of-band PA spectrum emission due to intermodulation products affecting all above-mentioned critical standard specified parameters. The novelty proposed in this paper is as follows. PA is restricted to operate within "reasonably above" PA linear region using PAPR reduction technique. The residual nonlinearity is taken care of by DPD. The combination of DPD and PAPR PA linearization methods is implemented on software-defined radio board. The necessary steps for efficient PA linearization are presented, compensating both out-of-band and in-band signal distortions. We achieved EVM = 2.0%, ACPR − 50 dBc, at 10 W LTE modulated PA output, antenna point and PA output power of 39.5 dBm. [ABSTRACT FROM AUTHOR]

The light-emitting diode (LED) is the major source of nonlinearity in LED communications, and the nonlinearity needs to be effectively modeled and thereby mitigated through predistortion or postdistortion to avoid degradation of communication performance. A memory polynomial is often used for LED nonlinearity modeling and mitigation in the literature. However, the estimation of memory polynomial coefficients suffers from numerical instability, resulting in inaccurate modeling and poor performance in nonlinearity mitigation. In this paper, we propose an orthogonal polynomial-based nonlinearity modeling and mitigation technique for LED communications with pulse amplitude modulation (PAM) signaling and show that the proposed technique significantly outperforms the conventional memory polynomial-based techniques.

The light-emitting diode (LED) is the major source of nonlinearity in LED communications, and the nonlinearity needs to be effectively modeled and mitigated to avoid the degradation of communication performance. In indoor LED communications, multipath dispersion can lead to inter-symbol interference (ISI) at high data rates. In this paper, we jointly estimate the LED nonlinearity and ISI channel based on an orthogonal polynomial based technique. Then, frequency domain equalization and post-distortion are adopted to mitigate the ISI and nonlinearity. Simulation results are provided to demonstrate the effectiveness of the proposed technique. [ABSTRACT FROM AUTHOR]

Summary: In this paper, a practical non‐linear equalizer with iterative distortion cancellation in a satellite receiver is studied. Assuming no prior satellite channel knowledge, distortion estimation and cancellation are performed at the receiver by means of a memory polynomial model used for channel estimation. A data packet transmission scenario over a single‐carrier satellite transponder is simulated, using the not‐linearized amplifier and onboard filter characteristics similar to the direct‐to‐home broadcast DVB‐S2X reference scenario. Varying the memory depth and the non‐linear order of the memory polynomial model trained in the receiver, we compared the packet‐error rate performance of the practical non‐linear equalizer to the standard fractionally spaced linear adaptive equalizer, as well as to an implementation of the non‐linear equalizer with ideal channel knowledge at the receiver. The improved receiver demonstrates superior performance as compared with the standard linear equalizer with up to 5.48‐dB energy efficiency gain for 64‐amplitude and phase‐shift keying for a practical memory polynomial set‐up, and it approaches consistently the packet‐error rate performance of the implementation with ideal channel knowledge when increasing the memory depth and the non‐linear order. Furthermore, it enables the use of high‐order modulation up to 256‐amplitude and phase‐shift keying in the studied scenario, improving significantly the spectral efficiency of the air interface. [ABSTRACT FROM AUTHOR]

Copyright of Telecommunication Engineering is the property of Telecommunication Engineering and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In this paper, a nonlinear autoregressive with exogenous inputs (NARX) digital pre-distortion scheme to linearize power amplifiers is proposed. The proposed NARX digital pre-distortion gives better accuracy and spectral leakage suppression compared with other commonly used Volterra-based techniques. The stability criterion of the NARX digital pre-distortion is derived from the frequency domain analysis. Simulation is carried out with a 20 MHz single carrier long-term evolution signal and two-carrier long-term evolution signal and instantaneous to average ratio of 6.2 dB at 0.01% complementary cumulative distribution function (CCDF). The results of simulation analysis show a slight improvement in adjacent channel leakage ratio performance with 30% reduction in the number of floating point operations compared with conventional pre-distortion techniques. Copyright © 2016 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

In this paper, an adaptive digital predistortion based on a memory polynomial model is proposed in order to linearize the power amplifier with memory effect. The coefficients of the power amplifier model have been extracted using a least square method and those of predistortion have been identified by applying an indirect learning structure. Finally, the performance of digital predistortion has been demonstrated using the simulation of the power amplifier and the digital predistortion excited by a modulated 16 QAM signal in Matlab software. According to the simulation results, the criterion of adjacent channel power ratio (ACPR) declined by around 15 dB and the input/output power spectrum density of the power amplifier has quite similar curves. The linearized power amplifier output spectrum demonstrates the superiority of the proposed predistorter in eliminating the spectral regrowth which is caused by the memory effect in comparison to the other linearization methods. [ABSTRACT FROM AUTHOR]

One of the biggest power consuming devices in wireless communications system is the Power Amplifier (PA) which amplifies signals non-linearly when operating in real-world systems. The negative effects of PA non-linearity are energy inefficiency, amplitude and phase distortion. The increases in transmission speed in present day communication technology introduces Memory Effects, where signal spreading happens at the PA output, thus causing overhead in signal processing at the receiver side. PA Linearization is therefore required to counter the non-linearity and Memory Effects. Digital Pre-distortion (DPD) is one of the outstanding PA Linearization methods in terms of its strengths in implementation simplicity, bandwidth, efficiency, flexibility and cost. DPD pre-distorts the input signal, using an inversed model function of the PA. Modelling of the PA is therefore vital in DPD, where the Memory Polynomial Method (MP) is used to model the PA with memory effects. In this paper, the MP method is improved in Memory Polynomial using Binomial Reduction method (MPB-imag-2k). The method is simulated using a modelled ZVE-8G Power Amplifier and sampled 4G (LTE) signals. It was found MPB-imag-2k is capable of achieving comparable anti-scattering/anti-distortion in MP for non-linearity order of 3, memory depth of 3 and pre-amplifier gain of 2. [ABSTRACT FROM AUTHOR]

The light-emitting diode (LED) is the major source of nonlinearity in LED communications, and the nonlinearity needs to be effectively modeled and thereby mitigated through predistortion or postdistortion to avoid degradation of communication performance. A memory polynomial is often used for LED nonlinearity modeling and mitigation in the literature. However, the estimation of memory polynomial coefficients suffers from numerical instability, resulting in inaccurate modeling and poor performance in nonlinearity mitigation. In this paper, we propose an orthogonal polynomial-based nonlinearity modeling and mitigation technique for LED communications with pulse amplitude modulation (PAM) signaling and show that the proposed technique significantly outperforms the conventional memory polynomial-based techniques. [ABSTRACT FROM PUBLISHER]

In this paper, a low-complexity model is proposed for linearizing power amplifiers with memory effects using the digital predistortion (DPD) technique. In the proposed model, the linear, low-order nonlinear and highorder nonlinear memory effects are computed separately to provide flexibility in controlling the model parameters so that both high performance and low model complexity can be achieved. The performance of the proposed model is assessed based on experimental measurements of a commercial class AB power amplifier by applying a single-carrier wideband code division multiple access (WCDMA) signal. The linearity performance and the model complexity of the proposed model are compared with the memory polynomial (MP) model and the DPD with single-feedback model. The experimental results show that the proposed model outperforms the latter model by 5 dB in terms of adjacent channel leakage power ratio (ACLR) with comparable complexity. Compared to MP model, the proposed model shows improved ACLR performance by 10.8 dB with a reduction in the complexity by 17% in terms of number of floating-point operations (FLOPs) and 18% in terms of number of model coefficients. [ABSTRACT FROM AUTHOR]

In this paper, a novel weighted memory polynomial (WMP)-based model is proposed for wireless transmitters and radio-frequency power amplifiers' (PAs) behavioral modeling and predistortion. The new model introduces an instantaneous-power-dependent weight function on the static and dynamic terms of the conventional memory polynomial (MP) model. Experimental validation in both modeling and predistortion contexts was performed on a PA prototype driven by a 20-MHz Long Term Evolution signal. The proposed model was assessed against the standard MP model. The experimental results demonstrate the superiority of the proposed polynomial in behavioral modeling applications as it results in up to 50% (3-dB) improvement in the normalized mean square error for the same number of coefficients. The model robustness was then validated by using a second test signal applied to two Doherty PAs using different transistor technologies. Furthermore, when applied for digital predistortion, the proposed WMP function achieves the same performance as the state-of-art MP while requiring approximately 50% less coefficients. [ABSTRACT FROM PUBLISHER]

As for the nonlinear and memory effects of RF power amplifier in modern wireless communication systems, this paper proposed a new dynamic rational-function model of low complexity. The proposed model simplified the rational-function model, and could be written as the ratio of two general memory poly-nomials, the molecular was a form of envelope memory polynomial, and the denominator consists of memorylees polynomial. Through the model simulation and predistortion system application, the results show that, compared with MP model, the dynamic rational-function model can get the similar model accuracy but with an approximately 30. 6% reduction in the number of coeeficients, and improve the adjacent channel power ratio" ACPR) almost 20 dB. However, compared with rational-function model, the dynamic rational-function model can increase the accuracy 2. 4 dB and improve the ACPR almost 15 dB, but with an approximately 21. 9% reduction in the number of coeeficients. The results show the superiority of the model complexity and accuracy, and the important reference value to the study of the amplifier predistortion. [ABSTRACT FROM AUTHOR]

Accurately modeling the memory effects is critical in modeling and nonlinearity pre-compensation for wideband radio frequency (RF) power amplifiers (PAs) with strong memory effects. In this paper, the memory effects are divided into two categories: lagging memory effect and leading memory effect, which are defined based on the input samples located after and before the current output samples, separately. Considering the above two types of memory effects, a generalized two-box cascaded (GTBC) nonlinear behavioral model for RF PAs with strong memory effects is proposed: one box for a static nonlinearity block that is used to include the strong static nonlinearities and the other box for a dynamic nonlinearity block which is used to predict the mild dynamic nonlinearities. The modeling accuracy of the proposed model, in terms of the normalized mean square error (NMSE) and the memory effect intensity (MEI), is compared to the generalized memory polynomial (GMP), the augmented Hammerstein (AH) and the enhanced Hammerstein (EH) models for a 450-470 MHz Doherty PA with a three-carrier WCMDA input signal and a 895-935 MHz inverse Class-F Doherty PA with a single-carrier FDD-LTE OFDM input signal. The validation demonstrates that the proposed model leads to high-accuracy with fewer modeling coefficients and floating point operations (FLOPs). [ABSTRACT FROM AUTHOR]

In modern communication systems, nonlinearity in power amplifiers (PAs) and in-phase and quadrature-phase (I/Q) imperfections in the transmitter are of enormous concern. With the increase in the importance for highly energy efficient and low complexity models, there is a need to develop low complexity digital predistortion (DPD) methods. In this paper, we present a novel memory polynomial based distributed two block model to alleviate these impairments. Various performance metrics are used to evaluate the design performance and complexity of proposed model as compared to the state of the art predistorter model. Simulation and measurement results indicate the ability of the proposed model to meet the desired design purpose with reduced complexity in terms of number of coefficients, dispersion coefficient, condition number and number of floating points operations required for computing various steps in the inverse modeling algorithm. This is achieved while maintaining reasonable performances in terms of NMSE and ACEPR. The major attribute of the model is the reduction in complexity of the system. The number of complex valued coefficients and the number of floating point operations (FLOPs) are both reduced by 17%–56%, matrix conditioning is improved by 12–33 dB and the dispersion coefficient is reduced by 16–42 dB as compared to the previously proposed joint modulator and power compensation technique. [ABSTRACT FROM AUTHOR]