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Synaptic connectivity defines groups of neurons that engage in correlated activity during specific functional tasks. These co-active groups of neurons form ensembles, the operational units involved in, for example, sensory perception, motor coordination and memory (then called an engram). Traditionally, ensemble formation has been thought to occur via strengthening of synaptic connections via long-term potentiation (LTP) as a plasticity mechanism. This synaptic theory of memory arises from the learning rules formulated by Hebb and is consistent with many experimental observations. Here, we propose, as an alternative, that the intrinsic excitability of neurons and its plasticity constitute a second, non-synaptic mechanism that could be important for the initial formation of ensembles. Indeed, enhanced neural excitability is widely observed in multiple brain areas subsequent to behavioral learning. In cortical structures and the amygdala, excitability changes are often reported as transient, even though they can last tens of minutes to a few days. Perhaps it is for this reason that they have been traditionally considered as modulatory, merely supporting ensemble formation by facilitating LTP induction, without further involvement in memory function (memory allocation hypothesis). We here suggest-based on two lines of evidence--that beyond modulating LTP allocation, enhanced excitability plays a more fundamental role in learning. First, enhanced excitability constitutes a signature of active ensembles and, due to it, subthreshold synaptic connections become suprathreshold in the absence of synaptic plasticity (iceberg model). Second, enhanced excitability promotes the propagation of dendritic potentials toward the soma and allows for enhanced coupling of EPSP amplitude (LTP) to the spike output (and thus ensemble participation). This permissive gate model describes a need for permanently increased excitability, which seems at odds with its traditional consideration as a short-lived mechanism. We propose that longer modifications in excitability are made possible by a low threshold for intrinsic plasticity induction, suggesting that excitability might be on/offmodulated at short intervals. Consistent with this, in cerebellar Purkinje cells, excitability lasts days to weeks, which shows that in some circuits the duration of the phenomenon is not a limiting factor in the first place. In our model, synaptic plasticity defines the information content received by neurons through the connectivity network that they are embedded in. However, the plasticity of cell-autonomous excitability could dynamically regulate the ensemble participation of individual neurons as well as the overall activity state of an ensemble. [ABSTRACT FROM AUTHOR]

This paper offers a fresh perspective to memory allocation in edge-PLCs within industrial IoT environments, leveraging a hybrid a structure that incorporates Deep Q-Networks (DQN) and Bidirectional Long Short-Term Memory Networks (BiLSTM), complemented by Quantum Genetic Algorithm Optimization. In addressing the dynamic challenges of memory management, our method combines the reinforcement learning capabilities of DQN with the temporal contextualization provided by BiLSTM networks. The DQN component learns to optimize memory allocation policies based on immediate rewards and feedback, while the BiLSTM network captures long-term dependencies in data, enhancing predictive modeling for future data arrival rates. Moreover, we introduce Quantum Genetic Algorithm Optimization, a cutting-edge approach that infuses quantum-inspired principles into the traditional genetic algorithm framework, to further refine the memory allocation process. By leveraging principles of quantum computing, this optimization algorithm explores the solution space more efficiently, allowing for faster convergence and improved performance. Through simulation experiments, we exhibit the potency of our hybrid approach in reducing data loss probability and enhancing system performance in edge-PLCs. Our findings underscore the significance of integrating advanced machine learning techniques with quantum-inspired optimization algorithms to address complex challenges in industrial IoT environments, offering a promising avenue for enhancing memory allocation efficiency in edge computing systems.

Memories are thought to be stored in ensembles of neurons across multiple brain regions. However, whether and how these ensembles are coordinated at the time of learning remains largely unknown. Here, we combined CREB-mediated memory allocation with transsynaptic retrograde tracing to demonstrate that the allocation of aversive memories to a group of neurons in one brain region directly affects the allocation of interconnected neurons in upstream brain regions in a behavioral- and brain region-specific manner in mice. Our analysis suggests that this cross-regional recruitment of presynaptic neurons is initiated by downstream memory neurons through a retrograde mechanism. Together with statistical modeling, our results indicate that in addition to the anterograde flow of information between brain regions, the establishment of interconnected, brain-wide memory traces relies on a retrograde mechanism that coordinates memory ensembles at the time of learning.

Memories are thought to be stored in neural ensembles known as engrams that are specifically reactivated during memory recall. Recent studies have found that memory engrams of two events that happened close in time tend to overlap in the hippocampus and the amygdala, and these overlaps have been shown to support memory linking. It has been hypothesized that engram overlaps arise from the mechanisms that regulate memory allocation itself, involving neural excitability, but the exact process remains unclear. Indeed, most theoretical studies focus on synaptic plasticity and little is known about the role of intrinsic plasticity, which could be mediated by neural excitability and serve as a complementary mechanism for forming memory engrams. Here, we developed a rate-based recurrent neural network that includes both synaptic plasticity and neural excitability. We obtained structural and functional overlap of memory engrams for contexts that are presented close in time, consistent with experimental and computational studies. We then investigated the role of excitability in memory allocation at the network level and unveiled competitive mechanisms driven by inhibition. This work suggests mechanisms underlying the role of intrinsic excitability in memory allocation and linking, and yields predictions regarding the formation and the overlap of memory engrams. [ABSTRACT FROM AUTHOR]

Many modern Systems-on-Chip (SoCs) are equipped with specialized Machine Learning (ML) accelerators that use both on-chip and off-chip memory to execute neural networks. While on-chip memory usually has a hard limit, off-chip memory is often considered large enough to hold the network’s inputs, outputs, weights, and any intermediate results that may occur during model execution. This assumption may not hold for edge devices, such as smartphones, which usually have a limit on the amount of memory a process can use. In this study, we propose a novel approach for minimizing a neural network’s off-chip memory usage by introducing a tile-aware allocator capable of reusing memory occupied by parts of a tensor before the entire tensor expires. We describe the necessary conditions for such an off-chip memory allocation approach and provide the results, showing that it can save up to 33% of the peak off-chip memory usage in some common network architectures.

FPGA has become a very powerful platform to provide real-time Electromagnetic Transient (EMT) solutions due to the much lower investment costs in comparison to the other existing real-time platform. Existing off-line initialization methods cannot be applied to real-time FPGA directly owing to timing constraints and resource utilization. Without appropriate initialization, it can lead to divergence for FPGA-based EMT simulations and cause inaccurate simulation results. To provide real-time initialization, this paper presents four initialization methods for FPGA-based EMT, namely, physical interface (Method 1), signal declaration (Method 2), signal assignment (Method 3) and Coefficient (COE) file (Method 4). The performance of these four methods are also compared, and Method 4 can initialize instantly with the simplest code. To improve hardware adaptability, optimized strategies are developed for address sequence, interface, update modes and dataflow. To accelerate initialization, software-to-hardware algorithm and structure are developed to automate initialization data sources for different topologies. Case study shows Method 2–4 can both initialize successfully on FPGA platform, while Method 4 achieves the best timing and routing performance. To verify scalability, Method 4 is expanded to initialize 4-machine 11-bus system and eliminate significant error to less than 5%, with a timing constraint of 0.005 ns.

Memory formation is dynamic in nature, and acquisition of new information is often influenced by previous experiences. Memories sharing certain attributes are known to interact so that retrieval of one increases the likelihood of retrieving the other, raising the possibility that related memories are organized into associative mnemonic structures of interconnected representations. Although the formation and retrieval of single memories have been studied extensively, very little is known about the brain mechanisms that organize and link related memories. Here we review studies that suggest the existence of mnemonic structures in humans and animal models. These studies suggest three main dimensions of experience that can serve to organize related memories: time, space, and perceptual/conceptual similarities. We propose potential molecular, cellular, and systems mechanisms that might support organization of memories according to these dimensions.

The rapid adoption of Advanced Driver Assistance Systems (ADAS) in modern vehicles, aiming to elevate driving safety and experience, necessitates the real-time processing of high-definition video data. This requirement brings about considerable computational complexity and memory demands, highlighting a critical research void for a design integrating high FPS throughput with optimal Mean Average Precision (mAP) and Mean Intersection over Union (mIoU). Performance improvement at lower costs, multi-tasking ability on a single hardware platform, and flawless incorporation into memory-constrained devices are also essential for boosting ADAS performance. Addressing these challenges, this study proposes an ADAS multi-task learning hardware-software co-design approach underpinned by the Kria KV260 Multi-Processor System-on-Chip Field Programmable Gate Array (MPSoC-FPGA) platform. The approach facilitates efficient real-time execution of deep learning algorithms specific to ADAS applications. Utilizing the BDD100K+Waymo, KITTI, and CityScapes datasets, our ADAS multi-task learning system endeavours to provide accurate and efficient multi-object detection, segmentation, and lane and drivable area detection in road images. The system deploys a segmentation-based object detection strategy, using a ResNet-18 backbone encoder and a Single Shot Detector architecture, coupled with quantization-aware training to augment inference performance without compromising accuracy. The ADAS multi-task learning offers customization options for various ADAS applications and can be further optimized for increased precision and reduced memory usage. Experimental results showcase the system’s capability to perform real-time multi-class object detection, segmentation, line detection, and drivable area detection on road images at approximately 25.4 FPS using a $1920\times 1080\text{p}$ Full HD camera. Impressively, the quantized model has demonstrated a 51% mAP for object detection, 56.62% mIoU for image segmentation, 43.86% mIoU for line detection, and 81.56% IoU for drivable area identification, reinforcing its high efficacy and precision. The findings underscore that the proposed ADAS multi-task learning system is a practical, reliable, and effective solution for real-world applications.

The parallel computing framework Spark 2.x adopts a unified memory management model. In the case of the memory bottleneck, the memory allocation of active tasks and the RDD(Resilient Distributed Datasets) cache causes memory contention, which may reduce computing resource utilization and persistence acceleration effects, thus affecting program execution efficiency. To this end, we propose less contention management strategy, abbreviated as MCM, to reduce the negative impact of memory contention. MCM is divided into two steps: Firstly, the task minimum memory priority guarantee algorithm is priority to meet the minimum resources of tasks for execution, to optimize the number of active tasks. Secondly, considering contention costs, the persisted location selection algorithm dynamically selects the best storage location to improve the effect of persistence acceleration. The experimental results comfirm that MCM has wonderful adaptability and scalability. In the case of serious memory bottleneck, MCM obviously reduces job execution time. Compared with similar works, such as only_memory, only_disk, memory_and_disk, DMAOM and SACM, MCM reduces the execution time by 28.3%. [ABSTRACT FROM AUTHOR]

Massively parallel systems, such as Graphics Processing Units (GPUs), play an increasingly crucial role in today's data-intensive computing. The unique challenges associated with developing system software for massively parallel hardware to support numerous parallel threads efficiently are of paramount importance. One such challenge is the design of a dynamic memory allocator to allocate memory at runtime. Traditionally, memory allocators have relied on maintaining a global data structure, such as a queue of free pages. However, in the context of massively parallel systems, accessing such global data structures can quickly become a bottleneck even with multiple queues in place. This paper presents a novel approach to dynamic memory allocation that eliminates the need for a centralized data structure. Our proposed approach revolves around letting threads employ random search procedures to locate free pages. Through mathematical proofs and extensive experiments, we demonstrate that the basic random search design achieves lower latency than the best-known existing solution in most situations. Furthermore, we develop more advanced techniques and algorithms to tackle the challenge of warp divergence and further enhance performance when free memory is limited. Building upon these advancements, our mathematical proofs and experimental results affirm that these advanced designs can yield an order of magnitude improvement over the basic design and consistently outperform the state-of-the-art by up to two orders of magnitude. To illustrate the practical implications of our work, we integrate our memory management techniques into two GPU algorithms: a hash join and a group-by. Both case studies provide compelling evidence of our approach's pronounced performance gains.

Persistent byte-addressable memory (PM) is poised to become prevalent in future computer systems. PMs are significantly faster than disk storage, and accesses to PMs are governed by the Memory Management Unit (MMU) just as accesses with volatile RAM. These unique characteristics shift the bottleneck from I/O to operations such as block address lookup—for example, in write workloads, up to 45% of the overhead in ext4-DAX is due to building and searching extent trees to translate file offsets to addresses on persistent memory. We propose a novel contiguous file system, ctFS, that eliminates most of the overhead associated with indexing structures such as extent trees in the file system. ctFS represents each file as a contiguous region of virtual memory, hence a lookup from the file offset to the address is simply an offset operation, which can be efficiently performed by the hardware MMU at a fraction of the cost of software-maintained indexes. Evaluating ctFS on real-world workloads such as LevelDB shows it outperforms ext4-DAX and SplitFS by 3.6× and 1.8×, respectively. [ABSTRACT FROM AUTHOR]

In modern operating systems and programming languages adapted to multicore computer architectures, parallelism is abstracted by the notion of execution threads. Multi-threaded systems have two major specificities: on the one part, new threads can be created dynamically at runtime, so there is no bound on the number of threads participating in long-running executions. On the other part, threads have access to a memory allocation mechanism that cannot allocate infinite arrays. These specificities make it challenging to adapt some algorithms to multi-threaded systems, in particular those that need to assign one shared register per process. This paper explores the synchronization power of shared objects in multi-threaded systems by extending the famous Herlihy's wait-free hierarchy to take these constraints into consideration. It proposes to subdivide the set of objects with an infinite consensus number into nine new degrees, depending on their ability to synchronize a bounded, finite or infinite number of processes, with or without the need to allocate an infinite array. To show the relevance of the proposed extension, for each new degree it is either proved that it is empty, or an object illustrating it is proposed. [ABSTRACT FROM AUTHOR]

I recount some landmark discoveries that initially confirmed the cyclic AMP response element-binding (CREB) protein-memory consolidation and allocation linkages. This work constitutes one of the successes of the field of Molecular and Cellular Cognition (MCC) but is also of interest to philosophers of neuroscience. Two approaches, “mechanism” and “ruthless reductionism”, claim to account for this case, yet these accounts differ in one crucial way. I explain this difference and argue that both the experiment designs and discussions of these discoveries by MCC scientists better fit the ruthless reductionist's account. This conclusion leads to further philosophical discussion about how discoveries in cellular/molecular neurobiology integrate with systems neuroscience findings.

Abstract The insular cortex (IC) is the primary gustatory cortex, and it is a critical structure for encoding and retrieving the conditioned taste aversion (CTA) memory. In the CTA, consumption of an appetitive tastant is associated with aversive experience such as visceral malaise, which results in avoidance of consuming a learned tastant. Previously, we showed that levels of the cyclic-AMP-response-element-binding protein (CREB) determine the insular cortical neurons that proceed to encode a conditioned taste memory. In the amygdala and hippocampus, it is shown that CREB and neuronal activity regulate memory allocation and the neuronal mechanism that determines the specific neurons in a neural network that will store a given memory. However, cellular mechanism of memory allocation in the insular cortex is not fully understood. In the current study, we manipulated the neuronal activity in a subset of insular cortical and/or basolateral amygdala (BLA) neurons in mice, at the time of learning; for this purpose, we used an hM3Dq designer receptor exclusively activated by a designer drug system (DREADD). Subsequently, we examined whether the neuronal population whose activity is increased during learning, is reactivated by memory retrieval, using the expression of immediate early gene c-fos. When an hM3Dq receptor was activated only in a subset of IC neurons, c-fos expression following memory retrieval was not significantly observed in hM3Dq-positive neurons. Interestingly, the probability of c-fos expression in hM3Dq-positive IC neurons after retrieval was significantly increased when the IC and BLA were co-activated during conditioning. Our findings suggest that functional interactions between the IC and BLA regulates CTA memory allocation in the insular cortex, which shed light on understanding the mechanism of memory allocation regulated by interaction between relevant brain areas.

Segmentation of an image into superpixel clusters is a necessary part of many imaging pathways. In this article, we describe a new routine for superpixel image segmentation (F-DBSCAN) based on the DBSCAN algorithm that is six times faster than previous existing methods, while being competitive in terms of segmentation quality and resistance to noise. The gains in speed are achieved through efficient parallelization of the cluster search process by limiting the size of each cluster thus enabling the processes to operate in parallel without duplicating search areas. Calculations are performed in large consolidated memory buffers which eliminate fragmentation and maximize memory cache hits thus improving performance. When tested on the Berkeley Segmentation Dataset, the average processing speed is 175 frames/s with a Boundary Recall of 0.797 and an Achievable Segmentation Accuracy of 0.944. [ABSTRACT FROM AUTHOR]

This paper considers the problem of memory allocation for the organization of the LIFO-stack in the algorithm for image segmentation based on growing regions is considered. Segmentation divides the image into regions with identical or similar properties and is the most demanding process for the capacity of RAM. The cultivation of areas begins with the neighborhoods of pre-selected initial growth pixels and uses stacks to store the coordinates of adjacent pixels attached to the cultivated region. Stack loading is maximized when the segment size matches the size of the YX image. In the absence of an expression for the exact determination of the size of the stack, it is possible to guarantee the stable operation of the algorithm for growing regions, eliminating the overflow of the memory allocated for processing if the stack size is assumed equal to YX. However, this approach does not take into account the fact that filling the coordinate stacks is also accompanied by a selection of them, which makesthe stack size always smaller than YX. The article proposes an expression that allows one to increase the accuracy of determining the required size of the LIFO-stack for storing the coordinates of adjacent pixels depending on the image size. The expression takes into account the conditions of the maximum load of the LIFO-stack when: a) the segmentation of the square region with the initial growth pixel in the corner of this region is carried out; b) in the scan window, adjacent pixels are always selected in order with the first selectable pixel located in the corner of the scan window. Using the proposed expression to calculate the required capacity of the LIFO-stack under conditions of its maximum load in the image segmentation algorithm based on growing regions provides a 2-fold reduction in the number of LIFO-stack memory cells.

Summary: A memory allocation anomaly occurs when the allocation of a set of heap blocks imposes an unnecessary overhead on the execution of an application. This overhead is particularly disturbing for high‐performance computing (HPC) applications running on shared resources—for example, numerical simulations running on clusters or clouds—because it may increase either the execution time of the application (contributing to a reduction on the overall efficiency of the shared resource) or its memory consumption (eventually inhibiting its capacity to handle larger problems). In this article, we propose a method for identifying, locating, characterizing and fixing allocation anomalies, and a tool for developers to apply the method. We experiment our method and tool with a numerical simulator aimed at approximating the solutions to partial differential equations using a finite element method. We show that taming allocation anomalies in this simulator reduces both its execution time and the memory footprint of its processes, irrespective of the specific heap allocator being employed with it. We conclude that the developer of HPC applications can benefit from the method and tool during the software development cycle. [ABSTRACT FROM AUTHOR]

I recount some landmark discoveries that initially confirmed the cyclic AMP response element-binding (CREB) protein-memory consolidation and allocation linkages. This work constitutes one of the successes of the field of Molecular and Cellular Cognition (MCC) but is also of interest to philosophers of neuroscience. Two approaches, "mechanism" and "ruthless reductionism", claim to account for this case, yet these accounts differ in one crucial way. I explain this difference and argue that both the experiment designs and discussions of these discoveries by MCC scientists better fit the ruthless reductionist's account. This conclusion leads to further philosophical discussion about how discoveries in cellular/molecular neurobiology integrate with systems neuroscience findings. [ABSTRACT FROM AUTHOR]

Due to large data volume and low latency requirements of modern web services, the use of an in-memory key-value (KV) cache often becomes an inevitable choice (e.g., Redis and Memcached). The in-memory cache holds hot data, reduces request latency, and alleviates the load on background databases. Inheriting from the traditional hardware cache design, many existing KV cache systems still use recency-based cache replacement algorithms, e.g., least recently used or its approximations. However, the diversity of miss penalty distinguishes a KV cache from a hardware cache. Inadequate consideration of penalty can substantially compromise space utilization and request service time. KV accesses also demonstrate locality, which needs to be coordinated with miss penalty to guide cache management. In this article, we first discuss how to enhance the existing cache model, the Average Eviction Time model, so that it can adapt to modeling a KV cache. After that, we apply the model to Redis and propose pRedis, Penalty- and Locality-awareMemory Allocation in Redis, which synthesizes data locality and miss penalty, in a quantitative manner, to guide memory allocation and replacement in Redis. At the same time, we also explore the diurnal behavior of a KV store and exploit long-term reuse. We replace the original passive eviction mechanism with an automatic dump/load mechanism, to smooth the transition between access peaks and valleys. Our evaluation shows that pRedis effectively reduces the average and tail access latencywithminimal time and space overhead. For both real-world and synthetic workloads, our approach delivers an average of 14.0%~52.3% latency reduction over a state-of-the-art penalty-aware cache management scheme, Hyperbolic Caching (HC), and shows more quantitative predictability of performance. Moreover, we can obtain even lower average latency (1.1%~5.5%) when dynamically switching policies between pRedis and HC. [ABSTRACT FROM AUTHOR]

While memories are often thought of as flashbacks to a previous experience, they do not simply conserve veridical representations of the past but must continually integrate new information to ensure survival in dynamic environments. Therefore, ‘drift’ in neural firing patterns, typically construed as disruptive ‘instability’ or an undesirable consequence of noise, may actually be useful for updating memories. In our view, continual modifications in memory representations reconcile classical theories of stable memory traces with neural drift. Here we review how memory representations are updated through dynamic recruitment of neuronal ensembles on the basis of excitability and functional connectivity at the time of learning. Overall, we emphasize the importance of considering memories not as static entities, but instead as flexible network states that reactivate and evolve across time and experience.

It is commonly assumed that memories about experienced stimuli are represented by groups of highly interconnected neurons called cell assemblies. This requires allocating and storing information in the neural circuitry, which happens through synaptic weight adaptations at different types of synapses. In general, memory allocation is associated with synaptic changes at feed-forward synapses while memory storage is linked with adaptation of recurrent connections. It remains, however, largely unknown how memory allocation and storage can be achieved and the adaption of the different synapses involved be coordinated to allow for a faithful representation of multiple memories without disruptive interference between them. In this theoretical study, by using network simulations and phase space analyses, we show that the interplay between long-term synaptic plasticity and homeostatic synaptic scaling organizes simultaneously the adaptations of feed-forward and recurrent synapses such that a new stimulus forms a new memory and where different stimuli are assigned to distinct cell assemblies. The resulting dynamics can reproduce experimental in-vivo data, focusing on how diverse factors, such as neuronal excitability and network connectivity, influence memory formation. Thus, the here presented model suggests that a few fundamental synaptic mechanisms may suffice to implement memory allocation and storage in neural circuitry.

It is commonly assumed that memories about experienced stimuli are represented by groups of highly interconnected neurons called cell assemblies. This requires allocating and storing information in the neural circuitry, which happens through synaptic weight adaptations at different types of synapses. In general, memory allocation is associated with synaptic changes at feed-forward synapses while memory storage is linked with adaptation of recurrent connections. It remains, however, largely unknown how memory allocation and storage can be achieved and the adaption of the different synapses involved be coordinated to allow for a faithful representation of multiple memories without disruptive interference between them. In this theoretical study, by using network simulations and phase space analyses, we show that the interplay between long-term synaptic plasticity and homeostatic synaptic scaling organizes simultaneously the adaptations of feed-forward and recurrent synapses such that a new stimulus forms a new memory and where different stimuli are assigned to distinct cell assemblies. The resulting dynamics can reproduce experimental in-vivo data, focusing on how diverse factors, such as neuronal excitability and network connectivity, influence memory formation. Thus, the here presented model suggests that a few fundamental synaptic mechanisms may suffice to implement memory allocation and storage in neural circuitry. [ABSTRACT FROM AUTHOR]

Hybrid memory systems composed of emerging non-volatile memory (NVM) and DRAM have drawn increasing attention in recent years. To fully exploit the advantages of both NVM and DRAM, a primary goal is to properly place application data on the hybrid memories. Previous studies have focused on page migration schemes to achieve higher performance and energy efficiency. However, those schemes all rely on online page access monitoring (costly), and data migration at the page granularity may cause additional overhead due to DRAM bandwidth contention and maintenance of cache/TLB consistency. In this article, we present Object-level memory Allocation and Migration (OAM) mechanisms for hybrid memory systems. OAM exploits a profiling tool to characterize objects’ memory access patterns at different execution phases of applications, and applies a performance/energy model to direct the initial static memory allocation and runtime dynamic object migration between NVM and DRAM. Based on our newly-developed programming interfaces for hybrid memory systems, application source codes can be automatically transformed via static code instrumentation. We evaluate OAM on an emulated hybrid memory system, and experimental results show that OAM can significantly reduce system energy-delay-product by 61 percent on average compared to a page-interleaving data placement scheme. It can also significantly reduce data migration overhead by 83 and 69 percent compared to the state-of-the-art page migration scheme CLOCK-DWF and 2PP, respectively, while improving application performance by up to 22 and 10 percent. [ABSTRACT FROM AUTHOR]

The insular cortex (IC) is the primary gustatory cortex, and it is a critical structure for encoding and retrieving the conditioned taste aversion (CTA) memory. In the CTA, consumption of an appetitive tastant is associated with aversive experience such as visceral malaise, which results in avoidance of consuming a learned tastant. Previously, we showed that levels of the cyclic-AMP-response-element-binding protein (CREB) determine the insular cortical neurons that proceed to encode a conditioned taste memory. In the amygdala and hippocampus, it is shown that CREB and neuronal activity regulate memory allocation and the neuronal mechanism that determines the specific neurons in a neural network that will store a given memory. However, cellular mechanism of memory allocation in the insular cortex is not fully understood. In the current study, we manipulated the neuronal activity in a subset of insular cortical and/or basolateral amygdala (BLA) neurons in mice, at the time of learning; for this purpose, we used an hM3Dq designer receptor exclusively activated by a designer drug system (DREADD). Subsequently, we examined whether the neuronal population whose activity is increased during learning, is reactivated by memory retrieval, using the expression of immediate early gene c-fos. When an hM3Dq receptor was activated only in a subset of IC neurons, c-fos expression following memory retrieval was not significantly observed in hM3Dq-positive neurons. Interestingly, the probability of c-fos expression in hM3Dq-positive IC neurons after retrieval was significantly increased when the IC and BLA were co-activated during conditioning. Our findings suggest that functional interactions between the IC and BLA regulates CTA memory allocation in the insular cortex, which shed light on understanding the mechanism of memory allocation regulated by interaction between relevant brain areas. [ABSTRACT FROM AUTHOR]

The mammalian brain can store and retrieve memories of related events as distinct memories and remember common features of those experiences. How it computes this function remains elusive. Here, we show in rats that recent memories of two closely timed auditory fear events share overlapping neuronal ensembles in the basolateral amygdala (BLA) and are functionally linked. However, remote memories have reduced neuronal overlap and are functionally independent. The activity of parvalbumin (PV)-expressing neurons in the BLA plays a crucial role in forming separate remote memories. Chemogenetic blockade of PV preserves individual remote memories but prevents their segregation, resulting in reciprocal associations. The hippocampus drives this process through specific excitatory connections with BLA GABAergic interneurons. These findings provide insights into the neuronal mechanisms that minimize the overlap between distinct remote memories and enable the retrieval of related memories separately. [Display omitted] • Hippocampus drives the pattern separation of fear memories in the amygdala • Parvalbumin cells enable the separation of related fear memories in the amygdala • Recent overlapped memories are transformed into segregated remote memories over time Remembering closely related events poses a brain challenge. Each memory must retain its uniqueness while commonalities are recalled. Concina et al. found that hippocampal neurons guide amygdala inhibitory cells, separating overlapped memories. This insight aids understanding of memory segregation, which is compromised in disorders like schizophrenia and post-traumatic stress disorder. [ABSTRACT FROM AUTHOR]