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A new dual-band low-noise amplifier (LNA) operating at L1/E1 1.575 GHz and L5/E5 1.192 GHz center frequencies for global navigation satellite system receivers is proposed. A doubled common-source amplifier architecture is used with a single input, shared gate inductor, and two outputs to split the RF signal into separate RX channels. The main advantage of the proposed circuit is compatibility with widespread multi-band antennas with single RF connectors dedicated to high-precision applications, as well as the possibility to use cheap SAW filters with small footprints to build low-cost, highly accurate GNSS receiver modules. The input and both outputs are well matched to 50 Ω impedance. The LNA is designed with a 110 nm CMOS process, consuming 6.13 mA current from a 1.5 V supply. The measured noise figures and voltage gains of the dual-band LNA are, respectively, NF1/NF5 = 3.23/3.5 dB and G1/G5 = 21.22/18.2 dB in the band of interest for each channel. The measured impedance matching at the input (S11) and output (S22) of the dual-band low-frequency amplifier is as follows: S11_L1 = −23.89, S11_L5 = −8.42, S22_L1 = −12.65, S22_L5 = −15.08. The one-decibel compression points are L1 band PdB1 = −37.71 dBm and L5 band PdB5 = −34.72 dBm, respectively. [ABSTRACT FROM AUTHOR]

This letter presents a 28 GHz balun‐first low noise amplifier (LNA) featuring a wide dB‐linear variable gain range. The architecture of LNA includes three‐stage cascode amplifiers. An integrated balun at the input stage provides RF ESD protection and converts a single‐ended signal to a differential one (S‐to‐D). A transformer‐based dual‐resonant matching network is designed and analyzed to achieve wideband performance. To realize a continuous dB‐linear variable gain range and consistent input/output matching, gain control is implemented in the second stage using a 5‐bit digital‐to‐analog converter (DAC) for a 32 dB gain range. The DAC can generate a nonlinear analog voltage to control the gate of the common‐gate transistor in the second cascode stage, inversely compensating for the nonlinear gain variations of the cascode amplifier. The LNA is fabricated in 65‐nm CMOS process with a core size of 0.154 mm². Measurement results exhibit a maximum gain of 33.5 dB and a minimum noise figure (NF) of 3.65 dB with a 3‐dB bandwidth of 23–29.5 GHz. The measured variable gain range is approximately 32 dB across 32 different gain states, with a linear gain step of ~1 dB per state and an IP1dB ranging from −6.5 dBm to −35.25 dBm. The power consumption is 35.4–48 mW from a 1.2 V supply voltage. [ABSTRACT FROM AUTHOR]

A low-noise amplifier (LNA) design with the operation of concurrent dual-band for Global Navigation Satellite System (GNSS) receivers with single channel is presented in this work. This LNA structure has an inductively degenerated cascode architecture and is pseudo-differential, operating at two frequencies simultaneously (1.2 GHz and 1.57 GHz). Two noise reduction/cancellation techniques, using load capacitor and feedforward path, respectively, are proposed resulting in an excellent improvement in the noise figure (NF). The input matching circuit uses both series and parallel resonant components to enable concurrency. The adopted pseudo-differential structure results in input balun elimination. Inductively degenerated cascode topology provides both input impedance and optimum noise impedance matching. The soundness of the proposed approach has been demonstrated in a 0.18-µm CMOS technology by TSMC. Simulation results show that at 1.2 GHz and 1.57 GHz the LNA achieves −13 dB and −11 dB of input matching, 24.6 dB and 24.7 dB of gain, 1.47 dB and 1.43 dB of NF, respectively. The input-referred 1-dB compression point (IP1dB) is around −16 dBm, while the input-referred third-order intercept point (IIP3) achieves −2.2 dBm at 1.2 GHz and −0.6 dBm at 1.57 GHz. The LNA draws about 13 mA from a 1.8-V supply voltage. [ABSTRACT FROM AUTHOR]

The recent boom in wireless consumer applications has emphasized the requirement for low-cost, highly integrated RF parts. pHEMTs have become the technology of choice for current system requirements. A key requirement for all systems is high reliability components that do not fail or degrade in performance during the life cycle of the product. A confident use of these technologies relies on our capacity to better understand their fault mechanisms, and our ability to deduce related fault models. [ABSTRACT FROM AUTHOR]

This article presents the optimal design of a high-gain, low-noise-figure (NF), highly linear complementary metal–oxide–semiconductor (CMOS) cascode low-noise amplifier (LNA) with inductive source degeneration for a 2.4 GHz ISM band. The evolutionary technique adopted here is the cat swarm optimization (CSO) algorithm. CSO is utilized to minimize the NF. The optimal transistor sizing of the LNA circuit is obtained through the CSO algorithm. Additionally, CSO helps to determine the other component values for the LNA. These parameters are applied to construct the LNA in CADENCE software. The post-layout simulation for the 2.4 GHz LNA results in an IIP3 of −2.44 dBm, NF of 0.303 dB, gain of 17.95 dB, and layout area of 0.66 × 0.65 mm2. The CSO-based design of LNA produces better results as compared to the previous literature regarding NF, gain, and figure of merit (FOM). The designed LNA is useful in Bluetooth, Zigbee, Wi-Fi, and wireless body area network (WBAN) applications. [ABSTRACT FROM AUTHOR]

The designed circuit features a dual-stage Low Noise Amplifier (LNA) in which, a common source (CS) configuration is employed to achieve high gain, while the subsequent stage adopts a Complementary Common Gate (CCG) setup provide the low power consumption. This arrangement ensures that both transistors share the same biasing current, promoting energy efficiency. The two stages are interconnected in a cascade configuration, amplifying the overall gain and concurrently mitigating noise. To facilitate wideband matching in the input stage, a parallel RC feedback mechanism is implemented. Additionally, a pair of mutually coupled inductors in the CS and CCG stages contribute to rendering the input impedance exclusively resistive, concurrently minimizing the overall size of the circuit. All simulations were done using 65 nm CMOS technology in Cadence Virtuoso. The proposed LNA showcases a Noise Figure (NF) of 3.2 dB, a Peak Power Gain (S21) of 19.8 dB, and an input reflection coefficient (S11) of –16.2 dB, spanning a bandwidth of 3.1-6.2 GHz. Operating on a 1V power supply, the proposed LNA demonstrates power efficiency by consuming only 2.8 mW. The overall performance assessment of the LNA is gauged using the Figure of Merit, yielding an obtained value of 18.2. Comparative analysis with other cutting-edge designs is presented in Table 1. [ABSTRACT FROM AUTHOR]

This article presents a low-noise amplifier based on the use of a composite right-left handed transmission line consisting of a single microstrip line and a split ring resonator at the transistor input and output. This design ensures optimum matching over a wide frequency range while eliminating an unwanted frequency band. The circuit is designed to operate at a center frequency of 2.4 GHz while simultaneously eliminating the frequency band around 4.8 GHz, meeting key performance criteria including improved gain, better stability, and significant noise reduction. To achieve these objectives, the transistor used undergoes precise biasing via a DC power supply. In this process, a specifically selected capacitor is arranged in series with a λ/4 transformer. This transformer, in turn, is connected in series to a radial line section. The dimensions of the proposed amplifier are 70 × 34 mm2.For validation purposes, the proposed method was implemented through design, manufacture, and testing. The results obtained show that the proposed low noise amplifier achieves a high gain of 15.27 dB, an input reflection loss S11 of −16.26 dB, an output reflection loss S22 of −13.94 dB, and an inverse isolation S12 of −22.82 dB at 2.4 GHz, with a resonance peak at 4.8 GHz allowing the surrounding frequency band to be eliminated with an attenuation of 77 dB at 4.8 GHz. What's more, the noise figure is kept below 2 dB, with unconditional stability in the desired frequency band.

Summary: In this paper, a vector‐sum phase shifter (VSPS) integrated with a wideband high‐gain low‐noise amplifier (LNA) for Ka‐band phased‐array receivers is presented. The digitally controlled VSPS based on the RF phase shifting architecture consists of a modified I/Q signal generator with additional inductor resonance and a programmable variable gain amplifier (VGA) based on Four 3 × 4 transistor arrays. Besides the reduced parasitic effect of the I/Q signal generator, an Equidistant Contraction Technology (ECT) is used in the VGA, to maintain higher phase shift accuracy of the VSPS. A multistage LNA with series inductor peaking is adopted to fulfill the flat wideband gain, where LC resonance networks are used as interstage matching to compensate for gain roll‐off at a higher frequency. Based on simulations in 65 nm CMOS technology, the presented LNA‐Phase shifter has achieved an average NF of 3.24–3.66 dB, and an average gain of 13.1–23.6 dB. Moreover, an RMS phase error of 1.1–12.6°, an RMS gain error of 4.2–5.6 dB, and an RMS magnitude error of 2.1–2.8 dB are maintained across 27–40 GHz, with a 360° phase shift coverage in steps of approximately 2.8125°. The chip consumes 16.83 mW from a 1.2 V supply voltage, and the occupied area is 0.65 mm2. [ABSTRACT FROM AUTHOR]

This paper presents novel way to achieve fast and accurate Artificial Neural Network (ANN) modeling of Radio Frequency (RF) front end Low Noise Amplifier (LNA). Multilayer perceptron neural network is implemented to model high gain, ultra-low noise pseudomorhic High Electron Mobility Transistor (pHEMT) based LNA. Datasets are developed for input and output that is obtained from the Electro-Magnetic simulator. Different neural networks such as PatternNet, FitNet, and CascadeForwardNet with different algorithms are trained, tested, and compared to learn the behavior of the amplifier, and the best model is analyzed. Neural networks are modeled for LNA S-parameters and NF. It is observed that greater than 99% accuracy is achieved for PatternNet Bayesian regularization algorithm with less number of hidden layers and also it is found that the simulation results are almost similar to the developed ANN. [ABSTRACT FROM AUTHOR]

The design of ultra-wide-band (UWB) low-noise amplifiers (LNAs) entails a large number of design challenges and tradeoffs, which include sustaining good input matching over a wide bandwidth along with finding a proper compromise between various LNA performance metrics, such as gain, bandwidth, noise figure, power, and linearity. This paper presents a design approach for UWB LNAs based on the inversion coefficient (IC). The proposed approach is a graphical design approach where the proper operating point is chosen based on predefined constraints. A complete systematic solution is presented for the problem of UWB input matching with a high degree of analytical accuracy. The design approach is illustrated through the design of two UWB stacked common-gate LNAs in 65 nm technology. The post-layout simulation results show very good agreement with analytical expectations. The first LNA achieves an S 11 better than −8.2 dB over a 27.6 GHz frequency range, a gain of 12.4 dB over a 16.5 GHz bandwidth, a minimum noise-figure, NF, of 4.5 dB, and an I I P 3 of −5.2 dBm while consuming only 530 μ W. The second LNA achieves an S 11 better than −15 dB over an 8.8 GHz frequency range, a gain of 12.5 dB over a 6.8 GHz bandwidth, a minimum NF of 4 dB, and an I I P 3 of −4.3 dBm while consuming only 550 μ W. [ABSTRACT FROM AUTHOR]

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This paper presents a broadband millimeter-wave (mm-Wave) low noise amplifier (LNA) designed in a 22 nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology. Electromagnetic (EM) simulations suggest that the LNA has a 3-dB bandwidth (BW) from 17.8 to 42.4 GHz and a fractional bandwidth (FBW) of 81.7%, covering the key frequency bands within the mm-Wave 5G FR2 band, with its noise figure (NF) ranging from 2.9 to 4.9 dB, and its input-referred 1-dB compression point (IP1dB) of −17.9 dBm and input-referred third-order intercept point (IIP3) of −8.5 dBm at 28 GHz with 15.8 mW DC power consumption (PDC). Using the FOM (figure-of-merit) developed for broadband LNAs (FOM = 20 × log((Gain[V/V] × S21-3 dB-BW [GHz])/(PDC [mW] × (F-1)))), this LNA achieves a competitive FOM (FOM = 18.9) among reported state-of-the-art mm-Wave LNAs in the literature. [ABSTRACT FROM AUTHOR]

This paper presents a BiCMOS low-noise amplifier (LNA) operating at G-band (140 to 220 GHz) that is robust against harsh operation conditions, namely large temperature variations and radiation exposure. A SiGe technology (IHP’s 0.13- $\mathrm {\mu }$ m SG13G2) has been used for the amplifier design, due to its suitability for millimeter wave (mmW) frequencies and its built-in tolerance to total ionizing dose (TID) radiation. To address the impact of temperature variations on HBTs, the negative temperature dependence of the gain is compensated with a positive temperature dependent collector current, generated by the proposed on-chip and compact (0.0035 mm2) biasing circuit. It has a negligible degradation on the LNA performance, which shows a measured performance comparable with the state of the art with a minimum noise figure (NF) of 9 dB and a gain of 18.1 dB at room temperature, centered around 195 GHz and with a 3-dB bandwidth of 25 GHz. The measured gain and noise figure variations over a −20°C to 80°C temperature range are ±1.1 dB and ±1.5 dB, respectively. Finally, an experiment to study the TID radiation response of mmW LNAs is carried out. Fabricated samples are exposed to 250 krad(Si), 1.5 Mrad(Si) and 2 Mrad(Si), exhibiting a variation smaller than 1 dB in both gain and noise figure.

This article presents a receiver for narrowband IoT (NB-IoT) that eliminates the need for an RF local oscillator (LO) via a subsampling architecture. A pseudo-balun Q-boosted LNA provides sharp anti-aliasing filtering with a noise figure (NF) of 5.6 dB. A direct-coupling derivative superposition technique where low- $V_{t}$ and thick-gate transistors with opposite nonlinear characteristics are combined to improve the measured IIP3 by 7 dB to −18 dBm with little NF overhead. Fabricated in 65-nm CMOS, the entire receiver, including the LNA, an S/H circuit, and a 10-bit SAR ADC, consumes only 0.69 mW while meeting NB-IoT specifications.

This article presents an innovative approach that harnesses neural networks (NN) to eliminate non-linear distortion in low-noise amplifier (LNA) within multi-channel direct sampling receivers (MDSR). Current mainstream methods, such as those relying on memory polynomial or Volterra models, face challenges in effectively addressing the demand for LNA linearization modeling, particularly in scenarios with high fractional bandwidth and stochastic inputs. The proposed method incorporates two key technologies to support NN. First, using input signals with specific frequency properties to derive ground truth values by isolating distortion components from the LNA output signals in the frequency domain, simplifies the process of acquiring training samples and enhances accuracy. Additionally, by utilizing mathematical characteristics of LNA output signals, such as instantaneous rate of change, magnitude, and non-uniformly sampled memory points, it performs feature engineering to simultaneously reduce the complexity of the NN and enhance its generalization capabilities. Evaluation with the LNA (ZFL-500LN+) demonstrates outstanding performance in suppressing multiple harmonics and inter-modulation components, which approaches the quantization noise floor of the analog-to-digital converter, especially harmonic reduction of up to 46 dB in the worst distorted channel. These results show the potential of this method to enhance the performance of MDSR.

Metastasis-associated lung adenocarcinoma transcript 1 (MALAT1) and multiple endocrine neoplasia-β (MENβ) are two long noncoding RNAs upregulated in multiple cancers, marking these RNAs as therapeutic targets. While traditional small-molecule and antisense-based approaches are effective, we report a locked nucleic acid (LNA)-based approach that targets the MALAT1 and MENβ triple helices, structures comprised of a U-rich internal stem-loop and an A-rich tract. Two LNA oligonucleotides resembling the A-rich tract (i.e., A9GCA4) were examined: an LNA (L15) and a phosphorothioate LNA (PS-L15). L15 binds tighter than PS-L15 to the MALAT1 and MENβ stem loops, although both L15 and PS-L15 enable RNA•LNA-RNA triple-helix formation. Based on UV thermal denaturation assays, both LNAs selectively stabilize the Hoogsteen interface by 5–13 °C more than the Watson–Crick interface. Furthermore, we show that L15 and PS-L15 displace the A-rich tract from the MALAT1 and MENβ stem loop and methyltransferase-like protein 16 (METTL16) from the METTL16-MALAT1 triple-helix complex. Human colorectal carcinoma (HCT116) cells transfected with LNAs have 2-fold less MALAT1 and MENβ. This LNA-based approach represents a potential therapeutic strategy for the dual targeting of MALAT1 and MENβ. [ABSTRACT FROM AUTHOR]

This paper presents a highly integrated C-band RF transceiver front-end design consisting of two Single Pole Double Throw (SPDT) transmit/receive (T/R) switches, a Low Noise Amplifier (LNA), and a Power Amplifier (PA) for Ultra-Wideband (UWB) positioning system applications. When fabricated using a 0.25 μm GaAs pseudomorphic high electron mobility transistor (pHEMT) process, the switch is optimized for system isolation and stability using inductive resonance techniques. The transceiver front-end achieves overall bandwidth expansion as well as the flat noise in receive mode using the bandwidth expansion technique. The results show that the front-end modules (FEM) have a typical gain of 22 dB in transmit mode, 18 dB in receive mode, and 2 dB noise in the 4.5–8 GHz band, with a chip area of 1.56 × 1.46 mm2. Based on the available literature, it is known that the proposed circuit is the most highly integrated C-band RF transceiver front-end design for UWB applications in the same process. [ABSTRACT FROM AUTHOR]

When designing a narrow band Internet of things (NB-IoT) system, the main tasks are to determine the boundary parameters of the system nodes and check its performance under various conditions. Automatic design tools make it possible to achieve reliable results even at the modeling stage, which helps to accelerate the development and implementation of new technologies in the microelectronic industry, including the industrial Internet of things. This paper presents aspects of designing an NB-IoT system. Analytical calculations of the receiving path are carried out using a debugging system in the context of radio wave propagation in an enclosed space in accordance with the specifications of the 5G 3GPP standard. Based on the results of analytical calculations on signal propagation in a closed space for a prototype of a subscriber device, general requirements for the development of an active node of a low-noise amplifier (LNA) of the receiving path of an NB-IoT transceiver are formulated. Based on the requirements and design standards of the 180-nm CMOS process, a prototype of an LNA is developed for operation as part of an NB-IoT transceiver of a subscriber terminal. The prototype low noise amplifier is designed in three stages and has a noise figure of 1.7 dB in the n7 frequency range with a gain of 25 dB. Digital CMOS libraries are adapted to unify and reduce the cost of the development process of analog nodes of the transceiver path, in this case an LNA. [ABSTRACT FROM AUTHOR]

This article presents a power-efficient low noise amplifier (LNA) with high gain and low noise figure (NF) dedicated to satellite communications at a frequency of 435 MHz. LNAs’ gain and NF play a significant role in the designs for satellite ground terminals seeking high amplification and maintaining a high signal-to-noise ratio (SNR). The proposed design utilized the transistor (BFP840ESD) to achieve a low NF of 0.459 dB and a high-power gain of 26.149 dB. The study carries out the LNA design procedure, from biasing the transistor, testing its stability at the operation frequency, and finally terminating the appropriate matching networks. In addition to the achieved high gain and low NF, the proposed LNA consumes as low power as only 2 mW. [ABSTRACT FROM AUTHOR]

In this study, a dual-band low-noise amplifier (LNA) was implemented by applying a transformer-based neutralization technology to the W-band. Incorporating the neutralization technique was difficult owing to performance degradation in the W-band. However, circuit performance was enhanced thanks to the layout optimization of transformer-based neutralization networks, and the improved operation was confirmed in the W-band. The neutralization technique was implemented in four stages with a 0.1-μm gallium arsenide (GaAs) pseudomorphic high-electron-mobility-transistor monolithic microwave integrated circuit LNA. The LNA showed small signal gains of 20.3 dB and 21.7 dB and noise figures of 5.0 dB and 6.4 dB (at 84 GHz and 96 GHz, respectively) while consuming 46 mW from a 1-V supply.

Millimeter Wave (mm-wave) technology is a prerequisite to ensure ubiquitous wireless communication, given the rapid growth of the Internet of Things (IoT) infrastructure that integrates emerging technologies such as virtual reality (VR), artificial intelligence (AI), etc. However, to ensure the future growth and acceptance of this technology, a highly efficient mm-wave compatible transceiver hardware is essential to be developed. A low noise amplifier (LNA) is one of the modules that directly influences the performance of an IoT transceiver. Numerous approaches have thus far been deployed in LNA design, such as differential cascode topology, active inductor, embedded input balun, transformer-based feedback, current reuse, stacked structure, and body biasing, to standardize various parameters e.g. die area, gain, noise figure, linearity, and power efficiency. Although complementary metal–oxide–semiconductor (CMOS) technology-based current LNA architectures in the mm-wave range suffer from substrate losses and device parasitic, it is regarded as a competitive solution for THz communication due to its inherent benefits of low-cost integrity, which promotes CMOS LNA design as an emerging research topic. This review presents several CMOS LNA architectures and perceives the adjustments of circuit topologies to ratify LNA structures in mm-wave applications. Furthermore, various state-of-the-art LNA design features are compared to envision CMOS LNA design directions and identify apposite circuit techniques suitable for the imminent 6G communication protocol. Therefore, this review will serve as a comparative study and reference for the future LNA design for the mm-wave sensor transceiver applications.

Spinal muscular atrophy (SMA) is a devastating neurodegenerative disease caused by mutations in the SMN1 gene. Existing therapies demonstrate positive results on SMA patients but still might be ameliorated in efficacy and price. In the presented study we designed antisense oligonucleotides (AONs), targeting intronic splicing silencer sites, some were modified with 2′-O-methyl, others with LNA. The AONs have been extensively tested in different concentrations, both individually and combined, in order to effectively target the ISS-N1 and A+100G splicing silencer regions in intron 7 of the SMN2 gene. By treating SMA-cultured fibroblasts with certain AONs, we discovered a remarkable increase in the levels of full-length SMN transcripts and the number of nuclear gems. This increase was observed to be dose-dependent and reached levels comparable to those found in healthy cells. When added to cells together, most of the tested molecules showed a remarkable synergistic effect in correcting splicing. Through our research, we have discovered that the impact of oligonucleotides is greatly influenced by their length, sequence, and pattern of modification. [ABSTRACT FROM AUTHOR]

This paper proposes a low-noise amplifier (LNA) for terahertz communication systems. The amplifier is designed based on 90 nm InP high-electron-mobility transistor (HEMT) technology. In order to achieve high gain of LNA, the proposed amplifier adopts a five-stage amplification structure. At the same time, the use of staggered tuning technology has achieved a large bandwidth of terahertz low-noise amplification. In addition, capacitors are used for interstage isolation, sector lines are used for RF bypass, and Microstrip is used to design matching circuits. The entire LNA circuit was validated using accurate electromagnetic simulation. The simulation results show that at 140 GHz, the small signal gain is 25 dB, the noise figure is 4.4 dB, the input 1 dB compression point is −19 dBm, and the 3 dB bandwidth reaches 60 GHz (110–170 GHz), which validates the effectiveness of the design. [ABSTRACT FROM AUTHOR]

This study presents a wideband low-noise amplifier (LNA) chip that covers the frequency range of 2.8–10 GHz using UMC's 0.18 μm complementary metal–oxide–semiconductor technology. The LNA adopts a current reuse architecture to reduce power consumption. This study improves linearity using multiple gated transistors and inductance degeneration techniques. In addition to enhancing linearity, the proposed technique also achieves high gain and broadband. The DC power dissipation of this LNA was 18 mW with a 1.5 V supply voltage. The measured minimum noise figure was 4.5 dB. Furthermore, the gain, input third-order intercept point, and total chip size of the LNA were 10.8–13.8 dB, 2 dBm, and 1.18 × 1.19 mm2, respectively. The proposed LNA measurements exhibit high linearity, high gain, an optimal reflection coefficient, and a low supply voltage. [ABSTRACT FROM AUTHOR]

Analyzing cellular structures and the relative location of molecules is essential for addressing biological questions. Super-resolution microscopy techniques that bypass the light diffraction limit have become increasingly popular to study cellular molecule dynamics in situ. However, the application of super-resolution imaging techniques to detect small RNAs (sRNAs) is limited by the choice of proper fluorophores, autofluorescence of samples, and failure to multiplex. Here, we describe an sRNA-PAINT protocol for the detection of sRNAs at nanometer resolution. The method combines the specificity of locked nucleic acid probes and the low background, precise quantitation, and multiplexable characteristics of DNA Point Accumulation for Imaging in Nanoscale Topography (DNA-PAINT). Using this method, we successfully located sRNA targets that are important for development in maize anthers at sub-20 nm resolution and quantitated their exact copy numbers. Graphic abstract: Multiplexed sRNA-PAINT. Multiple Vetting and Analysis of RNA for In Situ Hybridization (VARNISH) probes with different docking strands (i.e., a, b, …) will be hybridized to samples. The first probe will be imaged with the a* imager. The a* imager will be washed off with buffer C, and then the sample will be imaged with b* imager. The wash and image steps can be repeated sequentially for multiplexing.

RNA structural elements occur in numerous single-stranded positive-sense RNA viruses. The stem-loop 2 motif (s2m) is one such element with an unusually high degree of sequence conservation, being found in the 3' untranslated region (UTR) in the genomes of many astroviruses, some picornaviruses and noroviruses, and a variety of coronaviruses, including severe acute respiratory syndrome coronavirus (SARS-CoV) and SARS-CoV-2. The evolutionary conservation and its occurrence in all viral subgenomic transcripts imply a key role for s2m in the viral infection cycle. Our findings indicate that the element, while stably folded, can nonetheless be invaded and remodeled spontaneously by antisense oligonucleotides (ASOs) that initiate pairing in exposed loops and trigger efficient sequence-specific RNA cleavage in reporter assays. ASOs also act to inhibit replication in an astrovirus replicon model system in a sequence-specific, dose-dependent manner and inhibit SARS-CoV-2 replication in cell culture. Our results thus permit us to suggest that the s2m element is readily targeted by ASOs, which show promise as antiviral agents. IMPORTANCE The highly conserved stem-loop 2 motif (s2m) is found in the genomes of many RNA viruses, including SARS-CoV-2. Our findings indicate that the s2m element can be targeted by antisense oligonucleotides. The antiviral potential of this element represents a promising start for further research into targeting conserved elements in RNA viruses.

A double balanced passive mixer-based receiver operating in the 3-5 GHz UWB for medical applications is described in this paper. The receiver front-end circuit is composed of an inductorless low noise amplifier (LNA) followed by a fully differential voltage-driven double-balanced passive mixer. A duty cycle of 25% was chosen to eliminate overlap between LO signals, thereby improving receiver linearity. The LNA realizes a gain of 25.3 dB and a noise figure of 2.9 dB. The proposed receiver achieves an IIP3 of 3.14 dBm, an IIP2 of 17.5 dBm and an input return loss (S11) below -12.5dB. Designed in 0.18μm CMOS technology, the proposed mixer consumes 0.72pW from a 1.8V power supply. The designed receiver demonstrated a good ports isolation performance with LO_IF isolation of 60dB and RF_IF isolation of 78dB.

This paper presents a broadband millimeter-wave (mm-Wave) low noise amplifier (LNA) designed in a 22 nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology. Electromagnetic (EM) simulations suggest that the LNA has a 3-dB bandwidth (BW) from 17.8 to 42.4 GHz and a fractional bandwidth (FBW) of 81.7%, covering the key frequency bands within the mm-Wave 5G FR2 band, with its noise figure (NF) ranging from 2.9 to 4.9 dB, and its input-referred 1-dB compression point (IP1dB) of −17.9 dBm and input-referred third-order intercept point (IIP3) of −8.5 dBm at 28 GHz with 15.8 mW DC power consumption (PDC). Using the FOM (figure-of-merit) developed for broadband LNAs (FOM = 20 × log((Gain[V/V] × S21-3 dB-BW [GHz])/(PDC [mW] × (F-1)))), this LNA achieves a competitive FOM (FOM = 18.9) among reported state-of-the-art mm-Wave LNAs in the literature.

The current research paper presents a design of a mutually coupled cascode Common Gate Common Source (CG-CS) Low Noise Amplifier (LNA) using current reuse technique. The proposed design provides a significant improvement in the gain and noise performance of the LNA, while also reducing power consumption. Mutually coupled inductors help in reducing the size of the circuit while transformer connected at the output provide output impedance matching. Proposed LNA simulated for the 4–14 GHz RF frequency. Mathematical analysis of proposed LNA has been analyzed using the small signal model henceforth input impedance; gain and Noise Figure (NF) have been derived from it. The design and simulation results show that the proposed LNA design with current reuse technique achieved a maximum gain of 17.87 dB, minimum NF of 5.45 dB, and input reflection coefficient less than –10 dB for the 10 GHz bandwidth. These results indicate a significant improvement in the overall performance of the LNA compared to conventional designs as Figure of Merit (FoM) is 17.34. [ABSTRACT FROM AUTHOR]

In this research, $\Gamma $ -gated AlGaN/GaN HEMTs with different layout designs and heights of gate stems were fabricated to investigate their impacts on the noise performance in the Ka-band. First, devices with 4 types of gate peripheries were prepared to optimize the layout structure for best noise performance since the values of parasitic capacitance and resistance, which are detrimental to the noise characteristic, vary as the gate widths and the number of fingers change. The device with gate width of $4\times 50\,\,\mu {\mathrm{ m}}$ achieved the optimal noise performance, minimum noise figure (NFmin) of 1.5 dB and associated gain of 6.2 dB at 28 GHz. Next, devices with different gate stem heights were fabricated following the $4\times 50\,\,\mu {\mathrm{ m}}$ layout pattern. The raised gate structure was applied to reduce the parasitic capacitance of the device for RF power performance enhancement, but a taller gate stem unfortunately results in the increment of gate resistance. Therefore, the impact of stem height on NFmin remains unknown. According to the experiment results, the device with a stem height of 200 nm stands out to be a viable compromise for the noise and output power performance in the Ka-band, thus providing a positive outlook for the feasibilities of single-chip circuit integration of both LNA and PA at millimeter-wave spectrum.

Oscillation-based testing (OBT) and Oscillation-based built-in self-testing (OBIST) circuits enable detection of catastrophic faults in analogue and RF circuits, but both are sensitive to process, voltage and temperature (PVT) variation. This paper investigates 15 OBT and OBIST feature extraction strategies, and four approaches to threshold selection, by calculating figure-of-merit (FOM) across PVT variation. This is done using a 2.4 GHz LNA in $0.35 \mu \mathrm{m}$ CMOS as DUT. Of the 15 feature extraction approaches, the OBT approaches are found more effective, with some benefit gained from switched-state detection. Of the four approaches to threshold selection (nominal-ranged static thresholds, extreme-range static thresholds, temperature dynamic thresholds, and simple noise-filtered tone detection), dynamic thresholds resulted in the highest average FoM of 0.919, with the best FoM of 0.952, with a corresponding probability of test escape $P\left(T_E\right)$ and yield loss $P\left(Y_L\right)$ of $5 \cdot 10^{-2}$ and $1.89 \cdot 10^{-2}$ respectively but requires accurate temperature measurement. Extreme static threshold selection resulted in a comparable average FoM of 0.912, but with less susceptibility to process variation and without the need for temperature measurement. Binary detection of a noise-filtered oscillating tone is found the least complex approach, with an average FoM of 0.891.