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This study aimed to compare the effects of two types of drip irrigation line design on cotton yield, water use, and net returns. The experiments were carried out in the arid region of Xinjiang, Northwest China, during 2009-2010 growing years. The two types of lateral placement are commonly used by the local farmers in the area: double lines (two laterals controlling four rows) and single line designs (one lateral controlling four rows). The results indicated that less irrigation water was applied by single line compared with double lines design. This implies that more irrigation water could be saved using single line, by reducing the water consumption of cotton. The emergence rates for double lines were 2 and 6% higher than those for single line design in 2009 and 2010. The seed cotton yields for double lines design were 5.76 and 6.41 Mg ha(-1) which were 13 and 9% higher than for single line design in 2009 and 2010, respectively. Single lines could however lower the investment cost compared to double lines, which produced 10 and 7% more net income in 2009 and 2010, respectively. By contrast, the double lines was more profitable and suitable for the farmers in Northwest China than single line design.

In the last decade the power consumption of electronic devices has increased for both static and active components. Following the Dennard's scaling rule, as long as the transistor sizes are reduced then the supply voltage (VDD) can also be scaled in order to increase the area density and maintain or improve the performances. However, scaling VDD and thus shifting the threshold voltage (Vth) of 60mV in a metal-oxide semiconductor field-effect transistor (MOSFET) increases the OFF state current (Ioff ) by a factor of 10 in the ideal case. The reason for this is that the inverse subthreshold slope (SS) in an ideal MOSFET is limited by the thermionic emission of electrons over a potential barrier, which has an intrinsic physical limit of 60mV/decade. To overcome this limit, novel device concepts have been proposed and the tunnel field-effect transistor (TFET) is one of the most promising because it resembles a MOSFET and should enable to achieve sub-60mV/dec SS, low Ioff and small VDD. The aim of this thesis is to investigate the potential of TFETs by the fabrication and characterization of InAs/Si as p-channel and InAs/GaSb as n-channel device for a complementary TFET technology. III-V nanowires are grown via metal-organic chemical vapor deposition (MOCVD) and are integrated on Si(100) substrates using a novel technique called template-assisted selective epitaxy (TASE), which enables the fabrication of vertical and lateral III-V hetero-structure TFETs. Sub-40nm nanowire cross-section InAs/Si p-TFETs and InAs/GaSb n-TFETs in-plane on Si are demonstrated for the first time. The InAs/Si p-TFETs exhibit state-of-the art performances with an ON state current (Ion) of 4uA/um at VGS=VDS=-0.5V, ON/OFF ratio of 1x10E5 with SSavg of 70-80mV/dec at room temperature. The InAs/GaSb n-TFETs have an order of magnitude larger Ion but the SS is limited by the non-optimized gate-stack on InAs channel and by the depletion of the undoped GaSb source. Different operation regimes of TFETs are investigated by temperature-dependent measurements,Wentzel-Kramers-Brillouin (WKB) modeling and TCAD simulations, indicating that the switching region for InAs/Si is dominated by the presence of traps at the hetero-junction. The abruptness of the band-edges in InAs/GaSb is studied by the extraction of the conductance slope in fabricated p-n and p-i-n tunnel diodes.