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In an ever-growing terahertz market, BiCMOS technologies have reached cut-off frequencies beyond 0.5 THz. These dynamic performances are achieved thanks to the current technological improvements in SiGe heterojunction bipolar transistors (HBTs). However, these increased performances lead to a shift of the transistors bias point closer to, or even beyond, the conventional safe-operating-area (SOA). As a consequence, several "parasitic" physical effects are encountered such as impact-ionization or self-heating which can potentially activate failure mechanisms, hence limiting the long-term reliability of the electric device. In the framework of this thesis, we develop an approach for the description and the modeling of hot-carrier degradation occurring in SiGe HBTs when operating near the SOA edges. The study aims to provide an in-depth characterization of transistors operating under static and dynamic operating conditions. Based on these measurements results, a compact model for the impact-ionization and the self-heating has been proposed, ultimately allowing to extend the validity domain of a commercially available compact model (HiCuM). Considering the operation as close as possible to the SOA, an aging campaign was conducted to figure out the physical origin behind such failure mechanism. As a result, it has been demonstrated that hot-carrier degradation leads to the creation of trap densities at the Si/SiO2interface of the emitter-base spacer which induces an additional recombination current in the base. A compact model integrating aging laws (HiCuM-AL) was developed to predict the evolution of the transistor/circuit electrical parameters through an accelerated aging factor. For ease of use in computer-aided design (CAD) tools, the aging laws have been scaled according to the geometry and architecture of the emitter-base spacer. The model has demonstrated its robustness and its accuracy for different SiGe HBT technologies under various aging conditions. In addition, a study on the reliability of several integrated circuits has been performed leading to a precise location of the most sensitive regions to the hot-carrier degradation mechanism. Thus, the HiCuM-AL model paves the way to perform circuit simulations optimizing the mm-wave circuit design not only in term of sheer performances but also in term of long-term reliability.; Afin de répondre au marché florissant des applications térahertz, les filières BiCMOS atteignent désormais des fréquences de coupure supérieures à 0,5 THz. Ces performances dynamiques sont obtenues grâce aux améliorations technologiques apportées aux transistors bipolaires à hétérojonction (TBH) SiGe. Toutefois, cette montée en fréquence à entraîner un décalage du point de polarisation des transistors au plus proche, voir au-delà, de l’aire de sécurité de fonctionnement (SOA). En conséquence, de nombreux effets physiques « parasites » sont présents tel que l’ionisation par impact ou bien l’auto-échauffement pouvant potentiellement activer des mécanismes de défaillance et ainsi limiter la fiabilité à long terme du transistor. Dans le cadre de cette thèse, nous proposons une approche pour la description et la modélisation de la dégradation par porteurs chauds au sein des TBH SiGe fonctionnant aux frontières de la SOA. L’étude est basée sur une caractérisation approfondie en conditions statiques et dynamiques des transistors. Du fait de ses résultats de mesures, une modélisation de l’ionisation par impact et de l’auto-échauffement a été proposé permettant d’étendre, avec précision, le domaine de validité des modèles compact commerciaux (HiCuM). Au-vu du fonctionnement aux limites de la SOA, une campagne de vieillissement a été mise en place afin de mieux cerner l’origine physique de ce mécanisme de défaillance. De ce fait, il a été démontré que la dégradation par porteurs chauds entraîne la création de densités de pièges au niveau de l’interface Si/SiO2del’espaceur émetteur-base induisant un courant de recombinaison supplémentaire dans la base. Un modèle compact intégrant des lois de vieillissement (HiCuM-AL) a été développé prédisant l’évolution des paramètres électriques d’un transistor ou d’un circuit au travers d’un facteur de vieillissement accéléré. Afin de faciliter son utilisation dans des outils de conception assistée par ordinateur (CAO), les lois de vieillissement ont été adaptées en fonction de la géométrie et de l’architecture de l’espaceur émetteur-base. Le modèle a démontré sa robustesse et sa précision pour plusieurs technologies de TBH SiGe et, ce, pour différentes conditions de vieillissement. De plus, une étude de la fiabilité de plusieurs architectures de circuits intégrés a été réalisé menant à une localisation précise des régions les plus sensibles au mécanisme de dégradation par porteurs chauds. Le modèle HiCuM-AL ouvre ainsi la voie à des simulations optimisées pour la conception de circuits millimétriques en termes de performances, mais aussi de fiabilité à long terme.

In this article, we investigate the impact of the hot carrier (HC) aging on the performance of nanoscale n-channel triple-gate junctionless MOSFETs with channel length varying from 95 down to 25 nm. The devices were electrically stressed in the ON-state region of operation at fixed gate voltage ${V}_{g} = {1.8}$ V and drain bias ${V}_{d} = {1.8}$ V, with the stress time being a variable parameter. The device degradation was monitored through the relative change with stress time of the threshold voltage, subthreshold swing, linear drain current, low-field mobility, series resistance, and gate current. For relatively long-channel transistors ( ${L} = {95}$ nm), the threshold voltage and the subthreshold swing remain almost unchanged, whereas the ON-state drain current is degraded showing a good correlation with the series resistance degradation, caused by HC-induced damage in the drain region. For short-channel transistor ( ${L} = {45}$ nm), the HC-induced damage is extended in the channel region: interface traps are generated, exhibiting good correlation with both threshold voltage and low-field mobility degradations. For the very short-channel device ( ${L} = {25}$ nm), after long stress time, the HC-induced interface degradation is severe, causing a continuous increase of the ideality factor with increasing the gate voltage.

In an ever-growing terahertz market, BiCMOS technologies have reached cut-off frequencies beyond 0.5 THz. These dynamic performances are achieved thanks to the current technological improvements in SiGe heterojunction bipolar transistors (HBTs). However, these increased performances lead to a shift of the transistors bias point closer to, or even beyond, the conventional safe-operating-area (SOA). As a consequence, several "parasitic" physical effects are encountered such as impact-ionization or self-heating which can potentially activate failure mechanisms, hence limiting the long-term reliability of the electric device. In the framework of this thesis, we develop an approach for the description and the modeling of hot-carrier degradation occurring in SiGe HBTs when operating near the SOA edges. The study aims to provide an in-depth characterization of transistors operating under static and dynamic operating conditions. Based on these measurements results, a compact model for the impact-ionization and the self-heating has been proposed, ultimately allowing to extend the validity domain of a commercially available compact model (HiCuM). Considering the operation as close as possible to the SOA, an aging campaign was conducted to figure out the physical origin behind such failure mechanism. As a result, it has been demonstrated that hot-carrier degradation leads to the creation of trap densities at the Si/SiO2interface of the emitter-base spacer which induces an additional recombination current in the base. A compact model integrating aging laws (HiCuM-AL) was developed to predict the evolution of the transistor/circuit electrical parameters through an accelerated aging factor. For ease of use in computer-aided design (CAD) tools, the aging laws have been scaled according to the geometry and architecture of the emitter-base spacer. The model has demonstrated its robustness and its accuracy for different SiGe HBT technologies under various aging conditions. In addition, a study on the reliability of several integrated circuits has been performed leading to a precise location of the most sensitive regions to the hot-carrier degradation mechanism. Thus, the HiCuM-AL model paves the way to perform circuit simulations optimizing the mm-wave circuit design not only in term of sheer performances but also in term of long-term reliability., Afin de répondre au marché florissant des applications térahertz, les filières BiCMOS atteignent désormais des fréquences de coupure supérieures à 0,5 THz. Ces performances dynamiques sont obtenues grâce aux améliorations technologiques apportées aux transistors bipolaires à hétérojonction (TBH) SiGe. Toutefois, cette montée en fréquence à entraîner un décalage du point de polarisation des transistors au plus proche, voir au-delà, de l’aire de sécurité de fonctionnement (SOA). En conséquence, de nombreux effets physiques « parasites » sont présents tel que l’ionisation par impact ou bien l’auto-échauffement pouvant potentiellement activer des mécanismes de défaillance et ainsi limiter la fiabilité à long terme du transistor. Dans le cadre de cette thèse, nous proposons une approche pour la description et la modélisation de la dégradation par porteurs chauds au sein des TBH SiGe fonctionnant aux frontières de la SOA. L’étude est basée sur une caractérisation approfondie en conditions statiques et dynamiques des transistors. Du fait de ses résultats de mesures, une modélisation de l’ionisation par impact et de l’auto-échauffement a été proposé permettant d’étendre, avec précision, le domaine de validité des modèles compact commerciaux (HiCuM). Au-vu du fonctionnement aux limites de la SOA, une campagne de vieillissement a été mise en place afin de mieux cerner l’origine physique de ce mécanisme de défaillance. De ce fait, il a été démontré que la dégradation par porteurs chauds entraîne la création de densités de pièges au niveau de l’interface Si/SiO2del’espaceur émetteur-base induisant un courant de recombinaison supplémentaire dans la base. Un modèle compact intégrant des lois de vieillissement (HiCuM-AL) a été développé prédisant l’évolution des paramètres électriques d’un transistor ou d’un circuit au travers d’un facteur de vieillissement accéléré. Afin de faciliter son utilisation dans des outils de conception assistée par ordinateur (CAO), les lois de vieillissement ont été adaptées en fonction de la géométrie et de l’architecture de l’espaceur émetteur-base. Le modèle a démontré sa robustesse et sa précision pour plusieurs technologies de TBH SiGe et, ce, pour différentes conditions de vieillissement. De plus, une étude de la fiabilité de plusieurs architectures de circuits intégrés a été réalisé menant à une localisation précise des régions les plus sensibles au mécanisme de dégradation par porteurs chauds. Le modèle HiCuM-AL ouvre ainsi la voie à des simulations optimisées pour la conception de circuits millimétriques en termes de performances, mais aussi de fiabilité à long terme.

Hot-carriers, that is, charge carriers with an effective temperature higher than that of the lattice, may contribute to the high power conversion efficiency (PCE) shown by perovskite-based solar cells (PSCs), which are now competitive with silicon solar cells. Hot-carriers lose their excess energy in very short times, typically in a few picoseconds after excitation. For this reason, the carrier dynamics occurring on this time scale are extremely important in determining the participation of hot-carriers in the photovoltaic process. However, the stability of PSCs over time still remains an issue that calls for a solution. In this work, we demonstrate that the insertion of graphene flakes into the mesoscopic TiO2 scaffold leads to stable values of carrier temperature. In PSCs aged over 1 week, we indeed observe that in the graphene-free perovskite cells the carrier temperature decreases by about 500 K from 1800 to 1300 K, while the graphene-containing cell shows a reduction of less than 200 K after the same aging time delay. The stability of the carrier temperature reflects the stability of the perovskite nanocrystals embedded in the mesoporous graphene-TiO2 layer. Our results, based on femtosecond transient absorption measurements, show that the insertion of graphene can be beneficial for the design of stable PSCs with the aim of exploiting the hot-carrier contribution to the PCE of the PSCs.

Graphene-based photodetectors have demonstrated mechanical flexibility, large operating bandwidth, and broadband spectral response. However, their linear dynamic range (LDR) is limited by graphene's intrinsichot-carrier dynamics, which causes deviation from a linear photoresponse at low incident powers. At the same time, multiplication of hot carriers causes the photoactive region to be smeared over distances of a few micro-meters, limiting the use of graphene in high-resolution applications. We present a novel method for engineer-ing photoactive junctions in FeCl3-intercalated graphene using laser irradiation. Photocurrent measured at these planar junctions shows an extraordinary linear response with an LDR value at least 4500 times larger than that of other graphene devices (44 dB) while maintaining high stability against environmental contamination without the need for encapsulation. The observed photoresponse is purely photovoltaic, demonstrating complete quenching of hot-carrier effects. These results pave the way toward the design of ultrathin photode-tectors with unprecedented LDR for high-definition imaging and sensing., 44 pages, includes supplementary

International audience; The hot-carrier (HC) degradation of short-channel n-FinFETs is investigated. The experiments indicate that interface trap generation over the entire channel length, which is enhanced near the drain region, is the main degradation mechanism. The relation of the hot-carrier degradation with stress time, channel length, fin width and bias stress voltages at the drain and gate electrodes is presented. A HC degradation compact model is proposed, which is experimentally verified. The good accuracy of the degradation model makes it suitable for implementation in circuit simulation tools. The impact of the hot-carriers on a CMOS inverter is simulated using HSPICE.

International audience; The hot-carrier reliability of a 0.25μm CMOS technology with a 5nm-thick gate-oxide is studied from low (−40°C) to high temperature (125°C). Channel hot-carriers are investigated using DC and AC experiments on single transistors and on ring oscillators. Turn-around effects are observed in the degradation of the ring oscillator frequency at short times when P-MOSFET's degradation totally compensate the N-MOSFET's current reduction. As the electron trapping becomes much less efficient in thin gate-oxide P-MOSFET's with respect to field enhanced detrapping, the influence of the generated interface traps dominates leading to a cumulative current reduction in both device types at long stress time which results in a reduction of the oscillator frequency. The degradation behavior of the oscillator frequency exhibits a clear dependence on the P-MOSFET channel-width and on temperature as negative bias temperature instability occurs at 125°C during the high state in P-MOSFET's and the field-assisted discharge of electron traps occurs at −40°C.

International audience; AC stressing is investigated to determine the hot-carrier reliability in a 0.5 μm CMOS technology and is interpreted by a quasi-static model based on distinct damage mechanisms. The hot-carrier dependence of n-MOSFETs operating in pass-transistor configurations is carefully studied as a function of the propagation time and geometry. It is shown that device degradation may exhibit in some cases a strong dependence on the propagation time and clearly differs from the simple case of inverter operation.

International audience; This paper presents a theoretical framework about interface states creation rate from SiAH bond breaking at the Si/SiO2 interface during Hot Carrier (HC) stress. It involves two mains mechanisms of bond breaking through incident carriers, either being very energetic or very numerous but less energetic. This concept allows physical modeling of the reliability of MOS transistors, for different HC stress conditions. Simulation is validated by measurement of both defect lateral profiles and degradation of MOS parameters. This poses a general framework for the study of HC degradation at defect level

International audience; This paper presents a theoretical framework about interface state creation rate from Si–H bonds atthe Si/SiO2 interface. It includes three main ways of bond breaking. In the first case, the bond canbe broken, thanks to the bond ground state rising with an electrical field. In two other cases, incidentcarriers will play the main role either if there are very energetic or very numerous but less energetic.This concept allows one to physically model the reliability of metal oxide semiconductor field effecttransistors, and particularly negative bias temperature instability permanent part, and channel hotcarrier to cold carrier damage.

International audience; An overview of evolution of transistor parameters under negative bias temperature instability stress conditions commonly observed in p-MOSFETs in recent technologies is presented. The physical mechanisms of the degradation as well as the different defects involved have been discussed according to a systematic set of experiments with different stress conditions. According to our findings, a physical model is proposed which could be used to more accurately predict the transistor degradation. Finally, the influence of different process splits as the gate oxide nitridation, the nitrogen content, the source/drain implant and poly doping level on the NBTI degradation is investigated and discussed with our present understanding.

International audience; Hot-carrier reliability is studied in core logic PMOSFETs with a thin gate-oxide (Tox=2 nm) and in Input/Output PMOSFETs with a thick gate-oxide (6.5 nm) used for systems on chip applications. Hot-hole (HH) injections are found to play a more important role in the injection mechanisms and in the degradation efficiency. This depends on the technology node for stressing voltage conditions corresponding to channel hot-hole injections, i.e. closer to the supply voltage than the other voltage condition. Distinct mechanisms of carrier injections and hot-carrier degradation are found in core devices used for high speed (HS) and low leakage (LL) applications where the hole tunneling current dominates at low voltages while the electron valence band tunneling from the gate occurs at gate-voltages above −1.8 V. Devices with Tox=6.5 nm have shown the existence of a thermionic hot-hole gate-current which is directly measured at larger voltages. This is related to the increase in the surface doping, the thinning of the drain junction depth and the location of the hot-carrier generation rate which is closer to the interface. Results show that hole injections worsen the hot-carrier damage in thin and thick gate-oxides which are both distinguished by the effects of the interface trap generation, the permanent hole trapping and the hole charging–discharging from slow traps using alternated stressing in thin gate-oxides. This consequently leads to a significant lifetime increase in 2 nm HS, LL devices with respect to 6.5 nm Input/Output devices explained by the dominant effect of the fast interface trap generation due to the hole discharge from slow traps and bulk oxide traps in 2 nm devices at the tunneling distance of the interface.

The hot carrier (HC) reliability has been investigated in MOSFETs with ultra-thin SiO 2 gate-oxide ranging from T ox =3.5 to 1.2 nm and in high speed CMOS technologies in order to identify the worst-case of HC injections. Distinctions are obtained between the influence of the T ox thinning and the shrink of the gate-length with L G ranging from 0.25 to 0.1 μm. Results show that the worst-case of HC damage can be different from the bias condition of the maximum substrate current (IB) in N-channel devices and of the hot electron (HE) injections in P-channel devices with the T ox and L G margin. It is shown that the interface trap generation (Δ N it ) has become the main damage mechanism at long term with the use of the correlation between charge pumping analysis and drain current reduction. We focus on the hole injection efficiency, the extension of the degraded region (Δ L ) with the L G reduction and the influence of the carrier energy which all participate to the degradation of ultra-thin gate-oxide MOSFETs submitted to carrier injections.

International audience; Carrier injection mechanisms have been compared in surface p-channel metal–oxide–semiconductor field-effect transistors with a 2.1 nm thick gate-oxide. Currents as a function of voltage, I(V), were correlated with a corrected charge-pumping analysis taking into account the tunneling components. Channel hot-hole injection at the gate and drain voltages, |VGS| >=|VDS|, induces damage even at low stress voltage (

The transistor performances and hot-carrier reliability in n-MOSFETs are investigated at high temperature in the range 25‐125 8C. A careful analysis of the temperature dependence of the device parameters shows that transistor performances are significantly reduced and that the Fermi potential, the mobility and current reductions, contribute to decrease the device sensitivity to the hot-carrier damage at high temperature. DiAerent degradation behaviors are found between DC and AC stressing depending on the degradation mechanisms i.e. whether the interface trap generation or oxide charge trapping dominates which consequently exhibits a strong temperature dependence through their magnitude and localization. It is pointed out that the reduction of the ionization rate significantly impacts the degradation behaviors at elevated temperature. Even if the amount of generated damage is slightly larger than what eAectively influences the transistor characteristics, the parameter insensitivity to given at high temperature improves the transistor reliability. This improvement is determined in the value of the device lifetime at 125 and 70 8C using inverter and pass transistor operations in a 0.35 mm LDD complementary metal-oxide semiconductor (CMOS) technology suitable for 3.3 V operation. # 1999 Elsevier Science Ltd. All rights reserved.

International audience; We review the hot-carrier injection phenomena in gate-oxide and the related degradation in silicon MOSFETs. We discuss the basic degradation mechanisms and the nature of the created defects by carrier injections through the gate-oxide. Emphasis is put on the discussion of dynamic hot-carrier injections in MOSFETs and on the stress induced leakage currents in very thin (

The hot carrier degradation of large-angle-tilt implanted drain (LATID) and standard LDD N-MOSFETs has been investigated thoroughly using the combination of I-V characterization, charge-pumping and profiling of the damaged region. Although the LATID structure exhibits a good current drivability and net improvement in the hot-carrier immunity, the gate-voltage dependence of the transistor degradation shows significant differences compared to the LDD structure. The distinct time-dependence of the transconductance degradation and the filling of acceptor-like (neutral) oxide traps were emphasized. It is shown that the degradation in LATID is less sensitive to the gate-voltage V g governing hole or electron injection, which leads to a “flat” V g -dependence where holes are less efficient to create acceptor-like oxide traps. The charge-pumping analysis has shown a similar V g -dependence between the interface trap generation and the acceptor-like oxide traps in both structures. Less positive and negative trapped charges are found in LATID than in LDD with a larger difference in the high V g -stress region (where the trapping of negative charge largely dominates the interface trap generation). This was confirmed by profiling measurements which have shown that the density of the negative trapped charges in LATID is one half of that in LDD, but in contrast presents a significant extension from the n -region into the channel. Finally, though the LATID N-MOSFET is one of the best structures able to exceed a DC lifetime of 10 years, lifetime experiments have shown that acceptor-like oxide traps clearly reduce the device lifetime in LATID in the same way as in LDD, which could lead to enhanced hot-carrier degradation in some cases of AC operation for these structures.

International audience; New degradation mechanisms are found during AC pass transistor operation combined with charge-pumping analysis in thin gate-oxide p-MOSFET's. The electron trapping is clearly saturating and in some cases can be completely suppressed by the subsequent detrapping phases leading to the strong influence of donor type interface traps alone, as no positive oxide charge is detected in a moderate field range. These influences reduce the transistor performances as in the case of n-MOSFET's and become more pronounced in 7nm gate-oxide, showing a large dependence with the propagation delay. This is partly due to the low sensitivity to the negative trapped charge with respect to the increasing proportion of the detrapped charge and of generated interface traps in 7nm gate-oxide surface-channel p-MOSFET's.